ANALOG DEVICES ADSP-BF50x Service Manual

ADSP-BF50x Blackfin® Processor

Hardware Reference

Revision 1.0, December 2010

Part Number

82-100101-01

Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CROSSCORE, EZ-KIT Lite, SHARC, TigerSHARC, and VisualDSP++ are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of their respective owners.

PREFACE

Purpose of This Manual .................................................................. li

Intended Audience .......................................................................... li

Manual Contents ........................................................................... lii

What’s New in This Manual ........................................................... lv

Technical or Customer Support ..................................................... lvi

Supported Processors .................................................................... lvii

Product Information .................................................................... lvii

Analog Devices Web Site ....................................................... lviii

VisualDSP++ Online Documentation .................................... lviii

Technical Library CD .............................................................. lix

Social Networking Web Sites .................................................... lx

Notation Conventions .................................................................... lx

INTRODUCTION

General Description of Processor ................................................... 1-1

Portable Low-Power Architecture ............................................. 1-3

System Integration ................................................................... 1-3

Peripherals .................................................................................... 1-4

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Memory Architecture .................................................................... 1-4

Internal Memory ..................................................................... 1-6

External Memory .................................................................... 1-6

I/O Memory Space .................................................................. 1-7

DMA Support .............................................................................. 1-8

General-Purpose I/O (GPIO) ........................................................ 1-9

Two-Wire Interface ..................................................................... 1-10

RSI Interface .............................................................................. 1-11

General-Purpose (GP) Counter ................................................... 1-12

3-Phase PWM Unit .................................................................... 1-13

Parallel Peripheral Interface ......................................................... 1-14

SPORT Controllers .................................................................... 1-16

Serial Peripheral Interface (SPI) Ports .......................................... 1-18

Timers ....................................................................................... 1-18

UART Ports ............................................................................... 1-19

Controller Area Network (CAN) Interface ................................... 1-21

ACM Interface ........................................................................... 1-22

Internal ADC ............................................................................. 1-22

Watchdog Timer ......................................................................... 1-23

Clock Signals .............................................................................. 1-23

Dynamic Power Management ..................................................... 1-24

Full-On Operating Mode—Maximum Performance ............... 1-24

Active Operating Mode—Moderate Dynamic Power Savings .. 1-24

Sleep Operating Mode—High Dynamic Power Savings .......... 1-25

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Deep Sleep Operating Mode—Maximum Dynamic

Power Savings ..................................................................... 1-26

Hibernate State—Maximum Static Power Savings .................. 1-26

Instruction Set Description ......................................................... 1-27

Development Tools ..................................................................... 1-28

MEMORY

Memory Architecture .................................................................... 2-1

L1 Instruction SRAM ................................................................... 2-2

L1 Data SRAM ............................................................................. 2-3

L1 Data Cache .............................................................................. 2-4

Boot ROM ................................................................................... 2-4

External Memory .......................................................................... 2-4

Processor-Specific MMRs .............................................................. 2-5

DMEM_CONTROL Register ................................................. 2-5

DTEST_COMMAND Register ............................................... 2-6

CHIP BUS HIERARCHY

Chip Bus Hierarchy Overview ....................................................... 3-1

Interface Overview ........................................................................ 3-2

Internal Clocks ........................................................................ 3-2

Core Bus Overview .................................................................. 3-4

Peripheral Access Bus (PAB) ..................................................... 3-5

PAB Arbitration .................................................................. 3-6

PAB Agents (Masters, Slaves) ............................................... 3-6

PAB Performance ................................................................ 3-7

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DMA Access Bus (DAB), DMA Core Bus (DCB), DMA

External Bus (DEB) .............................................................. 3-7

DAB, DCB, and DEB Arbitration ...................................... 3-7

DAB Bus Agents (Masters) .................................................. 3-9

DAB, DCB, and DEB Performance ..................................... 3-9

External Access Bus (EAB) .................................................... 3-10

Arbitration of the External Bus .............................................. 3-10

DEB/EAB Performance ......................................................... 3-10

SYSTEM INTERRUPTS

Specific Information for the ADSP-BF50x .................................... 4-1

Overview ...................................................................................... 4-1

Features .................................................................................. 4-2

Description of Operation .............................................................. 4-2

Events and Sequencing ............................................................ 4-2

System Peripheral Interrupts .................................................... 4-4

Programming Model ..................................................................... 4-7

System Interrupt Initialization ................................................. 4-8

System Interrupt Processing Summary ..................................... 4-8

System Interrupt Controller Registers .......................................... 4-10

System Interrupt Assignment (SIC_IAR) Register .................. 4-11

System Interrupt Mask (SIC_IMASK) Register ...................... 4-12

System Interrupt Status (SIC_ISR) Register ........................... 4-12

System Interrupt Wakeup-Enable (SIC_IWR) Register ........... 4-12

Programming Examples .............................................................. 4-13

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Clearing Interrupt Requests ................................................... 4-13

Unique Information for the ADSP-BF50x Processor .................... 4-15

Interfaces .............................................................................. 4-15

System Peripheral Interrupts .................................................. 4-18

EXTERNAL BUS INTERFACE UNIT

EBIU Overview ............................................................................ 5-1

Block Diagram ........................................................................ 5-3

Internal Memory Interfaces ...................................................... 5-4

Registers .................................................................................. 5-4

Error Detection ....................................................................... 5-5

AMC Overview and Features ......................................................... 5-5

Features ................................................................................... 5-6

Asynchronous Memory Interface .............................................. 5-6

Asynchronous Memory Address Decode .............................. 5-6

AMC Description of Operation ..................................................... 5-6

Avoiding Bus Contention ........................................................ 5-6

AMC Programming Model ............................................................ 5-7

EBIU Registers ............................................................................. 5-9

EBIU_AMGCTL Register ..................................................... 5-10

EBIU_AMBCTL Register ...................................................... 5-11

EBIU_MODECTL Register .................................................. 5-12

EBIU_FCTL Register ............................................................ 5-12

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INTERNAL FLASH MEMORY

Overview ...................................................................................... 6-1

Command Interface to Internal Flash Memory .............................. 6-6

Command Interface – Standard Commands ............................ 6-7

Read Array Command ....................................................... 6-7

Read Status Register Command ......................................... 6-7

Read Electronic Signature Command ................................. 6-8

Read CFI Query Command ............................................... 6-9

Clear Status Register Command ......................................... 6-9

Block Erase Command .................................................... 6-10

Program Command ......................................................... 6-11

Program/Erase Suspend Command .................................. 6-11

Program/Erase Resume Command ................................... 6-12

Protection Register Program Command ............................ 6-13

The Set Configuration Register Command ....................... 6-14

Block Lock Command ..................................................... 6-14

Block Unlock Command ................................................. 6-15

Block Lock-Down Command .......................................... 6-15

Status Register ..................................................................... 6-18

Program/Erase Controller Status Bit (SR7) ....................... 6-19

Erase Suspend Status Bit (SR6) ........................................ 6-20

Erase Status Bit (SR5) ...................................................... 6-20

Program Status Bit (SR4) ................................................. 6-21

VPP Status Bit (SR3) ........................................................ 6-21

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Program Suspend Status Bit (SR2) .................................... 6-22

Block Protection Status Bit (SR1) ..................................... 6-22

Bank Write Status Bit (SR0) ............................................. 6-22

Configuration Register ......................................................... 6-24

Read Select Bit (CR15) .................................................... 6-24

X Latency Bits (CR13-CR11) ........................................... 6-25

Wait Polarity Bit (CR10) .................................................. 6-25

Data Output Configuration Bit (CR9) ............................. 6-26

Wait Configuration Bit (CR8) .......................................... 6-27

Burst Type Bit (CR7) ....................................................... 6-27

Valid Clock Edge Bit (CR6) ............................................. 6-27

Wrap Burst Bit (CR3) ...................................................... 6-27

Burst Length Bits (CR2-CR0) .......................................... 6-27

Read Modes ......................................................................... 6-33

Asynchronous Read Mode ................................................ 6-33

Synchronous Burst Read Mode ......................................... 6-33

Synchronous Burst Read Suspend ..................................... 6-35

Single Synchronous Read Mode ........................................ 6-36

Dual Operations and Multiple Bank Architecture .................. 6-36

Block Locking ...................................................................... 6-38

Reading a Block’s Lock Status ........................................... 6-39

Locked State .................................................................... 6-39

Unlocked State ................................................................. 6-39

Lock-Down State ............................................................. 6-40

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Locking Operations During Erase Suspend ....................... 6-40

Block Address Table .................................................................... 6-42

Common Flash Interface ............................................................ 6-45

Flowcharts and Pseudo Codes .................................................... 6-56

Command Interface State Tables ................................................ 6-68

Internal Flash Memory Programming Guidelines ......................... 6-77

Bringing Internal Flash Memory Out of Reset ........................ 6-78

Timing Configurations for Setting the Internal Flash

Memory in Asynchronous Read Mode ................................ 6-79

Timing Configurations for Setting the Internal Flash

Memory for Write Accesses ................................................. 6-80

Enabling the Program or Erasure of Internal Flash

Memory Blocks .................................................................. 6-82

Configuring Internal Flash Memory for Synchronous

Burst Read Mode ............................................................... 6-83

Supported Configuration Register Combinations in

ADSP-BF50xF Processors .............................................. 6-84

Configuring the EBIU for Synchronous Read Mode .......... 6-85

Unsupported Programming Practices in Flash ........................ 6-87

Internal Flash Memory Control Registers .................................... 6-88

Internal Flash Memory Control

(FLASH_CONTROL) Register .......................................... 6-88

Internal Flash Memory Control Set

(FLASH_CONTROL_SET) Register ................................. 6-91

Internal Flash Memory Control Clear

(FLASH_CONTROL_CLEAR) Register ............................ 6-91

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DIRECT MEMORY ACCESS

Specific Information for the ADSP-BF50x ..................................... 7-1

Overview and Features .................................................................. 7-2

DMA Controller Overview ............................................................ 7-4

External Interfaces ................................................................... 7-4

Internal Interfaces ................................................................... 7-4

Peripheral DMA ...................................................................... 7-5

Memory DMA ........................................................................ 7-6

Handshaked Memory DMA (HMDMA) Mode ................... 7-8

Modes of Operation ...................................................................... 7-9

Stop Mode ........................................................................ 7-11

Autobuffer Mode .............................................................. 7-11

Two-Dimensional DMA Operation ........................................ 7-11

Examples of Two-Dimensional DMA ................................ 7-13

Descriptor-based DMA Operation ......................................... 7-14

Descriptor List Mode ........................................................ 7-15

Descriptor Array Mode ..................................................... 7-15

Variable Descriptor Size .................................................... 7-15

Mixing Flow Modes .......................................................... 7-17

Functional Description ............................................................... 7-17

DMA Operation Flow ........................................................... 7-17

DMA Startup .................................................................... 7-17

DMA Refresh ................................................................... 7-23

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Work Unit Transitions ...................................................... 7-25

DMA Transmit and MDMA Source .............................. 7-26

DMA Receive ............................................................... 7-27

Stopping DMA Transfers .................................................. 7-29

DMA Errors (Aborts) ............................................................ 7-30

DMA Control Commands .................................................... 7-32

Restrictions ...................................................................... 7-35

Transmit Restart or Finish ............................................. 7-35

Receive Restart or Finish ............................................... 7-36

Handshaked Memory DMA Operation .................................. 7-37

Pipelining DMA Requests ................................................. 7-38

HMDMA Interrupts ......................................................... 7-40

DMA Performance ................................................................ 7-41

DMA Throughput ............................................................ 7-42

Memory DMA Timing Details .......................................... 7-45

Static Channel Prioritization ............................................. 7-45

Temporary DMA Urgency ................................................ 7-45

Memory DMA Priority and Scheduling ............................. 7-47

Traffic Control ................................................................. 7-49

Programming Model ................................................................... 7-51

Synchronization of Software and DMA .................................. 7-51

Single-Buffer DMA Transfers ............................................ 7-53

Continuous Transfers Using Autobuffering ........................ 7-54

Descriptor Structures ........................................................ 7-56

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Descriptor Queue Management ......................................... 7-57

Descriptor Queue Using Interrupts on Every Descriptor 7-58

Descriptor Queue Using Minimal Interrupts .................. 7-59

Software-Triggered Descriptor Fetches ............................... 7-61

DMA Registers ........................................................................... 7-63

DMA Channel Registers ........................................................ 7-64

DMA Peripheral Map Registers (DMAx_PERIPHERAL

_MAP/MDMA_yy_PERIPHERAL_MAP) ..................... 7-67

DMA Configuration Registers

(DMAx_CONFIG/MDMA_yy_CONFIG) .................... 7-68

DMA Interrupt Status Registers

(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 7-72

DMA Start Address Registers

(DMAx_START_ADDR/MDMA_yy_START_ADDR) .. 7-75

DMA Current Address Registers

(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) .... 7-76

DMA Inner Loop Count Registers

(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 7-76

DMA Current Inner Loop Count Registers

(DMAx_CURR_X_COUNT

/MDMA_yy_CURR_X_COUNT) ................................. 7-77

DMA Inner Loop Address Increment Registers

(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 7-78

DMA Outer Loop Count Registers

(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .............. 7-79

DMA Current Outer Loop Count Registers

(DMAx_CURR_Y_COUNT/

MDMA_yy_CURR_Y_COUNT) .................................. 7-80

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DMA Outer Loop Address Increment Registers

(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 7-80

DMA Next Descriptor Pointer Registers

(DMAx_NEXT_DESC_PTR/

MDMA_yy_NEXT_DESC_PTR) .................................. 7-81

DMA Current Descriptor Pointer Registers

(DMAx_CURR_DESC_PTR/

MDMA_yy_CURR_DESC_PTR) ................................. 7-83

HMDMA Registers ............................................................... 7-85

Handshake MDMA Control Registers

(HMDMAx_CONTROL) ............................................. 7-85

Handshake MDMA Initial Block Count Registers

(HMDMAx_BCINIT) ................................................... 7-88

Handshake MDMA Current Block Count Registers

(HMDMAx_BCOUNT) ............................................... 7-88

Handshake MDMA Current Edge Count Registers

(HMDMAx_ECOUNT) ............................................... 7-89

Handshake MDMA Initial Edge Count Registers

(HMDMAx_ECINIT) ................................................... 7-90

Handshake MDMA Edge Count Urgent Registers

(HMDMAx_ECURGENT) ........................................... 7-90

Handshake MDMA Edge Count Overflow Interrupt

Registers (HMDMAx_ECOVERFLOW) ........................ 7-91

DMA Traffic Control Registers

(DMA_TC_PER and DMA_TC_CNT) ............................. 7-91

DMA_TC_PER Register .................................................. 7-92

DMA_TC_CNT Register ................................................. 7-92

Programming Examples .............................................................. 7-94

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Initializing Descriptors in Memory ........................................ 7-97

Software-Triggered Descriptor Fetch Example ...................... 7-100

Handshaked Memory DMA Example ................................... 7-103

Unique Information for the ADSP-BF50x Processor .................. 7-105

Static Channel Prioritization ................................................ 7-107

DYNAMIC POWER MANAGEMENT

Phase Locked Loop and Clock Control .......................................... 8-1

PLL Overview ......................................................................... 8-2

PLL Clock Multiplier Ratios .................................................... 8-4

Core Clock/System Clock Ratio Control ............................. 8-5

Dynamic Power Management Controller ....................................... 8-7

Operating Modes ..................................................................... 8-8

Dynamic Power Management Controller States ........................ 8-9

Full-On Mode .................................................................... 8-9

Active Mode ..................................................................... 8-10

Sleep Mode ....................................................................... 8-10

Deep Sleep Mode .............................................................. 8-10

Hibernate State ................................................................. 8-11

Operating Mode Transitions .................................................. 8-12

Programming Operating Mode Transitions ............................. 8-15

Dynamic Supply Voltage Control ........................................... 8-17

Power Supply Management .................................................... 8-17

Changing Voltage .............................................................. 8-17

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Powering Down the Core (Hibernate State) ....................... 8-19

PLL and VR Registers ................................................................. 8-20

PLL_DIV Register ................................................................ 8-21

PLL_CTL Register ................................................................ 8-22

PLL_STAT Register .............................................................. 8-22

PLL_LOCKCNT Register ..................................................... 8-23

VR_CTL Register ................................................................. 8-23

System Control ROM Function .................................................. 8-24

Programming Model ............................................................. 8-26

Accessing the System Control ROM Function in C/C++ ........ 8-26

Accessing the System Control ROM Function in Assembly .... 8-27

Programming Examples .............................................................. 8-30

Full-on Mode to Active Mode and Back ................................. 8-32

Transition to Sleep Mode or Deep Sleep Mode ....................... 8-33

Set Wakeup Events and Enter Hibernate State ........................ 8-35

Perform a System Reset or Soft-Reset ..................................... 8-37

In Full-on Mode, Change VCO Frequency, Core Clock

Frequency, and System Clock Frequency ............................. 8-38

Changing Voltage Levels ....................................................... 8-40

GENERAL-PURPOSE PORTS

Overview ...................................................................................... 9-1

Features ........................................................................................ 9-1

Interface Overview ....................................................................... 9-3

External Interface .................................................................... 9-3

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Port F Structure .................................................................. 9-3

Port G Structure ................................................................. 9-5

Port H Structure ................................................................. 9-6

Input Tap Considerations .................................................... 9-6

PWM Unit Considerations .................................................. 9-8

RSI Considerations ............................................................. 9-8

GP Counter Considerations ................................................ 9-9

SPI Considerations .............................................................. 9-9

Internal Interfaces ................................................................... 9-9

GP Timer Interaction With Other Blocks .......................... 9-10

Buffered CLKIN (CLKBUF) ......................................... 9-10

GP Counter .................................................................. 9-10

PPI ............................................................................... 9-10

UART ........................................................................... 9-10

SPORT ......................................................................... 9-11

ACM ............................................................................ 9-11

Performance/Throughput ...................................................... 9-12

Description of Operation ............................................................ 9-12

Operation ............................................................................. 9-12

General-Purpose I/O Modules ............................................... 9-13

GPIO Interrupt Processing .................................................... 9-16

Programming Model ................................................................... 9-22

Hysteresis Control ...................................................................... 9-24

PORTx Hysteresis (PORTx_HYSTERESIS) Register ............. 9-24

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Drive Strength Control ............................................................... 9-26

Memory-Mapped GPIO Registers ............................................... 9-27

Port Multiplexer Control Registers (PORTx_MUX) ............... 9-27

Function Enable Registers (PORTx_FER) ............................. 9-30

GPIO Direction Registers (PORTxIO_DIR) ......................... 9-30

GPIO Input Enable Registers (PORTxIO_INEN) ................. 9-31

GPIO Data Registers (PORTxIO) ......................................... 9-31

GPIO Set Registers (PORTxIO_SET) ................................... 9-32

GPIO Clear Registers (PORTxIO_CLEAR) ........................... 9-32

GPIO Toggle Registers (PORTxIO_TOGGLE) ..................... 9-33

GPIO Polarity Registers (PORTxIO_POLAR) ....................... 9-33

Interrupt Sensitivity Registers (PORTxIO_EDGE) ................ 9-34

GPIO Set on Both Edges Registers (PORTxIO_BOTH) ........ 9-34

GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ....... 9-35

GPIO Mask Interrupt Set Registers

(PORTxIO_MASKA/B_SET) ............................................ 9-36

GPIO Mask Interrupt Clear Registers

(PORTxIO_MASKA/B_CLEAR) ....................................... 9-38

GPIO Mask Interrupt Toggle Registers

(PORTxIO_MASKA/B_TOGGLE) .................................... 9-40

Programming Examples .............................................................. 9-41

GENERAL-PURPOSE TIMERS

Specific Information for the ADSP-BF50x .................................. 10-1

Overview .................................................................................... 10-2

External Interface .................................................................. 10-3

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Internal Interface ................................................................... 10-4

Description of Operation ............................................................ 10-4

Interrupt Processing .............................................................. 10-5

Illegal States .......................................................................... 10-7

Modes of Operation .................................................................. 10-10

Pulse Width Modulation (PWM_OUT) Mode ..................... 10-10

Output Pad Disable ........................................................ 10-12

Single Pulse Generation ................................................... 10-12

Pulse Width Modulation Waveform Generation ............... 10-13

PULSE_HI Toggle Mode ................................................ 10-15

Externally Clocked PWM_OUT ..................................... 10-19

Using PWM_OUT Mode With the PPI .......................... 10-20

Stopping the Timer in PWM_OUT Mode ....................... 10-21

Pulse Width Count and Capture (WDTH_CAP) Mode ....... 10-23

Autobaud Mode .............................................................. 10-31

External Event (EXT_CLK) Mode ....................................... 10-31

Programming Model ................................................................. 10-33

Timer Registers ......................................................................... 10-34

Timer Enable Register (TIMER_ENABLE) .......................... 10-35

Timer Disable Register (TIMER_DISABLE) ........................ 10-36

Timer Status Register (TIMER_STATUS) ............................ 10-38

Timer Configuration Register (TIMER_CONFIG) .............. 10-40

Timer Counter Register (TIMER_COUNTER) ................... 10-41

Timer Period (TIMER_PERIOD) and Timer

Width (TIMER_WIDTH) Registers ................................. 10-42

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Summary ............................................................................ 10-45

Programming Examples ............................................................ 10-48

Unique Information for the ADSP-BF50x Processor .................. 10-57

Interface Overview .............................................................. 10-57

External Interface ........................................................... 10-57

CORE TIMER

Specific Information for the ADSP-BF50x .................................. 11-1

Overview and Features ................................................................ 11-1

Timer Overview ......................................................................... 11-2

External Interfaces ................................................................ 11-2

Internal Interfaces ................................................................. 11-3

Description of Operation ............................................................ 11-3

Interrupt Processing .............................................................. 11-3

Core Timer Registers .................................................................. 11-4

Core Timer Control Register (TCNTL) ................................. 11-5

Core Timer Count Register (TCOUNT) ............................... 11-5

Core Timer Period Register (TPERIOD) ............................... 11-6

Core Timer Scale Register (TSCALE) .................................... 11-7

Programming Examples .............................................................. 11-7

Unique Information for the ADSP-BF50x Processor .................... 11-9

WATCHDOG TIMER

Specific Information for the ADSP-BF50x .................................. 12-1

Overview and Features ................................................................ 12-1

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Interface Overview ...................................................................... 12-3

External Interface .................................................................. 12-3

Internal Interface ................................................................... 12-3

Description of Operation ............................................................ 12-4

Watchdog Count (WDOG_CNT) Register ............................ 12-5

Watchdog Status (WDOG_STAT) Register ............................ 12-6

Watchdog Control (WDOG_CTL) Register ........................... 12-7

Programming Examples ............................................................... 12-8

Unique Information for the ADSP-BF50x Processor .................. 12-11

GENERAL-PURPOSE COUNTER

Specific Information for the ADSP-BF50x ................................... 13-1

Overview .................................................................................... 13-2

Features ...................................................................................... 13-2

Interface Overview ...................................................................... 13-3

Description of Operation ............................................................ 13-4

Quadrature Encoder Mode .................................................... 13-4

Binary Encoder Mode ............................................................ 13-5

Up/Down Counter Mode ...................................................... 13-6

Direction Counter Mode ....................................................... 13-6

Timed Direction Mode .......................................................... 13-7

Functional Description ............................................................... 13-7

Input Noise Filtering (Debouncing) ....................................... 13-7

Zero Marker (Push Button) Operation ................................... 13-9

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Boundary Comparison Modes ............................................. 13-10

Control and Signaling Events .............................................. 13-11

Illegal Gray/Binary Code Events ..................................... 13-12

Up/Down Count Events ................................................. 13-12

Zero-Count Events ......................................................... 13-13

Overflow Events ............................................................. 13-13

Boundary Match Events .................................................. 13-13

Zero Marker Events ........................................................ 13-14

Capturing Timing Information ............................................ 13-14

Capturing Time Interval Between

Successive Counter Events ............................................ 13-14

Capturing Counter Interval and

CNT_COUNTER Read Timing .................................. 13-15

Programming Model ................................................................. 13-18

Registers ................................................................................... 13-18

Counter Module Register Overview ..................................... 13-18

Counter Configuration Register (CNT_CONFIG) .............. 13-19

Counter Interrupt Mask Register (CNT_IMASK) ................ 13-20

Counter Status Register (CNT_STATUS) ............................ 13-20

Counter Command Register (CNT_COMMAND) ............. 13-21

Counter Debounce Register (CNT_DEBOUNCE) .............. 13-23

Counter Count Value Register (CNT_COUNTER) ............ 13-24

Counter Boundary Registers (CNT_MIN and CNT_MAX) . 13-25

Programming Examples ............................................................ 13-27

Unique Information for the ADSP-BF50x Processor .................. 13-37

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PWM CONTROLLER

Specific Information for the ADSP-BF50x ................................... 14-1

Overview .................................................................................... 14-1

General Operation ...................................................................... 14-8

Functional Description ............................................................... 14-9

Three-Phase PWM Timing Unit and Dead Time

Control Unit .................................................................... 14-10

PWM Switching Frequency (PWM_TM) Register ................ 14-10

PWM Switching Dead Time (PWM_DT) Register ............... 14-12

PWM Operating Mode (PWM_CTRL and PWM_STAT)

Registers ........................................................................... 14-13

PWM Duty Cycle (PWM_CHA, PWM_CHB,

and PWM_CHC) Registers .............................................. 14-14

Special Consideration for PWM Operation in

Over-Modulation ............................................................. 14-20

Three-Phase PWM Timing Unit Operation .......................... 14-22

Effective PWM Accuracy ..................................................... 14-24

Switched Reluctance Mode .................................................. 14-25

Output Control Unit ........................................................... 14-25

Crossover Feature ............................................................ 14-25

Mode Bits (POLARITY and SRMODE) .......................... 14-26

Output Enable Function ................................................. 14-26

Brushless DC Motor (Electronically Commutated Motor)

Control ........................................................................ 14-27

Gate Drive Unit .................................................................. 14-29

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High-Frequency Chopping ............................................. 14-29

PWM Polarity Control ................................................... 14-30

Output Control Feature Precedence ..................................... 14-31

Switched Reluctance (SR) Mode .......................................... 14-31

PWM Sync Operation ......................................................... 14-34

Internal PWM SYNC Generation ................................... 14-35

External PWM SYNC Generation ................................... 14-35

PWM Shutdown and Interrupt Control Unit ....................... 14-36

PWM Registers ........................................................................ 14-37

PWM Control (PWM_CTRL) Register ............................... 14-38

PWM Status (PWM_STAT) Register ................................... 14-40

PWM Period (PWM_TM) Register ..................................... 14-41

PWM Dead Time (PWM_DT) Register .............................. 14-42

PWM Chopping Control (PWM_GATE) Register ............... 14-42

PWM Channel A, B, C Duty Control

(PWM_CHA, PWM_CHB, PWM_CHC) Registers ......... 14-43

PWM Crossover and Output Enable (PWM_SEG)

PWM Sync Pulse Width Control (PWM_SYNCWT)

PWM Channel AL, BL, CL Duty Control

(PWM_CHAL, PWM_CHBL, PWM_CHCL) Registers ... 14-47

PWM Low Side Invert (PWM_LSI) Register ....................... 14-49

PWM Simulation Status (PWM_STAT2) Register ............... 14-49

Unique Information for the ADSP-BF50x Processor .................. 14-50

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UART PORT CONTROLLERS

Overview .................................................................................... 15-1

Features ................................................................................. 15-2

Interface Overview ...................................................................... 15-3

External Interface .................................................................. 15-3

Internal Interface ................................................................... 15-5

Description of Operation ............................................................ 15-5

UART Transfer Protocol ........................................................ 15-6

UART Transmit Operation .................................................... 15-7

UART Receive Operation ...................................................... 15-8

Hardware Flow Control ....................................................... 15-10

IrDA Transmit Operation .................................................... 15-13

IrDA Receive Operation ...................................................... 15-13

Interrupt Processing ............................................................ 15-15

Bit Rate Generation ............................................................. 15-18

Autobaud Detection ............................................................ 15-20

Programming Model ................................................................. 15-22

Non-DMA Mode ................................................................ 15-22

DMA Mode ........................................................................ 15-23

Mixing Modes ..................................................................... 15-25

UART Registers ........................................................................ 15-26

UARTx_LCR Registers ........................................................ 15-28

UARTx_MCR Registers ...................................................... 15-31

UARTx_LSR Registers ........................................................ 15-33

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Contents

UARTx_MSR Registers ....................................................... 15-36

UARTx_THR Registers ...................................................... 15-37

UARTx_RBR Registers ....................................................... 15-38

UARTx_DLL and UARTx_DLH Registers .......................... 15-43

UARTx_SCR Registers ........................................................ 15-44

UARTx_GCTL Registers .................................................... 15-45

Programming Examples ............................................................ 15-46

TWO WIRE INTERFACE CONTROLLER

Specific Information for the ADSP-BF50x .................................. 16-1

Overview .................................................................................... 16-2

Interface Overview ..................................................................... 16-3

External Interface .................................................................. 16-4

Serial Clock Signal (SCL) ................................................. 16-4

Serial Data Signal (SDA) .................................................. 16-4

TWI Pins ......................................................................... 16-5

Internal Interfaces ................................................................. 16-5

Description of Operation ............................................................ 16-6

TWI Transfer Protocols ......................................................... 16-6

Clock Generation and Synchronization ............................. 16-7

Bus Arbitration ................................................................. 16-8

Start and Stop Conditions ................................................. 16-8

General Call Support ........................................................ 16-9

Fast Mode ...................................................................... 16-10

Functional Description ............................................................. 16-10

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Contents

General Setup ...................................................................... 16-10

Slave Mode .......................................................................... 16-11

Master Mode Clock Setup ................................................... 16-12

Master Mode Transmit ........................................................ 16-12

Master Mode Receive ........................................................... 16-14

Repeated Start Condition ................................................ 16-15

Transmit/Receive Repeated Start Sequence ................... 16-15

Receive/Transmit Repeated Start Sequence ................... 16-16

Clock Stretching ............................................................. 16-17

Clock Stretching During FIFO Underflow ....................... 16-17

Clock Stretching During FIFO Overflow ......................... 16-19

Clock Stretching During Repeated Start Condition .......... 16-20

Programming Model ................................................................. 16-22

TWI CONTROL Register (TWI_CONTROL) ................... 16-24

SCL Clock Divider Register (TWI_CLKDIV) ...................... 16-25

TWI Slave Mode Control Register (TWI_SLAVE_CTL) ...... 16-26

TWI Slave Mode Address Register (TWI_SLAVE_ADDR) ... 16-28

TWI Slave Mode Status Register (TWI_SLAVE_STAT) ....... 16-28

TWI Master Mode Control Register

(TWI_MASTER_CTL) .................................................... 16-30

TWI Master Mode Address Register

(TWI_MASTER_ADDR) ................................................ 16-33

TWI Master Mode Status Register

(TWI_MASTER_STAT) .................................................. 16-34

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Contents

TWI FIFO Control Register (TWI_FIFO_CTL) ................. 16-37

TWI FIFO Status Register (TWI_FIFO_STAT) .................. 16-39

TWI FIFO Status ........................................................... 16-39

TWI Interrupt Mask Register (TWI_INT_MASK) .............. 16-40

TWI Interrupt Status Register (TWI_INT_STAT) .............. 16-41

TWI FIFO Transmit Data Single Byte

TWI FIFO Transmit Data Double Byte

TWI FIFO Receive Data Single Byte

TWI FIFO Receive Data Double Byte

Programming Examples ............................................................ 16-47

Master Mode Setup ............................................................. 16-47

Slave Mode Setup ................................................................ 16-52

Electrical Specifications ............................................................ 16-59

Unique Information for the ADSP-BF50x Processor .................. 16-59

CAN MODULE

Overview .................................................................................... 17-1

Interface Overview ..................................................................... 17-2

CAN Mailbox Area ............................................................... 17-4

CAN Mailbox Control .......................................................... 17-6

CAN Protocol Basics ............................................................. 17-7

CAN Operation ......................................................................... 17-9

xxviii ADSP-BF50x Blackfin Processor Hardware Reference

Contents

Bit Timing .......................................................................... 17-10

Transmit Operation ............................................................. 17-12

Retransmission ................................................................ 17-13

Single Shot Transmission ................................................. 17-14

Auto-Transmission .......................................................... 17-15

Receive Operation ............................................................... 17-15

Data Acceptance Filter .................................................... 17-18

Remote Frame Handling ................................................. 17-19

Watchdog Mode ............................................................. 17-19

Time Stamps ....................................................................... 17-20

Temporarily Disabling Mailboxes ......................................... 17-21

Functional Operation ................................................................ 17-22

CAN Interrupts ................................................................... 17-22

Mailbox Interrupts .......................................................... 17-23

Global CAN Status Interrupt .......................................... 17-23

Event Counter ..................................................................... 17-26

CAN Warnings and Errors ................................................... 17-27

Programmable Warning Limits ........................................ 17-28

CAN Error Handling ...................................................... 17-28

Error Frames ............................................................... 17-29

Error Levels ................................................................ 17-31

Debug and Test Modes ........................................................ 17-33

Low Power Features ............................................................. 17-37

CAN Built-In Suspend Mode .......................................... 17-37

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Contents

CAN Built-In Sleep Mode .............................................. 17-38

CAN Wakeup From Hibernate State ............................... 17-38

CAN Register Definitions ......................................................... 17-39

Global CAN Registers ......................................................... 17-43

CAN_CONTROL Register ............................................ 17-43

CAN_STATUS Register ................................................. 17-44

CAN_DEBUG Register .................................................. 17-45

CAN_CLOCK Register .................................................. 17-45

CAN_TIMING Register ................................................. 17-46

CAN_INTR Register ...................................................... 17-46

CAN_GIM Register ....................................................... 17-47

CAN_GIS Register ......................................................... 17-47

CAN_GIF Register ......................................................... 17-48

Mailbox/Mask Registers ...................................................... 17-48

CAN_AMxx Registers ..................................................... 17-48

CAN_MBxx_ID1 Registers ............................................ 17-52

CAN_MBxx_ID0 Registers ............................................ 17-54

CAN_MBxx_TIMESTAMP Registers ............................. 17-56

CAN_MBxx_LENGTH Registers ................................... 17-58

CAN_MBxx_DATAx Registers ....................................... 17-59

Mailbox Control Registers ................................................... 17-68

CAN_MCx Registers ...................................................... 17-68

CAN_MDx Registers ...................................................... 17-69

CAN_RMPx Register ..................................................... 17-70

xxx ADSP-BF50x Blackfin Processor Hardware Reference

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