Analog Devices ADSP-21MOD980N-000 Datasheet
a
MultiPort Internet
Gateway Processor
Preliminary Technical Data
PERFORMANCE FEATURES
Complete Single Device Multi-Port Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each DSP Can Implement two V.34/V.90 Data/Fax
Modem Channels (includes Datapump and
Controller)
Low Power Version: 640 MIPS Sustained Performance,
12.5 ns Instruction Time @ 1.9 Volts nominal
(internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Low Power Dissipation, 25 mW (typical) per Channel
Powerdown Mode Featuring Low CMOS Standby Power
Dissipation
ADSP-21mod980N
INTEGRATION FEATURES
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
16 Mbits of On-Chip SRAM, Configured as 9 Mbits of
Program Memory and 7 Mbits of Data Memory
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
ⴛ
352-Ball PBGA with a 35mm
SYSTEM CONFIGURATION FEATURES
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports 24/32
Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate Reset Pins for Each Internal Processor
35mm footprint
Host IDMA
SPORT0
SPORT1
CONTROL
REV. PrB 6/2001
21mod980N
2188N
DSP 1
Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
2188N
DSP 2
2188N
DSP 3
2188N
DSP 4
2188N
DSP 5
2188N
DSP 6
2188N
DSP 7
2188N
DSP 8
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703 ©Analog Devices,Inc., 2001
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
GENERAL DESCRIPTION
The ADSP-21mod980N is a multi-port Internet gateway
processor optimized for implementation of a complete
V.34/V.90 digital modem. All datapump and controller
functions can be implemented on a single device, offering
the lowest power consumption and highest possible modem
port density.
The ADSP-21mod980N combines the ADSP-2100 Family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports,
a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and
on-chip program and data memory.
The ADSP-21mod980N integrates 16 Mbits of on-chip
memory, configured as 384 Kwords (24-bit) of program
RAM, and 448 Kwords (16-bit) of data RAM. Power-down
circuitry is also provided to reduce the average and standby
power consumption of equipment which in turn reduces
equipment cooling requirements. The ADSP-21mod980N
is available in a 35 mm x 35 mm, 352-lead PBGA package.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980N operates with a 12.5 ns instruction
cycle time. Every instruction can execute in a single processor cycle.
The ADSP-21mod980N’s flexible architecture and comprehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSP-21mod980N can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal
DMA port
• Receive and/or transmit data through the byte DMA
port
• Decrement timer
For current information contact Analog Devices at (800) ANALOGD
MODEM SOFTWARE
The following software is available as object code from
Analog Devices Inc.
• ADSP-21mod Family Dynamic Internet Voice
• ADSP-21mod980-210N Multiport Internet Gateway
A complete system implementation requires the
ADSP-21mod980N device plus modem or voice software.
The modem software executes general modem control,
command sets, error correction, and data compression,
data modulations (for example, V.34 and V.90), and host
interface functions.The host interface allows system access
to modem statistics, such as call progress, connect speed,
retrain count, symbol rate, and other modulation
parameters.
The modem datapump and controller software reside in
on-chip SRAM and do not require additional memory. You
can configure the ADSP-21mod980N dynamically by
downloading software from the host through the 16-bit
IDMA interface. This SRAM-based architecture provides a
software upgrade path to other applications, such as
voice-over-IP, and to future standards.
DEVELOPMENT SYSTEM
Analog Devices' wide range of software and hardware development tools supports the ADSP-218x N Series. The DSP
tools include an integrated development environment
(IDE), an evaluation kit, and a serial port emulator.
VisualDSP® is an integrated development environment,
allowing for fast and easy development, debug and deployment. The VisualDSP project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library
builder); a linker; a loader; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library
that includes DSP and mathematical functions.
Debugging both C and assembly programs with the VisualDSP debugger, programmers can:
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Fill and dump memor y
• Source level debugging
TM
Access
Processor Modem Solution.
(DIVA) Voice Over Network Solution.
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PRELIMINARY TECHNICAL DATA
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The VisualDSP IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the
ADSP-218x development tools, including the syntax highlighting in the VisualDSP editor. This capability controls
how the development tools process inputs and generate
outputs.
The ADSP-218x EZ-ICE ® Emulator provides an easier
and more cost-effective method for engineers to develop
and optimize DSP systems, shortening product development cycles for faster time-to-market. The
ADSP-21mod980N integrates on-chip emulation support
with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer
mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-21mod980N
device need not be removed from the target system when
using the EZ-ICE, nor are any adapters needed. Due to the
small footprint of the EZ-ICE connector, emulation can be
supported in final board designs.The EZ-ICE performs a
full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and
altered
• PC upload and download functions
• Instruction-level emulation of program booting and
execution
• Complete assembly and disassembly of instructions
• C source-level debugging
ADSP-21mod980N
ADDITIONAL INFORMATION
This data sheet provides a general overview of
ADSP-21mod980N functionality. For specific information
about the modem processors, refer to the ADSP-2188N
data sheet. For additional information on the architecture
and instruction set of the modem processors, refer to the
ADSP-2100 Family User’s Manual (3rd edition). For more
information about the development tools, refer to the
ADSP-2100 Family Development Tools Data Sheet.
3REV. PrB 6/2001
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
For current information contact Analog Devices at (800) ANALOGD
ARCHITECTURE OVERVIEW
Figure 2 on page 4 is a functional block diagram of the
ADSP-21mod980N. It contains eight independent digital
signal processors.
DATA<23:8>, A<0>
CLKIN
IAD<15:0>, IDMA CNT L
PF<0:2>/MODE A:C
SPORT0A
SPORT1
EMULATOR
17
20
3
2188N
DSP 1 DSP 2 DSP 3 DSP 4
4
4
8
SIGNALS ROUTED TO EACH RESPECTIVE DIE
BR <8:1>
BG <8:1>
RESET <8:1>
CLKOUT <8:1>
EE <8:1>
IS <8:1>
TFS0 <8:1>
DT1 <8:1>
INTERRUPTS < 8:1>
SUBTOTAL = 177 S IGNAL BAL LS
GND
VDDINT
VDDEXT
2188N
8
8
8
8
8
8
8
8
32
109
44
22
2188N2188N
2188N
DSP 5
IDMA CNTL = IAL, IRD, IW R, IACK
INTERRUPT S = IRQ E (PF4), IRQL0(P F5), IRQ L1 (PF 6), IRQ 2(PF 7)
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK
SPORT0A, SPORT 0B
SPORT1 = RFS1, TFS1, DR1, SCKL1
NOTE:
1. PWD AND PF3/MODE D ARE TIED HIGH
2188N
DSP 6
ELOUT, ERESET
= RFS0, DR0, DT0, SCKL0
2188N
DSP 7
2188N
DSP 8
IAD <15:0>,
IDMA CNT L
4
SPORT0B
20
SUBTOTAL = 175 P OW ER BA LLS
TOTAL = 352 BALLS
Figure 2. ADSP-21mod980N Functional Block Diagram
Every modem processor has:
• A DSP core
• 256K bytes of RAM
• Two s er i a l p o r ts
• An IDMA host.
The signals of each modem processor are accessed through
accessed through a single external pin. Other signals remain
separate and they are accessed through separate external
pins for each processor.
The arrangement of the eight modem processors in the
ADSP-21mod980N makes one basic configuration possible: a slave configuration. In this configuration, the data
pins of all eight processors connect to a single bus structure.
the external pins of the ADSP-21mod980N. Some signals
are bussed with the signals of the other processors and are
4 6/2001 REV. PrB
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All eight modem processors have identical functions and
have equal status. Each of the modem processors is connected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in “Memory
Architecture” on page 10). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem processor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:
• is bidirectional and has a separate, double-buffered
transmit and receive section.
• can use an external serial clock or generate its own
serial clock internally.
• has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
• supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding according to CCITT recommendation G.711.
• receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An interrupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
ADSP-21mod980N
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are configured during RESET
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6 lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
only, while ser i a l por t p i ns are software
5REV. PrB 6/2001
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
Table 1. Common Mode Pins
Pin Name(s) # of Pins Input/Output Function
For current information contact Analog Devices at (800) ANALOGD
RESET 8 I Processor Reset Input
BR
BG
IRQ2
/ 8 I Edge- or Level-Sensitive Interrupt Request
8 I Bus Request Input
8 O Bus Grant Output
PF7 8 I/O Programmable I/O Pin
IRQL1
/ 8 I Level-Sensitive Interrupt Requests
PF6 8 I/O Programmable I/O Pin
/ 8 I Level-Sensitive Interrupt Requests
IRQL0
PF5 8 I/O Programmable I/O Pin
/ 8 I Edge-Sensitive Interrupt Requests
IRQE
1
1
1
1
PF4 8 I/O Programmable I/O Pin
Mode C / 1 I Mode Select Input - Checked Only During RESET
PF2 1 I/O Programmable I/O Pin During Normal Operation
Mode B / 1 I Mode Select Input - Checked Only During RESET
PF1 1 I/O Programmable I/O Pin During Normal Operation
Mode A / 1 I Mode Select Input - Checked Only During RESET
PF0 1 I/O Programmable I/O Pin During Normal Operation
CLKIN 1 I Clock Input
CLKOUT 8 O Processor Clock Output
SPORT 28 I/O Serial Port I/O Pins
2
VDD and GND 175 I Power and Ground
EZ-Port 16 I/O For Emulation Use
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector
to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable.
MEMORY INTERFACE PINS
The ADSP-21mod980N modem pool is used in Slave
Mode. In Slave Mode, the Modem Processors operate in
host configuration. The operating mode is determined by
the state of the Mode C pin during RESET
and cannot be
changed while the modem pool is running. See the “Mem-
ory Architecture” section for more information.
6 6/2001 REV. PrB
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Table 2. Host Pins (Mode C = 1) Modem Processors 1-8
Pin Name
# of
Pins
IAD[15:0] 32
Input/
Output
1
I/O IDMA Port
Function
Address/Data Bus
A0 1 O Address Pin for Exter-
nal I/O, Program,
Data, or Byte access
D[23:8] 16 I/O Data I/O Pins for Pro-
gram, Data Byte and
I/O spaces
IWR
IRD
IAL 2
1
2
2
I IDMA Write Enable
1
I IDMA Read Enable
1
I IDMA Address Latch
Pin
IS
IACK
8 I IDMA Selects
1
2
O IDMA Port Acknowl-
edge Configurable in
Mode D; Open Drain
1
There are two distinct IAD buses. One addresses DSPs 1-4 and the other
communicates with DSPs 5-8. See Figure 2 for details.
INTERRUPTS
The interrupt controller allows each modem processor in
the modem pool to respond individually to eleven possible
interrupts and RESET
with minimum overhead. The
ADSP-21mod980N provides four dedicated external interrupt input pins, IRQ2
, IRQL1, IRQL0, and IRQE (shared
with the PF[7:4] pins) for each modem processor. The
ADSP-21mod980N also supports internal interrupts from
the timer, the byte DMA port, the serial port, software, and
the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except
power down and RESET
). The IRQ2, IRQ1, and IRQ0
input pins can be programmed to be either level- or
edge-sensitive. IRQL0
and IRQL1 are level-sensitive and
ADSP-21mod980N
IRQE
is edge sensitive. The priorities and vector addresses
of all interrupts are shown in Table on page 7. When the
modem pool is reset, interrupt servicing is disabled.
Table 3. Interrupt Priority and Interrupt Vector
Addresses
Source Of Interrupt
RESET (or Power-Up
with PUCR = 1)
Power Down
(Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
IRQE
BDMA Interrupt 0x001C
SPORT1 Transmit or
IRQ1
SPORT1 Receive or
IRQ0
Timer 0x0028 (Lowest Priority)
LOW POWER OPERATION
The ADSP-21mod980N has three low power modes that
significantly reduce the power dissipation when the device
operates under standby conditions. These modes are:
• Power Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
POWER D OW N
The ADSP-21mod980N modem pool has a low power feature that lets the modem pool enter a very low power
dormant state through software control. Here is a brief list
Interrupt Vector Address
(Hex)
0x0000 (Highest Priority)
0x002C
0x0004
0x0008
0x000C
0x0018
0x0020
0x0024
7REV. PrB 6/2001
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
of power-down features. Refer to the ADSP-2100 Family
User’s Manual, “System Interface” chapter, for detailed
information about the power-down feature.
• Quick recovery from power down. The modem pool
begins executing instructions in as few as 200 CLKIN
cycles.
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running during power down without affecting the lowest
power rating and 200 CLKIN cycle recovery.
• Power down is initiated by the software power-down
force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally
powering down.
• Context clear/save control allows the modem pool to
continue where it left off or start with a clean context
when leaving the power down state.
• The RESET
down.
IDLE
When the ADSP-21mod980N is in the Idle Mode, the
modem pool waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA
and autobuffer cycle steals still occur.
pin also can be used to terminate power
For current information contact Analog Devices at (800) ANALOGD
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the modem pool’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the modem pool takes to come out of the
idle state (a maximum of n cycles).
SYSTEM CONFIGURATION
Figure on page 9 shows the hardware interfaces for a typi-
cal multichannel modem configuration with the
ADSP-21mod980N. Other system design considerations
such as host processing requirements, electrical loading,
and overall bus timing must all be met. A line interface can
be used to connect the multichannel subscriber or client
data stream to the multichannel serial port of the
ADSP-21mod980N. The IDMA port of the
ADSP-21mod980N is used to give a host processor full
access to the internal memory of the ADSP-21mod980N.
This lets the host dynamically configure the
ADSP-21mod980N by loading code and data into its internal memory. This configuration also lets the host access
server data directly from the ADSP-21mod980N’s internal
memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
SLOW IDLE
The IDLE instruction is enhanced on the
ADSP-21mod980N to let the modem pool’s internal clock
signal be slowed, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given
in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
modem pool fully functional, but operating at the slower
clock rate. While it is in this state, the modem pool’s other
internal clock signals, such as SCLK, CLKOUT, and timer
clock, are reduced by the same ratio. The default form of
the instruction, when no clock divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the modem pool’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, the
ADSP-21mod980N will remain in the idle state for up to a
maximum of n modem pool cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
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T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
ADSP-21mod980N
T1/E1
LINE
INTERFACE
SPORT
21mod980N
ST/CNTL IDMA
Figure 3. Multichannel Modem Configuration
CLOCK SIGNALS
The ADSP-21mod980N is clocked by a TTL-compatible
clock signal that runs at half the instruction rate; a 40 MHz
input clock yields a 12.5 ns processor cycle, which is equivalent to 80 MHz. Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction clock rate, which is indicated by the
CLKOUT signal when enabled. The clock input signal is
connected to the processor’s CLKIN input.
The CLKIN input cannot be halted, changed during operation, or operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power down state. For additional information, refer
to Chapter 9, ADSP-2100 Family User’s Manual for a
detailed explanation of this power down feature.
9REV. PrB 6/2001
PRELIMINARY TECHNICAL DATA
ADSP-21mod980N
A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
For current information contact Analog Devices at (800) ANALOGD
• Figure on page 11 shows Data Memory
• Table on page 11 shows the generation of address bits
based on the DMOVLAY values. Access to external
memory is not available
RESET
The RESET signals initiate a reset of each modem processor in the ADSP-21mod980N. The RESET signals must be
asserted during the power-up sequence to assure proper initialization. RESET
during initial power-up must be held
long enough to let the internal clocks stabilize. If RESETs
PM M OD E B = 0
ALW AYS
ACCESSIBLE
AT ADDRESS
0x0000 - 0x1FFF
are activated any time after power up, the clocks continue to
run and do not require stabilization time.
The power-up sequence is defined as the total time required
for the oscillator circuits to stabilize after a valid V
DD
is
ACCE SSIBL E W HEN
PM OVLAY = 0
applied to the processors, and for the internal phase-locked
loops (PLL) to lock onto the specific frequency. A minimum of 2000 CLKIN cycles ensures that the PLLs have
locked, but this does not include the oscillators’ start-up
time. During this power-up sequence, the RESET
signals
should be held low. On any subsequent resets, the RESET
signals must meet the minimum pulse width specification,
t
.
RSP
The RESET
use an RC circuit to generate your RESET
input contains some hysteresis; however, if you
signals, the use
of an external Schmidt triggers are recommended.
The RESET
for each individual modem processor sets the
ACCE SSIBL E W HEN
PM OVLAY = 4
ACCE SSIBL E W HEN
PM OVLAY = 5
ACCESSIBLE
WHEN
PM OVLAY = 6
INTERNAL
MEMORY
internal stack pointers to the empty stack condition, masks
all interrupts and clears the MSTAT register. When a
RESET
is released, if there is no pending bus request and
PROGRAM MEMORY
MODE B=0
the modem processor is configured for booting, the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
MEMORY ARCHITECTURE
The ADSP-21mod980N provides a variety of memory and
8K INTERNAL
PMOVLAY =
0, 4, 5, 6, 7
8K
INTERNAL
peripheral interface options for Modem Processor 1. The
key functional groups are Program Memory, Data Memory,
Byte Memory, and I/O. Refer to the following figures and
tables for PM and DM memory allocations in the
ADSP-21mod980N.
The ADSP-21mod980N modem pool operates in one
memory mode: Slave Mode. The following figures and
tables describe the memory of the ADSP-21mod980N:
• Figure on page 10 shows Program Memory
Table 4. PMOVLAY bits
PMOVLAY Memory A13 A[12:0]
0, 4, 5, 6, 7 Internal Not
Figure 4. Program Memory Map
• Table on page 10 shows the generation of address bits
based on the PMOVLAY values
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
0x2000 0x3FFF
ACCE SSIBLE
WHEN
PM OVLAY = 7
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
Not Applicable
Applicable
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PRELIMINARY TECHNICAL DATA
DATA MEM O RY
ALWA YS
ACCESS IBLE
AT ADDRE SS
0x2000 - 0x3FFF
ACCE SSIBL E W HEN
DM O VLAY = 0
ACCE SSIBL E W H EN
DM O VL AY = 4
ACCE SSIBL E W HEN
DM O VL AY = 5
INTERNAL
MEMORY
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ACCE SSIBL E W HEN
DM O VL AY = 6
ACCE SSIBL E W HEN
DM O VL AY = 7
ACCE SSIBL E W H EN
DM O VL AY = 8
For current information contact Analog Devices at (800) ANALOGD
Table 5. DMOVLAY bits
DMOVLAY Memory A13 A[12:0]
0, 4, 5, 6, 7, 8 Internal Not
MEMORY MAPPED REGISTERS (NEW TO THE
0x0000 - 0x1FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ADSP-21MOD980N)
The ADSP-21mod980N has three memory mapped registers that differ from other ADSP-21xx Family DSPs. See
“Waitstate Control Register” on page 11. See
“Programmable Flag & Composite Select Control Regis-
0x0000 - 0x1FFF
ter” on page 12. See “System Control Register” on
page 12. The slight modifications to these registers provide
the ADSP-21mod980N’s waitstate and BMS
features.
ADSP-21mod980N
Not
Applicable
Applicable
control
DATA ME M ORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
ADDR
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
Figure 5. Data Memory Map
1514131211109876543210
11111111 1111
Wait State M od e Select
0 = Normal mo de (P WA IT, DW AIT , IO W AIT 0-3 = N wait states, rang ing fro m 0 to 7)
1 = 2N+ 1 m ode (PW AIT , D WA IT, IOWA IT0 -3 = 2N +1 wait state s, rang ing from 0 to 15)
11 1 1
IOW AIT 1IOW AIT 2IOW AIT 3DWAIT
Figure 6. Waitstate Control Register
.
DM(0x3FFE)
IOW AIT 0
11REV. PrB 6/2001
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1514131211109876543210
11111011 000000 0 0
BMWAIT
CMSSEL
0 = Disable CMS
1 = Enabl e CMS
(where bit: 11-IOM, 10-BM, 9-DM, 8-PM)
PFTYPE
0 = Input
1 = Output
DM(0x3FE6)
Figure 7. Programmable Flag1 & Composite Select Control Register
1
Since they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM
(0x3FE6) must also be 0 to ensure that PF[3] is never an output.
1514131211109876543210
00000100 0111
00 0 0
DM(0x3FFF)
Reserved Set
To 0
SPORT0 Enable
0 = Disa ble
1 = En able
SPORT1 Enable
0 = Disable
1 = Enable
SPORT1 Configure
0 = F I, FO , IR Q0, IRQ 1, S CL K
1= SPORT1
RESERVED
SET TO 0
PWAIT
Program Memory
Wait States
Disable BMS
0 = En able B MS
1 = Disable BM S, exc ept w hen
me mory strobes are three-stated
Figure 8. System Control Register
Table 6. ADSP-21mod980N Mode of Operation
MODE C MODE B MODE A Booting Method
101
1
Considered standard operating settings. These configurations simplify your design and improve memory management.
2
IDMA timing details and the correct usage of IACK are described in the
SLAVE MODE
This section describes the Slave Mode memory configuration of the Modem Processors.
IDMA feature is used to load internal memory as desired. Program execution is held off until internal
program memory location 0x0000 is written to. Chip is configured in Slave Mode.
external pulldown.
2
ADSP-2100 Family User’s Manual
.
INTERNAL MEMORY DMA PORT (IDMA PORT)
The IDMA Port provides an efficient way for a host system
and the ADSP-21mod980N to communicate. The port is
used to access the on-chip program memory and data memory of each modem processor with only one processor cycle
per word overhead. The IDMA port cannot be used, how-
1
IACK requires
12 6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ever, to write to the processor’s memory-mapped control
registers. A typical IDMA transfer process is described as
follows:
1. Host starts IDMA transfer
2. Host uses IS
and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the processor’s IDMA control
registers.
If IAD [15] = 1, the value of IAD [7:0] represents the
IDMA overlay: IAD[14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represents the
starting address of internal memory to be accessed and
IAD [14] reflects PM or DM for access.
1. Host uses IS
and IRD (or IWR) to read (or write) processor internal memory (PM or DM).
2. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written to, while the
ADSP-21mod980N is operating at full speed.
The processor memory address is latched and then automatically incremented after each IDMA transaction. An
external device can therefore access a block of sequentially
addressed memory by specifying only the starting address of
the block. This increases throughput as the address does
not have to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is
asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address
ADSP-21mod980N
specifies an on-chip memory location, the destination type
specifies whether it is a DM or PM access. The falling edge
of the address latch signal latches this value into the
IDMAA register.
Once the address is stored, data can then be either read
from, or written to, the ADSP-21mod980N’s on-chip
memory. Asserting the select line (IS
read or write line (IRD
and IWR respectively) signals the
ADSP-21mod980N that a particular transaction is
required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automatically incremented, and another access can occur.
Through the IDMAA register, the processor can also specify the starting address and data format for DMA operation.
Asserting the IDMA port select (IS
enable (IAL) directs the ADSP-21mod980N to write the
address onto the IAD [14:0] bus into the IDMA Control
Register. If IAD [15] is set to 0, IDMA latches the address.
If IAD [15] is set to 1, IDMA latches OVLAY memory. The
IDMAA register is memory mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) or overlay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address
DM(0x3FE7). See Figure on page 13 for more information on IDMA memory mapping. When bit 14 in 0x3FE7
is set to 1, then timing in Figure on page 35 applies for
short reads. When bit 14 in 0x3FE7 is set to zero short
reads use the timing shown in Figure on page 34.
) and the appropriate
) and address latch
IDM A O VER LAY
1514131211109876543210
0 0 0 0 0 0
RESERVED
RESERVED
ALWA YS SET
TO 0
RESERVED
ALWA YS SET
TO 0
Short Read Only
Enable
1 = Enable
0 = Disable
1514131211109876543210
U
0
SET TO 0
IDMA CONTRO L (U=UNDEFINED AT RESET)
UUUUUUUU UUUUUU
IDM AD
Destination memory type:
0=PM
1=DM
0
0
ID DM OVLAY
IDM AA
ADDRESS
00
0
0
0
ID PM O VLA Y
Figure 9. IDMA Control/OVLAY Registers
000
DM(0x3FE7)
DM(0x3FE0)
13REV. PrB 6/2001
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