Analog Devices ADSP-21mod980 Datasheet

MultiPort Internet

a

FEATURES
PERFORMANCE
Complete Single-Chip MultiPort Internet Gateway

Processor (No External Memory Required)

Implements Sixteen Modem Channels or Forty Voice

Channels in One Package

Each Processor Can Implement One V.34/V.90 Data/

Fax Modem (Includes Datapump and Controller)

Standard Power Version: 600 MIPS Sustained Perfor-

mance, 13.3 ns Instruction Time @ 2.75 V (Internal)

Low Power Version: 600 MIPS Sustained Performance,

13.3 ns Instruction Time @ 1.80 V (Internal)

Open Architecture Extensible to Voice-over-Network

(VoN) and Other Applications
Low Power Dissipation, 45 mW (Typical) Per Channel
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation

Gateway Processor

ADSP-21mod980

INTEGRATION
ADSP-2100 Family Code-Compatible, with Instruction

Set Extensions

2.00M Bytes of On-Chip SRAM, Configured as 1.125M
Bytes of Program Memory and 0.875M Bytes of Data
Memory

Dual-Purpose Program Memory, for Both Instruction

and Data Storage

352-Ball PBGA with a 1.9 Square Inch (1225 Square mm)

Footprint

SYSTEM CONFIGURATION
16-Bit Internal DMA Port for High-Speed Access to

On-Chip Memory (Mode-Selectable)

Programmable Multichannel Serial Port Supports

24/32 Channels

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Separate RESET Pins for Each Internal Processor

DATA<23:8>,

A<0>

CLKIN

IAD<15:0>,

IDMA CNTL

PF<0:2>

/MODE A:C

SPORT0A

SPORT1

EMULATOR

FUNCTIONAL BLOCK DIAGRAM

17

218x

8

20

4

IAD<15:0>,
IDMA CNTL

SPORT0B

20

3

218x

1

4

4

8

218x

2

218x

3

218x

4

218x

5

218x

6

218x

7

REV. 0

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Fax: [phone] © Analog Devices, Inc., 2000

ADSP-21mod980

GENERAL DESCRIPTION

The ADSP-21mod980 is a multiport Internet gateway processor
optimized for implementation of a complete V.34/56K modem.
All data pump and controller functions can be implemented on a
single device, offering the lowest power consumption and high­est possible modem port density.

The ADSP-21mod980 combines the ADSP-2100 Family base
architecture (three computational units, data address generators,
and a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.

The ADSP-21mod980 integrates 2.0M bytes of on-chip memory,
configured as 384K words (24-bit) of program RAM, and 448K
words (16-bit) of data RAM. Power-down circuitry is also pro­vided to reduce the average and standby power consumption of
equipment which, in turn, reduces equipment cooling require­ments. The ADSP-21mod980 is available in a 35 sq-mm., 352-lead
PBGA package.

Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980 operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.

The ADSP-21mod980’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle, the ADSP-21mod980 can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

Modem Software

The modem software executes general modem control, command
sets, error correction and data compression, data modulations
(for example, V.90 and V.34), and host interface functions. The
host interface allows system access to modem statistics, such as
call progress, connect speed, retrain count, symbol rate, and
other modulation parameters.

The modem data pump and controller software resides in on­chip SRAM and does not require additional memory. The
ADSP-21mod980 can be dynamically configured by download­ing software from the host through the 16-bit DMA interface.
This SRAM-based architecture provides a software upgrade path
to other applications, such as Voice-Over-IP (VOIP), and to
future standards. The modem software is available as object code.

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup­ports the ADSP-21mod980. The System Builder provides a
high-level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction­level simulation with a reconfigurable user interface to display
different portions of the hardware environment.

A PROM Splitter generates PROM programmer-compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-21mod980 assembly source
code. The source code debugger allows programs to be corrected
in the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.

The ADSP-218x EZ-ICE
debugging of an ADSP-21mod980 system. The EZ-ICE, in
conjunction with the required processor selection hardware, allows
the user to independently debug code on individual modem
processors. The emulator consists of hardware, host computer
resident software, and target board connector. The ADSP­21mod980 integrates on-chip emulation support with a 14-pin
ICE-Port interface. The ADSP-21mod980 device need not be
removed from the target system when using the EZ-ICE, nor are
any adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Designing an EZ-ICE Compatible System section of
this data sheet, for the exact specifications of the EZ-ICE target
board connector.

Additional Information

This data sheet provides a general overview of ADSP-21mod980
functionality. For specific information about the modem
processors, refer to the ADSP-2188M Preliminary data sheet.
For additional information on the architecture and instruction
set of the modem processors, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools data sheet.

®

Emulator aids in the hardware

EZ-ICE is a registered trademark of Analog Devices, Inc.

–2–

REV. 0

ADSP-21mod980

DATA<23:8>,

A<0>

CLKIN

IAD<15:0>,

IDMA CNTL

PF<0:2>

/MODE A:C

SPORT0A

SPORT1

EMULATOR

17

20

3

218x

1

4

4

8

SIGNALS ROUTED TO EACH RESPECTIVE DIE

BR<8:1>
BG<8:1>

RESET<8:1>

CLKOUT<8:1>

EE<8:1>

IS<8:1>

TFS0<8:1>

DT1<8:1>

INTERRUPTS <8:1>

SUBTOTAL = 177 SIGNAL BALLS

V

V

SUBTOTAL = 175 POWER BALLS
TOTAL = 352 BALLS

GND

DDINT

DDEXT

218x

2

109
44
22

218x

8
8
8
8
8
8
8
8

32

Figure 1. ADSP-21mod980 Processor Pool

20

IAD<15:0>,
IDMA CNTL

3

218x

4

218x

5

IDMA CNTL = IAL, IRD, IWR, IACK
INTERRUPTS= IRQE (PF4), IRQL0 (PF5), IRQL1 (PF6), IRQ2 (PF7)
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK, ELOUT, ERESET
SPORT 0A, SPORT 0B = RFS0, DR0, DT0. SCLK0
SPORT 1 = RFS1, TFS1, DR1, SCLK1

NOTE:

1) PWD AND PF3/MODE D ARE TIED HIGH

218x

6

218x

7

218x

8

4

SPORT0B

ARCHITECTURE OVERVIEW

Figure 1 is an overall block diagram of the ADSP-21mod980
MultiPort Internet Gateway Processor. It contains eight inde­pendent digital signal processors.

Every modem processor has:

• A DSP core

• 256K bytes of RAM

• Two serial ports

• A DMA port

The signals of each modem processor are accessed through the
external pins of the ADSP-21mod980. Some signals are bused
with the signals of the other processors and are accessed through
a single external pin. Other signals remain separate and are
accessed through separate external pins for each processor.

The arrangement of the eight modem processors in the
ADSP-21mod980 makes one basic configuration possible: a
slave configuration. In this configuration, the data pins of all
eight processors connect to a single bus structure.

All eight modem processors have identical functions and equal
status. Each of the four modem processors are connected to a
common DMA bus and each modem processor is configured to
operate in the same mode (see the Slave Mode and the Memory
Mode descriptions in the Memory Architecture section. The
slave mode is considered to be the only mode of operation in the
ADSP-21mod980 modem pool.

Serial Ports

The ADSP-21mod980 has a multichannel serial port (SPORT)
connected to each internal digital modem processor for serial
communications.

The following is a brief list of ADSP-21mod980 SPORT fea­tures. For additional information on the internal Serial Ports,
refer to the ADSP-2100 Family User’s Manual. Each SPORT:

• Is bidirectional and has a separate, double-buffered transmit
and receive section.

• Can use an external serial clock or generate its own serial
clock internally.

• Has independent framing for the receive and transmit sections.
Sections run in a frameless mode, or with frame synchroniza­tion signals internally or externally generated. Frame sync
signals are active high or inverted, with either of two pulse­widths and timings.

• Supports serial data word lengths from 3 to 16 bits and pro­vides optional A-law and µ-law companding according to
CCITT recommendation G.711.

• Receive and transmit sections can generate unique interrupts
on completing a data word transfer.

• Can receive and transmit an entire circular buffer of data with
one overhead cycle per data word. An interrupt is generated
after a data buffer transfer.

A multichannel interface selectively receives and transmits a 24­or 32-word, time-division multiplexed, serial bitstream.

REV. 0

–3–

ADSP-21mod980

PIN DESCRIPTIONS

The ADSP-21mod980 is available in a 352-lead PBGA package.
In order to maintain maximum functionality and reduce pack­age size and pin count, some serial port, programmable flag,
interrupt, and external bus pins have dual, multiplexed func­tionality. The external bus pins are configured during RESET
only, while serial port pins are software configurable during
program execution. Flag and interrupt functionality is retained
concurrently on multiplexed pins. In cases where pin functional­ity is reconfigurable, the default state is shown in plain text;
alternate functionality is shown in italics.

Common-Mode Pins

Pin of Out­Name(s) Pins put Function

RESET 8 I Processor Reset Input
BR 8 I Bus Request Input
BG 8 O Bus Grant Output
IRQ2/ 8 I Edge- or Level-Sensitive Interrupt Request

PF7 I/O Programmable I/O Pin

IRQL0/ 8 I Level-Sensitive Interrupt Request

PF5 I/O Programmable I/O Pin

IRQL1/ 8 I Level-Sensitive Interrupt Requests

PF6 I/O Programmable I/O Pin

IRQE/ 8 I Edge-Sensitive Interrupt Requests

PF4 I/O Programmable I/O Pin
Mode C/ 1 I Mode Select Input—Checked Only
PF2 During RESET

Mode B/ 1 I Mode Select Input—Checked Only
PF1 During RESET

Mode A/ 1 I Mode Select Input—Checked Only
PF0 During RESET

CLKIN 1 I Clock Input
CLKOUT 8 O Processor Clock Output
SPORT 28 I/O Serial Port I/O Pins
VDD and GND 175 I Power and Ground
EZ-Port 16 I/O For Emulation Use

NOTES

1

Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable
the corresponding interrupts, the modem pool will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.

2

SPORT configuration determined by the modem pool’s System Control Regis­ter. Software configurable.

# Input/

1

1

1

1

I/O Programmable I/O Pin During Normal

Operation

I/O Programmable I/O Pin During Normal

Operation

I/O Programmable I/O Pin During Normal

Operation

2

MEMORY INTERFACE PINS

The ADSP-21mod980 modem pool is used in slave mode. In
slave mode, the modem processors operate in host configura­tion. The operating mode is determined by the state of the
Mode C pin during RESET and cannot be changed while the
modem pool is running. See the Memory Architecture section
for more information.

Host Pins (Mode C = 1) Modem Processors 1–8

# Input/
Pin of Out­Name(s) Pins put Function

IAD15:0 32 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Program,

Data, or Byte Access

D23:8 16 I/O Data I/O Pins for Program, Data Byte

and I/O Spaces

IWR 2 I IDMA Write Enable
IRD 2 I IDMA Read Enable

IAL 2 I IDMA Address Latch Pin

IS 8 I IDMA Select
IACK 2 O IDMA Port Acknowledge Configurable

in Mode D; Open Drain

INTERRUPTS

The interrupt controller allows each modem processor in the
modem pool to respond individually to 11 possible interrupts
and reset with minimum overhead. The ADSP-21mod980 pro­vides four dedicated external interrupt input pins, IRQ2, IRQL1,
IRQL0, and IRQE (shared with the PF7:4 pins) for each modem
processor. The ADSP-21mod980 also supports internal inter­rupts from the timer, the byte DMA port, the serial port, software,
and the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except power­down and reset). The IRQ2, IRQ1, and IRQ0 input pins can be
programmed to be either level- or edge-sensitive. IRQL0 and
IRQL1 are level-sensitive and IRQE is edge-sensitive. The pri­orities and vector addresses of all interrupts are shown in Table I.

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt Address (Hex)

Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable) 002C

IRQ2 0004
IRQL1 0008
IRQL0 000C

SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)

When the modem pool is reset, interrupt servicing is disabled.

LOW POWER OPERATION

The ADSP-21mod980 has three low-power modes that signifi­cantly reduce the power dissipation when the device operates
under standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

–4–

REV. 0

ADSP-21mod980

Power-Down

The ADSP-21mod980 modem pool has a low-power feature
that lets the modem pool enter a very low-power dormant state
through software control. Here is a brief list of power-down fea­tures. Refer to the ADSP-2100 Family User’s Manual, “System
Interface” chapter, for detailed information about the power­down feature.

• Quick recovery from power-down. The modem pool begins
executing instructions in as few as 200 CLKIN cycles.

• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power­down without affecting the lowest power rating and 200 CLKIN
cycle recovery.

• Power-down is initiated by the software power-down force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.

• Context clear/save control allows the modem pool to continue
where it left off or start with a clean context when leaving the
power-down state.

• The RESET pin also can be used to terminate power-down.

Idle

When the ADSP-21mod980 is in the Idle Mode, the modem pool
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc­tion. In Idle mode IDMA, BDMA, and autobuffer cycle steals
still occur.

Slow Idle

The IDLE instruction is enhanced on the ADSP-21mod980 to
let the modem pool’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by
a selectable divisor given in the IDLE instruction.

The format of the instruction is:

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the modem
pool fully functional, but operating at the slower clock rate.
While it is in this state, the modem pool’s other internal clock
signals, such as SCLK, CLKOUT, and timer clock, are reduced
by the same ratio. The default form of the instruction, when no
clock divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down
the modem pool’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan­dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-21mod980 will remain
in the idle state for up to a maximum of n modem pool cycles
(n = 16, 32, 64, or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the modem pool’s reduced internal clock
rate. Under these conditions, interrupts must not be generated
at a faster rate than can be serviced, due to the additional time
the modem pool takes to come out of the idle state (a maximum
of n cycles).

SYSTEM CONFIGURATION

Figure 2 shows the hardware interfaces for a typical multichan­nel modem configuration with the ADSP-21mod980. Other
system design considerations, such as host processing require­ments, electrical loading, and overall bus timing, must all be
met. A line interface can be used to connect the multichannel
subscriber or client data stream to the multichannel serial
port of the ADSP-21mod980. The IDMA port of the ADSP­21mod980 is used to give a host processor full access to the
internal memory of the ADSP-21mod980. This lets the host
dynamically configure the ADSP-21mod980 by loading code
and data into its internal memory. This configuration also lets
the host access server data directly from the ADSP-21mod980’s
internal memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.

REV. 0

HOST

MICRO

HOST CONTROL

HOST ADDRESS

HOST DATA

T1/E1

LINE

INTERFACE

SPORT

ADSP-21

mod

980

IDMAST/CNTL

STATUS

AND CONTROL

STATUS

AND

CONTROL

PAL

IDMA

PAL

IDMA CONTROL

IDMA ADDRESS

Figure 2. Multichannel Modem Configuration

–5–

SPORT

ADSP-21

mod

980

IDMAST/CNTL

ADSP-21mod980

CLOCK SIGNALS

The ADSP-21mod980 is clocked by a TTL-compatible clock
signal that runs at half the instruction rate; a 37.5 MHz input
clock yields a 13.3 ns processor cycle, which is equivalent to
75 MHz. Normally, instructions are executed in a single proces­sor cycle. All device timing is relative to the internal instruction
clock rate, which is indicated by the CLKOUT signal when
enabled. The clock input signal is connected to the processor’s
CLKIN input.

The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information, refer to Chapter 9, ADSP-
2100 Family User’s Manual for a detailed explanation of this
power-down feature.

A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate.

Reset

The RESET signals initiate a reset of each modem processor in
the ADSP-21mod980. The RESET signals must be asserted
during the power-up sequence to assure proper initialization.
RESET during initial power-up must be held long enough to let
the internal clocks stabilize. If RESETs are activated any time
after power up, the clocks continue to run and do not require
stabilization time.

The power-up sequence is defined as the total time required for
the oscillator circuits to stabilize after a valid V
the processors, and for the internal phase-locked loops (PLL) to
lock onto the specific frequency. A minimum of 2000 CLKIN
cycles ensures that the PLLs have locked, but this does not include
the oscillators’ start-up time. During this power-up sequence,
the RESET signals should be held low. On any subsequent
resets, the RESET signals must meet the minimum pulsewidth
specification, t

RSP

.

is applied to

DD

The RESET inputs contains some hysteresis; however, if an RC
circuit is used to generate the RESET signals, the use of exter­nal Schmitt triggers is recommended.

The reset for each individual modem processor sets the internal
stack pointers to the empty stack condition, masks all interrupts
and clears the MSTAT register. When a RESET is released, if
there is no pending bus request and the modem processor is
configured for booting, the boot-loading sequence is performed.
The first instruction is fetched from on-chip program memory
location 0x0000 once boot loading completes.

MEMORY ARCHITECTURE

The ADSP-21mod980 provides a variety of memory and
peripheral interface options for Modem Processor 1. The key
functional groups are Program Memory, Data Memory, Byte
Memory, and I/O. Refer to the following figures and tables for
PM and DM memory allocations in the ADSP-21mod980.

The ADSP-21mod980 modem pool operates in one memory
mode: Slave Mode. The following figures and tables describe
the memory of the ADSP-21mod980:

• Figure 3 shows Program Memory.

• Figure 4 shows Data Memory.

• Table II explains the generation of address bits based on the

PMOVLAY values.

• Table III explains the generation of address bits based on the
DMOVLAY values. Access to external memory is not available.

–6–

REV. 0

ADSP-21mod980

PROGRAM MEMORY

PM MODE B = 0

ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF

ACCESSIBLE WHEN
PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 4

INTERNAL
MEMORY

0x2000 – 0x3FFF

ACCESSIBLE WHEN
PMOVLAY = 5

ACCESSIBLE WHEN
PMOVLAY = 6

ACCESSIBLE WHEN
PMOVLAY = 7

0x2000 – 0x3FFF

0x2000 – 0x3FFF

0x2000 – 0x3FFF

0x2000 – 0x3FFF

Figure 3. Program Memory

Table II. PMOVLAY Bits

PROGRAM MEMORY

MODE B = 0

8K INTERNAL

PMOVLAY =

0, 4, 5, 6, 7

8K

INTERNAL

ADDR

0x3FFF

0x2000

0x1FFF

0x0000

PMOVLAY Memory A13 A12:0

0, 4, 5, 6, 7 Internal Not Applicable Not Applicable

DATA MEMORY

ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF

ACCESSIBLE WHEN
DMOVLAY = 0

ACCESSIBLE WHEN
DMOVLAY = 4

ACCESSIBLE WHEN
DMOVLAY = 5

INTERNAL
MEMORY

0x0000 – 0x1FFF

0x0000 – 0x1FFF

ACCESSIBLE WHEN
DMOVLAY = 6

ACCESSIBLE WHEN
DMOVLAY = 7

ACCESSIBLE WHEN
DMOVLAY = 8

0x0000 – 0x1FFF

0x0000 – 0x1FFF

0x0000 – 0x1FFF

0x0000 – 0x1FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

INTERNAL 8160

WORDS

8K INTERNAL

DMOVLAY =

0, 4, 5, 6, 7, 8

ADDR

0x3FFF

0x3FE0

0x3FDF

0x2000

0x1FFF

REV. 0

Figure 4. Data Memory Map

Table III. DMOVLAY Bits

DMOVLAY Memory A13 A12:0

0, 4, 5, 6, 7, 8 Internal Not Applicable Not Applicable

–7–

ADSP-21mod980

Memory-Mapped Registers (New to the ADSP-21mod980)

The ADSP-21mod980 has three memory-mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifi­cations to these registers (Wait State Control, Programmable
Flag and Composite Select Control, and System Control) provide
the ADSP-21mod980’s wait state and BMS control features.

Slave Mode

This section describes the Slave Mode memory configuration of
the Modem Processors.

Internal Memory DMA Port (IDMA Port)

The IDMA Port provides an efficient way for a host system and
the ADSP-21mod980 to communicate. The port is used to
access the on-chip program memory and data memory of each
modem processor with only one processor cycle per word over­head. The IDMA port cannot be used, however, to write to the

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1

111101100000000

DWAIT

WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, RANGING FROM 0 TO 15)

IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0

Figure 5. Wait State Control Register

processor’s memory-mapped control registers. A typical IDMA
transfer process is described as follows:

1. Host starts IDMA transfer.

2. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection
into the processor’s IDMA control registers.

If IAD [15] = 1, the value of IAD [7:07] represents the IDMA
overlay: IAD[14:8] must be set to 0.

If IAD [15] = 0, the value of IAD [13:0] represents the starting
address of internal memory to be accessed and IAD [14] reflects
PM or DM for access.

3. Host uses IS and IRD (or IWR) to read (or write) processor

internal memory (PM or DM).

4. Host ends IDMA transfer.

DM(0x3FFE)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 DM(0x3FE6)

111101100000000

BMWAIT

CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS

(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)

PFTYPE
0 = INPUT
1 = OUTPUT

Figure 6. Programmable Flag and Composite Select
Control Register

NOTE: Since they are multiplexed within the ADSP-21mod980, PF[2:0] should be configured as an output for only one processor at a
time. Bit [3] of DM (0x3F36) must also be 0.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0

000010000000111

RESERVED

SET TO 0

SPORT0 ENABLE
0 = DISABLE
1 = ENABLE

SPORT1 ENABLE
0 = DISABLE
1 = ENABLE

SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1

RESERVED

ALWAYS
SET TO 0

DISABLE BMS
0 = ENABLE BMS
1 = DISABLE BMS, EXCEPT WHEN
MEMORY STROBES ARE
THREE-STATED

DM(0x3FFF)

PWAIT
PROGRAM MEMORY
WAIT STATES

Figure 7. System Control Register

Table IV. ADSP-21mod980 Mode of Operation

MODE C MODE B MODE A Booting Method

1 0 1 IDMA feature is used to load internal memory as desired. Program execution is held off until

internal program memory location 0x0000 is written to. Chip is configured in Slave Mode.
IACK requires external pull-down.

1

Considered standard operating settings. These configurations simplify your design and improve memory management. IDMA timing details and the correct
usage of IACK are described in the ADSP-2100 Family User’s Manual; refer to pages 11-18 thru 11-19.

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ADSP-21mod980

The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to, while the
ADSP-21mod980 is operating at full speed.

The processor memory address is latched and then automati­cally incremented after each IDMA transaction. An external
device can, therefore, access a block of sequentially addressed
memory by specifying only the starting address of the block.
This increases throughput as the address does not have to be
sent for each memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.

Once the address is stored, data can then be either read from, or
written to, the ADSP-21mod980’s on-chip memory. Asserting
the select line (IS) and the appropriate read or write line (IRD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0

000010000000111

and IWR respectively) signals the ADSP-21mod980 that a par­ticular transaction is required. In either case, there is a one­processor-cycle delay for synchronization. The memory access
consumes one additional processor cycle.

Once an access has occurred, the latched address is automati­cally incremented, and another access can occur.

Through the IDMAA register, the processor can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the ADSP-21mod980 to write the address onto the IAD [14:0]
bus into the IDMA Control Register. If IAD [15] is set to 0,
IDMA latches the address. If IAD [15] is set to 1, IDMA latches
OVLAY memory. The IDMAA register is memory mapped at
address DM (0x3FE0). Note that the latched address (IDMAA)
or overlay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address DM(0x3FE7).
See Figure 8 for more information on IDMA memory map­ping. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 25
applies for short reads. When Bit 14 in 0x3FE7 is set to zero
short reads, use the timing shown in Figure 26.

DM(0x3FE7)

RESERVED

SET TO 0

RESERVED

SET TO 0

SHORT READ ONLY
ENABLE
0 = DISABLE
1 = ENABLE

ID DMOVLAY ID PMOVLAY

a. IDMA Overlay

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

UUUUUUUUUUUUUUU

IDMAA

IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM

ADDRESS

b. IDMA Control (U = Undefined at Reset)

Figure 8. IDMA Control/OVLAY Registers

DM(0x3FE0)

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ADSP-21mod980

DMA

PROGRAM MEMORY

OVLAY

ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF

0x2000 – 0x3FFF

ACCESSIBLE WHEN
PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 4

ACCESSIBLE WHEN
PMOVLAY = 5

ACCESSIBLE WHEN
PMOVLAY = 6

0x2000 – 0x3FFF

0x2000 – 0x3FFF

ACCESSIBLE WHEN
PMOVLAY = 7

0x2000 – 0x3FFF

0x2000 – 0x3FFF

Figure 9. Direct Memory Access—PM and DM Memory Maps

IDMA Port Booting

The ADSP-21mod980 boots programs through its Internal
DMA port. When Mode C = 1, Mode B = 0, and Mode A = 1,
the ADSP-21mod980 boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execu­tion is held off until on-chip program memory location 0 is
written to.

Flag I/O Pins

Each modem processor has eight general-purpose program­mable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register
is used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the ADSP­21mod980’s clock. Bits that are programmed as outputs will
read the value being output. The PF pins default to input dur­ing reset.

Note: Pins PF0, PF1, and PF2 are also used for device con­figuration during reset. Since they are multiplexed within the
ADSP-21mod980, PF[0:2] should be configured as an output
for only one processor at a time.

DMA

DATA MEMORY

OVLAY

ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF

0x0000 – 0x1FFF

ACCESSIBLE WHEN
DMOVLAY = 0

ACCESSIBLE WHEN
DMOVLAY = 4

ACCESSIBLE WHEN
DMOVLAY = 5

ACCESSIBLE WHEN
DMOVLAY = 6

0x0000 – 0x1FFF

0x0000 – 0x1FFF

ACCESSIBLE WHEN
DMOVLAY = 7

ACCESSIBLE WHEN
DMOVLAY = 8

0x0000 – 0x1FFF

0x0000 – 0x1FFF

0x0000 – 0x1FFF

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-21mod980 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation, without replacing the
target system processor, by using only a 14-pin connection from
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a
14-pin plug.

The EZ-ICE can emulate only one modem processor at a time.
You must include hardware to select which processor in the
ADSP-21mod980 you want to emulate. Figure 10 is a functional
representation of the modem processor selection hardware. One
ICE-Port connector can be used with two ADSP-21mod980
processors without using additional buffers.

Issuing the “chip reset” command during emulation causes the
modem processor to perform a full chip reset, including a reset
of its memory mode. Therefore, it is vital that the mode pins are
set correctly prior to issuing a chip reset command from the
emulator user interface. As the mode pins share functionality
with PF0:2 on the ADSP-21mod980, it may be necessary to
reset the target hardware separately to ensure the proper mode
selection state on emulator chip reset. See the ADSP-2100 Fam-
ily EZ-Tools data sheet for complete information on ICE products.

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