Analog Devices ADSP-21992 Datasheet
a
Mixed Signal DSP Controller With CAN
ADSP-21992
KEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
160 MIPS Sustained Performance
48K Words of On-Chip RAM, Configured as 32K Words
On-Chip 24-Bit Program RAM and 16K Words On-Chip
16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full-Speed Operation from Low-
Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
with up to 20 MSPS Sampling Rate (at 160 MHz Core
Clock Rate)
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GENERATOR/PLL
JTAG
TEST AND
EMULATION
ADSP-219x
DSP CORE
32K ⴛ 24
PM RAM
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Controller Area Network (CAN) Module Fully Compliant
with V2.0B Standard
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
16K ⴛ 16
DM RAM
4K ⴛ 24
PM ROM
I/O
PWM
GENERATION
UNIT
BUS
I/O REGISTERS
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
PM ADDRESS/DATA
DM ADDRESS/DATA
TIMER 0
TIMER 1
TIMER 2
FLAG
I/O
REV. 0
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may result from its use. No license is granted by implication or otherwise
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registered trademarks are the property of their respective companies.
ADDRESS
EXTERNAL
MEMORY
INTERFACE
(EMI)
SPI SPORT
WATCHDOG
TIMER
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 www.analog.com
Fax:781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
INTERRUPT
CONTROLLER
(ICNTL)
CONTROLLER AREA
NETWORK (CAN)
ADC
CONTROL
POR
DATA
CONTROL
MEMORY DMA
CONTROLLER
PIPELINE
FLASH ADC
VREF
ADSP-21992
KEY FEATURES (continued)
Precision 1.0 V Voltage Reference
Integrated Power-On-Reset (POR) Generator
Flexible Power Management with Selectable Power-
Down and Idle Modes
2.5 V Internal Operation with 3.3 V I/O
Operating Temperature Ranges of –40ºC to +85ºC and
–40ºC to +125ºC
196-Ball Mini-BGA Package
176-Lead LQFP Package
TARGET APPLICATIONS
Industrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 4
External (Off-chip) Memory . . . . . . . . . . . . . . . . . . 5
External Memory Space . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . 6
Serial Peripheral Interface (SPI) Port . . . . . . . . . . . . . 7
DSP Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . 7
Controller Area Network (CAN) Module . . . . . . . . . 8
Analog-to-Digital Conversion System . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PWM Generation Unit . . . . . . . . . . . . . . . . . . . . . . . 9
Auxiliary PWM Generation Unit . . . . . . . . . . . . . . . . 9
Encoder Interface Unit . . . . . . . . . . . . . . . . . . . . . . 10
Flag I/O (FIO) Peripheral Unit . . . . . . . . . . . . . . . . 10
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . 11
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Peripheral Interrupt Controller . . . . . . . . . . . . . . . . 11
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 12
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-Down Core Mode . . . . . . . . . . . . . . . . . . . 12
Power-Down Core/Peripherals Mode . . . . . . . . . . 12
Power-Down All Mode . . . . . . . . . . . . . . . . . . . . 12
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Power-On Reset (POR) . . . . . . . . . . . . . . 13
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Set Description . . . . . . . . . . . . . . . . . . . 14
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 14
Designing an Emulator-Compatible DSP Board . . . 15
Additional Information . . . . . . . . . . . . . . . . . . . . . . 15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 28
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 28
Clock In and Clock Out Cycle Timing . . . . . . . . . 29
Programmable Flags Cycle Timing . . . . . . . . . . . 30
Timer PWM_OUT Cycle Timing . . . . . . . . . . . . 31
External Port Write Cycle Timing . . . . . . . . . . . . 32
External Port Read Cycle Timing . . . . . . . . . . . . 33
External Port Bus Request/Grant Cycle Timing . . 34
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Peripheral Interface Port—Master Timing . 38
Serial Peripheral Interface Port—Slave Timing . . 39
JTAG Test And Emulation Port Timing . . . . . . . 40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . 41
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 42
Example System Hold Time Calculation . . . . . . . 42
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 48
GENERAL DESCRIPTION
The ADSP-21992 is a mixed signal DSP controller based on the
ADSP-219x DSP Core, suitable for a variety of high performance
industrial motor control and signal processing applications that
require the combination of a high performance DSP and the
mixed signal integration of embedded control peripherals such
as analog-to-digital conversion with communications interfaces
such as CAN.
The ADSP-21992 integrates the fixed point ADSP-219x family
base architecture with a serial port, an SPI compatible port, a
DMA controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21992 architecture is code compatible with previous
ADSP-217x based ADMCxxx products. Although the architectures are compatible, the ADSP-21992, with ADSP-219x
architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data address
generators, and program sequencer make the ADSP-21992 more
flexible and easier to program than the previous ADSP-21xx
embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for easier
implementation of circular buffering.
The ADSP-21992 integrates 48K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21992 operates with a 6.25 ns instruction cycle time for
a 160 MHz CCLK, with a 6.67 ns instruction cycle time for a
–2– REV. 0
ADSP-21992
150 MHz CCLK, and with a 10.0 ns instruction cycle time for
a 100 MHz CCLK. All instructions, except two multiword
instructions, execute in a single DSP cycle.
The flexible architecture and comprehensive instruction set of
the ADSP-21992 support multiple operations in parallel. For
example, in one processor cycle, the ADSP-21992 can:
• Generate an address for the next instruction fetch.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computational operation.
These operations take place while the processor continues to:
• Receive and transmit data through the serial port.
• Receive or transmit data over the SPI port.
• Access external memory through the external memory
interface.
• Decrement the timers.
• Operate the embedded control peripherals (ADC, PWM,
EIU, etc.).
DSP Core Architecture
• 6.25 ns instruction cycle time (internal), for up to
160 MIPS sustained performance (6.67 ns instruction
cycle time for 150 MIPS sustained performance and
10.0 ns instruction cycle time for 100 MIPS sustained
performance)
• ADSP-218x family code compatible with the same easy
to use algebraic syntax
• Single cycle instruction execution
• Up to 1M words of addressable memory space with
twenty four bits of addressing width
• Dual purpose program memory for both instruction and
data storage
• Fully transparent instruction cache allows dual operand
fetches in every instruction cycle
• Unified memory space permits flexible address genera-
tion, using two independent DAG units
• Independent ALU, multiplier/accumulator, and barrel
shifter computational units with dual 40-bit accumulators
• Single cycle context switch between two sets of computa-
tional and DAG registers
• Parallel execution of computation and memory
instructions
• Pipelined architecture supports efficient code execution
at speeds up to 160 MIPS
• Register file computations with all nonconditional, non-
parallel computational instructions
• Powerful program sequencer provides zero overhead
looping and conditional instruction execution
• Architectural enhancements for compiled C code
efficiency
• Architecture enhancements beyond ADSP-218x family
are supported with instruction set extensions for added
registers, ports, and peripherals.
The clock generator module of the ADSP-21992 includes clock
control logic that allows the user to select and change the main
clock frequency. The module generates two output clocks: the
DSP core clock, CCLK; and the peripheral clock, HCLK.
CCLK can sustain clock values of up to 160 MHz, while HCLK
can be equal to CCLK or CCLK/2 for values up to a maximum
80MHz peripheral clock at the 160MHz CCLK rate.
The ADSP-21992 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single word instruction can be executed in a
single processor cycle. The ADSP-21992 assembly language uses
an algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
The block diagram Figure 1 shows the architecture of the
embedded ADSP-219x core. It contains three independent com-
putational units: the ALU, the multiplier/accumulator (MAC),
and the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating point representations.
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21992 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four 16-
bit address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
ADSP-219x DSP Instruction Set Reference
.
–3–REV. 0
ADSP-21992
ADSP-219x DSP CORE
DAG1
4 ⴛ 4 ⴛ 16
DM ADDRESS BUS
DATA
REGISTER
FILE
MULT
PX
DAG2
4 ⴛ 4 ⴛ 16
INPUT
REGIST ERS
RESULT
REGIST ERS
16 ⴛ 16-BIT
CACHE
64 ⴛ 24-BIT
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
24
DMA CONNECT
PM DATA BUS
DM DATA BUS
I/O DATA
BARREL
SHIFTER
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
24 BI T
ADDRESS
ADDRESS
ADDRESS
ADDRESS
I/O ADDRESS
24
16
16
DMA ADDRESS
DMA DATA
ALU
24
24
(MEMORY-MAPPED)
SYSTEM INTERRUPT
Figure 1. Block Diagram
24 BIT
I/O REGISTERS
CONTROL
BUFFERS
DMA CONTROLLER
CONTROLLER
DATA
16 BIT
16 B IT
18
STATUS
DATA
DATA
DATA
PROGRAMMABLE
0
K
1
C
K
O
2
C
L
K
B
O
L
C
B
O
L
B
EXTERNAL PORT
I/O PROCESSOR
PERIPHERALS
COMMUNICATIONS
FLAGS (16)
3
JTAG
K
TEST AND
C
O
EMULATION
L
B
ADDR BUS
MUX
DATA BUS
MUX
EMBEDDED
CONTROL
AND
PORTS
TIMERS
6
20
16
3
(3)
in the DAGs allow circular addressing within 64K word boundaries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Direct Memory Access Address Bus
• Direct Memory Access Data Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting the ADSP-21992 to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP
dual memory buses also let the embedded ADSP-219x core fetch
an operand from data memory and the next instruction from
program memory in a single cycle.
Memory Architecture
The ADSP-21992 provides 48K words of on-chip SRAM
memory. This memory is divided into three blocks: two
×
24-bit blocks (blocks 0 and 1) and one 16K × 16-bit block
16K
×
(block 2). In addition, the ADSP-21992 provides a 4K
24-bit
block of program memory boot ROM (that is reserved by ADI
for boot load routines). The memory map of the ADSP-21992
is illustrated in Figure 2.
As shown in Figure 2, the three internal memory RAM blocks
reside in memor y page 0. The entire DSP memory map consists
of 256 pages (pages 0 to 255), and each page is 64K words long.
External memory space consists of four memory banks
(banks3–0) and supports a wide variety of memory devices. Each
MS3–0
bank is selectable using unique memory select lines (
) and
has configurable page boundaries, wait states, and wait state
modes. The 4K words of on-chip boot ROM populates the top
of page 255, while the remaining 254 pages are addressable offchip. I/O memory pages differ from exte rna l m em or y in th at th ey
are 1K word long, and the external I/O pages have their own select
IOMS
pin (
). Pages 31–0 of I/O memory space reside on-chip and
contain the configuration registers for the peripherals. Both the
ADSP-219x core and DMA capable peripherals can access the
entire memory map of the DSP.
–4– REV. 0
ADSP-21992
NOTE: The physical external memory addresses are limited by
20 address lines, and are determined by the external data width
and packing of the external memory space. The Strobe signals
MS3-0
(
) can be programmed to allow the user to change starting
page addresses at run time.
0x00 0000
0x00 3FFF
0x00 4000
0x00 7FFF
0x00 8000
0x00 BFFF
0x00 C000
0x00 FFFF
0x01 0000
0x40 0000
0x80 0000
0xC0 0000
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
BLOCK 0: 16K ⴛ 24-BIT PM RAM
BLOCK 1: 16K ⴛ 24-BIT PM RAM
BLOCK 2: 16K ⴛ 16-BIT DM RAM
RESERVED (16K)
EXTERNAL MEMORY
(4M–64K)
EXTERNAL MEMORY (4M)
EXTERNAL MEMORY (4M)
EXTERNAL MEMORY
(4M–64K)
BLOCK 3: 4K ⴛ 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
PAGE 0 ( 64K) ON-CHIP
(0 WAIT STATE)
PAGES 1 TO 63 BANK 0
(OFF-CHIP) MS0
PAGES 64 TO 127 BANK 1
(OFF-CHIP)
PAGES 128 TO 191 BANK 2
(OFF-CHIP)
PAGES 192 TO 254 BANK 3
(OFF-CHIP)
PAGE 255
(INCLUDES ON-CHIP BOOT ROM)
MS1
MS2
MS3
Figure 2. Core Memory Map at Reset
Internal (On-Chip) Memory
The unified program and data memor y space of the ADSP-21992
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA, and DMA buses. The DSP uses slightly
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
• The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A “C”
program macro is provided for setting this register.
• The program sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit program counter (PC). In
direct addressing instructions (two word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer IJPG register to the
appropriate memory page.
The ADSP-21992 has 4K word of on-chip ROM that holds boot
routines. The DSP starts executing instructions from the on-chip
boot ROM, which starts the boot process. See Booting Modes
on Page 13. The on-chip boot ROM is located on Page 255 in
the DSP memory space map, starting at address 0xFF0000.
External (Off-chip) Memory
Each of the off-chip memory spaces of the ADSP-21992 has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths. See Clock Signals on
Page 12. The off-chip memory spaces are:
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for 8-bit or 16-bit data
widths.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0 containing pages 1 to 63, Bank1 containing pages 64 to 127, Bank2
containing pages 128 to 191, and Bank3 containing pages 192 to
MS3-0
254. The
memory bank pins select Banks 3-0, respectively. Both the ADSP-219x core and DMA capable peripherals
can access the DSP external memory space.
All accesses to external memory are managed by the External
Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21992 supports an additional external memory
called I/O memory space. The IO space consists of 256 pages,
each containing 1024 addresses. This space is designed to
support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers.
The first 32K addresses (IO pages 0 to 31) are reserved for onchip peripherals. The upper 224K addresses (IO pages 32 to 255)
–5–REV. 0
ADSP-21992
are available for external peripheral devices. External I/O pages
IOMS
have their own select pin (
). The DSP instruction set
provides instructions for accessing I/O space.
0x00::0x000
ON-CHIP
PERIPHERALS
16-BITS
0x1F::0x3FF
0x20::0x000
OFF-CHIP
PERIPHERALS
16-BITS
0xFF::0x3FF
PAGES 0 TO 31
1024 WORDS/PAGE
2 PERIPHERALS/PAGE
PAGES 32 TO 255
1024 WORDS/PAGE
Figure 3. I/O Memory Map
Boot Memory Space
Boot memory space consists of one off-chip bank with 254 pages.
BMS
The
memory bank pin selects boot memory space. Both
the ADSP-219x core and DMA capable peripherals can access
the DSP off-chip boot memory space. After reset, the DSP always
starts executing instructions from the on-chip boot ROM.
0x01 0000
OFF-CHIP
BOOT MEMORY
16-BITS
0xFE 0000
PAGES 1 TO 254
64K WORDS/PAGE
two accesses. If an instruction requires an external memory read
and an external memory write access, the bus may be granted
between the two accesses. The external memory interface can be
configured so that the core will have exclusive use of the interface.
DMA and Bus Requests will be granted. When the external
BR
device releases
, the DSP releases BG and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, even while the DSP
is booting and
RESET
The ADSP-21992 asserts the
is active.
BGH
pin when it is ready to start
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.
DMA Controller
The ADSP-21992 has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-21992 internal memory and any of its DMA capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA capable peripherals and external
devices connected to the external memory interface. DMA
capable peripherals include the SPORT and SPI ports, and ADC
Control module. Each individual DMA capable peripheral has a
dedicated DMA channel. To describe each DMA sequence, the
DMA controller uses a set of parameters—called a DMA descriptor. When successive DMA sequences are needed, these DMA
descriptors can be linked or chained together, so the completion
of one DMA sequence auto initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in Figure 1 on
Page 4. Because all of the peripherals use the same bus, arbitra-
tion for DMA bus access is needed. The arbitration for DMA bus
access appears in Table 1.
Figure 4. Boot Memory Map
Bus Request and Bus Grant
The ADSP-21992 can relinquish control of the data and address
buses to an external device. When the external device requires
BR
access to the bus, it asserts the bus request (
) signal. The (BR)
signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Due to synchronizer and arbitration delays, bus grants will be provided with
a minimum of three peripheral clock delays. The ADSP-21992
will respond to the bus grant by:
• Three-stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
• Asserting the bus grant (BG) signal.
The ADSP-21992 will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or peripheral memory spaces. If an instruction requires two external
memory read accesses, the bus will not be granted between the
Table 1. I/O Bus Arbitration Priority
DMA Bus Master Arbitration Priority
SPORT Receive DMA 0—Highest
SPORT Transmit DMA 1
ADC Control DMA 2
SPI Receive/Transmit DMA 3
Memory DMA 4—Lowest
DSP Peripherals Architecture
The ADSP-21992 contains a number of special purpose,
embedded control peripherals, which can be seen in the Functional Block Diagram on Page 1. The ADSP-21992 contains a
high performance, 8-channel, 14-bit ADC system with dual
channel simultaneous sampling ability across four pairs of inputs.
An internal precision voltage reference is also available as part of
the ADC system. In addition, a 3-phase, 16-bit, center based
PWM generation unit can be used to produce high accuracy
PWM signals with minimal processor overhead. The ADSP21992 also contains a flexible incremental encoder interface unit
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ADSP-21992
for position sensor feedback; two adjustable frequency auxiliary
PWM outputs, 16 lines of digital I/O; a 16-bit watchdog timer;
three general-purpose timers, and an interrupt controller that
manages all peripheral interrupts. Finally, the ADSP-21992
contains an integrated power-on-reset (POR) circuit that can be
used to generate the required reset signal for device power-on.
The ADSP-21992 has an external memory interface that is
shared by the DSP core, the DMA controller, and DMA capable
peripherals, which include the ADC, SPORT, and SPI communication ports. The external port consists of a 16-bit data bus, a
20-bit address bus, and control signals. The data bus is configurable to provide an 8- or 16-bit interface to external memory.
Support for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus width.
The memory DMA controller lets the ADSP-21992 move data
and instructions from between memory spaces: internal-toexternal, internal-to-inter nal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.
The embedded ADSP-219x core can respond to up to seventeen
interrupts at any given time: three internal (stack, emulator
kernel, and power-down), two external (emulator and reset), and
twelve user defined (peripherals) interrupts. Programmer s assign
each of the 32 peripheral interrupt requests to one of the 12 user
defined interrupts. These assignments determine the priority of
each peripheral for interrupt service.
The following sections provide a functional overview of the
ADSP-21992 peripherals.
Serial Peripheral Interface (SPI) Port
The Serial Peripheral Interface (SPI) Port provides functionality
for a generic configurable serial port interface based on the SPI
standard, which enables the DSP to communicate with multiple
SPI compatible devices. Key features of the SPI port are:
• Interface to host microcontroller or serial EEPROM
• Master or slave operation (3-wire interface MISO, MOSI,
SCK)
• Data rates to HCLKⴜ4 (16-bit baud rate selector)
• 8- or 16-bit transfer
• Programmable clock phase and polarity
• Broadcast Mode – 1 master, multiple slaves
• DMA capability and dedicated interrupts
• PF0 can be used as Slave Select input line
• PF1–PF7 can be used as external Slave Select output
SPI is a 3 wire interface consisting of 2 data pins (MOSI and
MISO), one clock pin (SCK), and a single Slave Select input
SPISS
) that is multiplexed with the PF0 Flag IO line and seven
(
Slave Select outputs (SPISEL1 to SPISEL7) that are multiplexed
SPISS
with the PF1 to PF7 Flag IO lines. The
select the ADSP-21992 as a slave to an external master. The
SPISEL1 to SPISEL7 outputs can be used by the ADSP-21992
(acting as a master) to select/enable up to seven external slaves
in a multidevice SPI configuration. In a multimaster or a multidevice configuration, all MOSI pins are tied together, all MISO
pins are tied together, and all SCK pins are tied together.
input is used to
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on the serial data line.
The serial clock line synchronizes the shifting and sampling of
data on the serial data line.
In master mode, the DSP core performs the following sequence
to set up and initiate SPI transfers:
1. Enables and configures the SPI port operation (data size,
and transfer format).
2. Selects the target SPI slave with the SPISELx output pin
(reconfigured Programmable Flag pin).
3. Defines one or more DMA descriptors in Page 0 of I/O
memory space (optional in DMA mode only).
4. Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
5. In non DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCK line generates the programmed clock pulses for simultaneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
1. Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
2. Defines and generates a receive DMA descriptor in
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
3. Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4. Starts receiving the data on the appropriate SCK edges
after receiving an SPI chip select on the SPISS input pin
(reconfigured Programmable Flag pin) from a master
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could
continue, by queuing up the next DMA descriptor.
A slave mode transmit operation is similar, except the DSP core
specifies the data buffer in memory space from which to transmit
data, generates and relinquishes control of the transmit DMA
descriptor, and begins filling the SPI port data buffer. If the SPI
controller is not ready on time to transmit, it can transmit a “zero”
word.
DSP Serial Port (SPORT)
The ADSP-21992 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
• Bidirectional: the SPORT has independent transmit and
receive sections.
• Double buffered: the SPORT section (both receive and
transmit) has a data register for transferring data words
to and from other parts of the processor and a register for
shifting data in or out. The double buffering provides
additional time to service the SPORT.
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ADSP-21992
• Clocking: the SPORT can use an external serial clock or
generate its own in a wide range of frequencies down to
0Hz.
• Word length: each SPORT section supports serial data
word lengths from three to sixteen bits that can be transferred either MSB first or LSB first.
• Framing: each SPORT section (receive and transmit) can
operate with or without frame synchronization signals for
each data-word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulsewidths and frame
signal timing.
• Companding in hardware: each SPORT section can
perform A law and µ law companding according to
CCITT recommendation G.711.
• Direct Memory Access with single cycle overhead: using
the built-in DMA master, the SPORT can automatically
receive and/or transmit multiple memory buffers of data
with an overhead of only one DSP cycle per data-word.
The on-chip DSP, via a linked list of memory space
resident DMA descriptor blocks, can configure transfers
between the SPORT and memory space. This chained list
can be dynamically allocated and updated.
• Interrupts: each SPORT section (receive and transmit)
generates an interrupt upon completing a data-word
transfer, or after transferring an entire buffer or buffers if
DMA is used.
• Multichannel capability: The SPORT can receive and
transmit data selectively from channels of a serial bit
stream that is time division multiplexed into up to 128
channels. This is especially useful for T1 interfaces or as
a network communication scheme for multiple processors. The SPORTs also support T1 and E1 carrier
systems.
• Each SPORT channel (Tx and Rx) supports a DMA
buffer of up to eight, 16-bit transfers.
• The SPORT operates at a frequency of up to one-half the
clock frequency of the HCLK
• The SPORT is capable of UART software emulation.
Controller Area Network (CAN) Module
The ADSP-21992 contains a Controller Area Network (CAN)
Module. Key features of the CAN Module are:
• Conforms to the CAN V2.0B standard.
• Supports both standard (11-bit) and extended (29-bit)
Identifiers
• Supports Data Rates of up to 1Mbit/sec (and higher)
• 16 Configurable Mailboxes (All receive or transmit)
• Dedicated Acceptance Mask for each Mailbox
• Data Filtering (first 2 bytes) can be used for Acceptance
Filtering
• Error Status and Warning registers
• Transmit Priority by Identifier
• Universal Counter Module
• Readable Receive and Transmit Counters
The CAN Module is a low baud rate serial interface intended for
use in applications where baud rates are typically under 1 Mbit/
sec. The CAN protocol incorporates a data CRC check, message
error tracking and fault node confinement as means to improve
network reliability to the level required for control applications.
The CAN module architecture is based around a 16-entry
mailbox RAM. The mailbox is accessed sequentially by the CAN
serial interface or the host CPU. Each mailbox consists of eight
16-bit data words. The data is divided into fields, which includes
a message identifier, a time stamp, a byte count, up to 8 bytes of
data, and several control bits. Each node monitors the messages
being passed on the network. If the identifier in the transmitted
message matches an identifier in one of it's mailboxes, then the
module knows that the message was meant for it, passes the data
into it's appropriate mailbox, and signals the host of its arrival
with an interrupt.
The CAN network itself is a single, differential pair line. All nodes
continuously monitor this line. There is no clock wire. Messages
are passed in one of 4 standard message types or frames. Synchronization is achieved by an elaborate sync scheme performed
in each CAN receiver. Message arbitration is accomplished 1 bit
at a time. A dominant polarity is established for the network. All
nodes are allowed to start transmitting at the same time following
a frame sync pulse.
As each node transmits a bit, it checks to see if the bus is the same
state that it transmitted. If it is, it continues to transmit. If not,
then another node has transmitted a dominant bit so the first
node knows it has lost the arbitration and it stops transmitting.
The arbitration continues, bit by bit until only 1 node is left
transmitting.
The electrical characteristics of each network connection are very
stringent so the CAN interface is typically divided into 2 parts: a
controller and a transceiver. This allows a single controller to
support different drivers and CAN networks. The ADSP-21992
CAN module represents only the controller part of the interface.
This module's network I/O is a single transmit line and a single
receive line, which communicate to a line transceiver.
Analog-to-Digital Conversion System
The ADSP-21992 contains a fast, high accuracy, multiple input
analog-to-digital conversion system with simultaneous sampling
capabilities. This A/D conversion system permits the fast,
accurate conversion of analog signals needed in high performance
embedded systems. Key features of the ADC system are:
• 14-bit Pipeline (6-Stage Pipeline) Flash Analog-to-
Digital Converter.
• 8 dedicated analog inputs.
• Dual channel simultaneous sampling capability.
• Programmable ADC clock rate to maximum of
HCLKⴜ4.
• First channel ADC data valid approximately 375 ns after
CONVST (at 20 MSPS).
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ADSP-21992
• All 8 inputs converted in approximately 725 ns (at
20 MSPS).
• 2.0 V peak-to-peak input voltage range.
• Multiple convert start sources.
• Internal or external Voltage Reference.
• Out of range detection.
• DMA capable transfers from ADC to memory.
The ADC system is based on a pipeline flash converter core, and
contains dual input sample-and-hold amplifiers so that simultaneous sampling of two input signals is supported. The ADC
system provides an analog input voltage range of 2.0 Vp-p and
ⴜ
provides 14-bit performance with a clock rate of up to HCLK
The ADC system can be programmed to operate at a clock rate
⁄
that is programmable from HCLK
of 20 MHz (at 160MHz CCLK rate).
The ADC input structure supports 8 independent analog inputs;
four of which are multiplexed into one sample-and-hold amplifier
(A_SHA) and 4 of which are multiplexed into the other sampleand-hold amplifier (B_SHA).
At the 20 MHz sampling rate, the first data value is valid approximately 375 ns after the Convert Start command. All 8 channels
are converted in approximately 725 ns.
The core of the ADSP-21992 provides 14-bit data such that the
stored data values in the ADC data registers are 14 bits wide.
Voltage Reference
The ADSP-21992 contains an onboard band gap reference that
can be used to provide a precise 1.0 V output for use by the A/D
system and externally on the VREF pin for biasing and level
shifting functions. Additionally, the ADSP-21992 may be configured to operate with an external reference applied to the VREF
pin, if required.
PWM Generation Unit
Key features of the 3-phase PWM generation unit are:
• 16-bit, center based PWM generation unit
• Programmable PWM pulsewidth, with resolutions to
12.5 ns (at 80 MHz HCLK Rate)
• Single/double update modes
• Programmable dead time and switching frequency
• Twos complement implementation permits smooth tran-
sition into full ON and full OFF states
• Possibility to synchronize the PWM generation to an
external synchronization
• Special provisions for BDCM Operation (crossover and
output enable functions)
• Wide variety of special switched reluctance (SR)
operating modes
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
• Multiple shutdown sources, independently for each unit
4 to HCLK⁄30, to a maximum
4.
The ADSP-21992 integrates a flexible and programmable, 3phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase
voltage source inverter for ac induction (ACIM) or permanent
magnet synchronous (PMSM) motor control. In addition, the
PWM block contains special functions that considerably simplify
the generation of the required PWM switching patterns for
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM). Tying a dedicated pin,
to GND, enables a special mode, for switched reluctance motors
(SRM).
The six PWM output signals consist of three high side drive pins
(AH, BH, and CH) and three low side drive signals pins (AL,
BL, and CL). The polarity of the generated PWM signals may
be set via hardware by the PWMPOL input pin, so that either
active HI or active LO PWM patterns can be produced.
The switching frequency of the generated PWM patterns is programmable using the 16-bit PWMTM register. The PWM
generator is capable of operating in two distinct modes, single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period,
so that the resultant PWM patterns are symmetrical about the
midpoint of the PWM period. In the double update mode, a
second updating of the PWM registers is implemented at the
midpoint of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns that produce lower
harmonic distortion in 3-phase PWM inverters.
Auxiliary PWM Generation Unit
Key features of the auxiliary PWM generation unit are:
• 16-bit, programmable frequency, programmable duty
cycle PWM outputs
• Independent or offset operating modes
• Double buffered control of duty cycle and period registers
• Separate auxiliary PWM synchronization signal and asso-
ciated interrupt (can be used to trigger ADC Convert
Start).
• Separate auxiliary PWM shutdown signal (AUXTRIP).
The ADSP-21992 integrates a 2-channel, 16-bit, auxiliary PWM
output unit that can be programmed with variable frequency,
variable duty cycle values and may operate in two different
modes, independent mode or offset mode. In independent mode,
the two auxiliary PWM generators are completely independent
and separate switching frequencies and duty cycles may be programmed for each auxiliary PWM output. In offset mode the
switching frequency of the two signals on the AUX0 and AUX1
pins is identical. Bit 4 of the AUXCTRL register places the
auxiliary PWM channel pair in independent or offset mode.
The Auxiliary PWM generation unit provides two chip output
pins, AUX0 and AUX1 (on which the switching signals appear),
and one chip input pin,
down the switching signals—for example, in a fault condition.
AUXTRIP
, which can be used to shut
PWMSR
,
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ADSP-21992
Encoder Interface Unit
The ADSP-21992 incorporates a powerful encoder interface
block to incremental shaft encoders that are often used for
position feedback in high performance motion control systems.
• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).
• Programmable filtering of all encoder input signals
• 32-bit encoder counter
• Variety of hardware and software reset modes
• Two registration inputs to latch EIU count value with
corresponding registration interrupt
• Status of A/B signals latched with reading of EIU count
value.
• Alternative frequency and direction mode
• Single north marker mode
• Count error monitor function with dedicated error
interrupt
• Dedicated 16-bit loop timer with dedicated interrupt
• Companion encoder event (1⁄T) timer unit.
The encoder interface unit (EIU) includes a 32-bit quadrature
up/down counter, programmable input noise filtering of the
encoder input signals and the zero markers, and has four
dedicated chip pins. The quadrature encoder signals are applied
at the EIA and EIB pins. Alternatively, a frequency and direction
set of inputs may be applied to the EIA and EIB pins. In addition,
two north marker/strobe inputs are provided on pins EIZ and
EIS. These inputs may be used to latch the contents of the
encoder quadrature counter into dedicated registers,
EIZLATCH and EISLATCH, on the occurrence of external
events at the EIZ and EIS pins. These events may be programmed
to be either rising edge only (latch event) or rising edge if the
encoder is moving in the forward direction and falling edge if the
encoder is moving in the reverse direction (software latched north
marker functionality).
The encoder interface unit incorporates programmable noise
filtering on the four encoder inputs to prevent spurious noise
pulses from adversely affecting the operation of the quadrature
counter. The encoder interface unit operates at a clock frequency
equal to the HCLK rate. The encoder interface unit operates
correctly with encoder signals at frequencies of up to 13.25 MHz,
at the 80 MHz HCLK rate, corresponding to a maximum
quadrature frequency of 53 MHz (assuming an ideal quadrature
relationship between the input EIA and EIB signals).
The EIU may be programmed to use the north marker on EIZ
to reset the quadrature encoder in hardware, if required.
Alternatively, the north marker can be ignored, and the encoder
quadrature counter is reset according to the contents of a
maximum count register, EIUMAXCNT. There is also a “single
north marker” mode available in which the encoder quadrature
counter is reset only on the first north marker pulse.
The encoder interface unit can also be made to implement some
error checking functions. If an encoder count error is detected
(due to a disconnected encoder line, for example), a status bit in
the EIUSTAT register is set, and an EIU count error interrupt is
generated.
The encoder interface unit of the ADSP-21992 contains a 16-bit
loop timer that consists of a timer register, period register and
scale register so that it can be programmed to time out and reload
at appropriate intervals. When this loop timer times out, an EIU
loop timer timeout interrupt is generated. This interrupt could
be used to control the timing of speed and position control loops
in high performance drives.
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate timing
of successive events of the encoder inputs. The EET can be programmed to time the duration between up to 255 encoder pulses
and can be used to enhance velocity estimation, particularly at
low speeds of rotation.
Flag I/O (FIO) Peripheral Unit
The FIO module is a generic parallel I/O interface that supports
sixteen bidirectional multifunction flags or general-purpose
digital I/O signals (PF15–PF0).
All sixteen FLAG bits can be individually configured as an input
or output based on the content of the direction (DIR) register,
and can also be used as an interrupt source for one of two FIO
interrupts. When configured as input, the input signal can be
programmed to set the FLAG on either a level (level sensitive
input/interrupt) or an edge (edge sensitive input/interrupt).
The FIO module can also be used to generate an asynchronous
unregistered wake-up signal FIO_WAKEUP for DSP core wake
up after power-down.
The FIO Lines, PF7–PF1 can also be configured as external slave
select outputs for the SPI communications port, while PF0 can
be configured to act as a slave select input.
The FIO Lines can be configured to act as a PWM shutdown
source for the 3-phase PWM generation unit of the
ADSP-21992.
Watchdog Timer
The ADSP-21992 integrates a watchdog timer that can be used
as a protection mechanism against unintentional software events.
It can be used to cause a complete DSP and peripheral reset in
such an event. The watchdog timer consists of a 16-bit timer that
is clocked at the external clock rate (CLKIN or crystal input
frequency).
In order to prevent an unwanted timeout or reset, it is necessary
to periodically write to the watchdog timer register. During
abnormal system operation, the watchdog count will eventually
decrement to 0 and a watchdog timeout will occur. In the system,
the watchdog timeout will cause a full reset of the DSP core and
peripherals.
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ADSP-21992
General-Purpose Timers
The ADSP-21992 contains a general-purpose timer unit that
contains three identical 32-bit timers. The three programmable
interval timers (Timer0, Timer1, and Timer2) generate periodic
interrupts. Each timer can be independently set to operate in one
of three modes:
• Pulse Waveform Generation (PWM_OUT) mode
• Pulsewidth Count/Capture (WDTH_CAP) mode
• External Event Watchdog (EXT_CLK) mode
Each Timer has one bidirectional chip pin, TMR2-TMR0. For
each timer, the associated pin is configured as an output pin in
PWM_OUT Mode and as an input pin in WDTH_CAP and
EXT_CLK Modes.
Interrupts
The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The DSP core implements an interrupt
priority scheme as shown in Table 2. Applications can use the
unassigned slots for software and peripheral interrupts. The
Peripheral Interrupt Controller is used to assign the various
peripheral interrupts to the 12 user assignable interrupts of the
DSP core.
Table 2. Interrupt Priorities/Addresses
IMASK/
Interrupt
Emulator (NMI)
—Highest Priority
Reset (NMI) 0 0x00 0000
Power-down (NMI) 1 0x00 0020
Loop and PC Stack 2 0x00 0040
Emulation Kernel 3 0x00 0060
User Assigned Interrupt
(USR0)
User Assigned Interrupt
(USR1)
User Assigned Interrupt
(USR2)
User Assigned Interrupt
(USR3)
User Assigned Interrupt
(USR4)
User Assigned Interrupt
(USR5)
User Assigned Interrupt
(USR6)
User Assigned Interrupt
(USR7)
User Assigned Interrupt
(USR8)
IRPTL Vector Address
NA NA
4 0x00 0080
5 0x00 00A0
6 0x00 00C0
7 0x00 00E0
8 0x00 0100
9 0x00 0120
10 0x00 0140
11 0x00 0160
12 0x00 0180
Table 2. Interrupt Priorities/Addresses
IMASK/
Interrupt
User Assigned Interrupt
(USR9)
User Assigned Interrupt
(USR10)
User Assigned Interrupt
(USR11)
—Lowest Priority
There is no assigned priority for the peripheral interrupts after
reset. To assign the peripheral interrupts a different priority,
applications write the new priority to their corresponding control
bits (determined by their ID) in the Interrupt Priority Control
register.
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically maintained during interrupt handling. To support inter rupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is 8 levels deep, and the status stack is 16 levels deep. To prevent
stack overflow, the PC stack can generate a stack level interrupt
if the PC stack falls below 3 locations full or rises above 28
locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the state of the DSP.
Peripheral Interrupt Controller
The Peripheral Interrupt Controller is a dedicated peripheral unit
of the ADSP-21992 (accessed via IO mapped registers). The
peripheral interrupt controller manages the connection of up to
32 peripheral interrupt requests to the DSP core.
For each peripheral interrupt source, there is a unique 4-bit code
that allows the user to assign the particular peripheral interrupt
to any one of the 12 user assignable interrupts of the embedded
ADSP-219x core. Therefore, the peripheral interrupt controller
IRPTL Vector Address
13 0x00 01A0
14 0x00 01C0
15 0x00 01E0
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ADSP-21992
of the ADSP-21992 contains eight, 16-bit Interrupt Priority
Registers (Interrupt Priority Register 0 (IPR0) to Interrupt
Priority Register 7 (IPR7)).
Each Interrupt Priority Register contains a four 4-bit codes; one
specifically assigned to each peripheral interrupt. The user may
write a value between 0x0 and 0xB to each 4-bit location in order
to effectively connect the particular interrupt source to the corresponding user assignable interrupt of the ADSP-219x core.
Writing a value of 0x0 connects the peripheral interrupt to the
USR0 user assignable interrupt of the ADSP-219x core while
writing a value of 0xB connects the peripheral interrupt to the
USR11 user assignable interrupt. The core interrupt USR0 is the
highest priority user interr upt, while USR11 is the lowest priority.
Writing a value between 0xC and 0xF effectively disables the
peripheral interrupt by not connecting it to any ADSP-219x core
interrupt input. The user may assign more than one peripheral
interrupt to any given ADSP-219x core interrupt. In that case,
the burden is on the user software in the interrupt vector table to
determine the exact interrupt source through reading status bits.
This scheme permits the user to assign the number of specific
interrupts that are unique to their application to the interrupt
scheme of the ADSP-219x core. The user can then use the
existing interrupt priority control scheme to dynamically control
the priorities of the 12 core interrupts.
Low Power Operation
The ADSP-21992 has four low power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-21992 uses the configuration of the PD, STCK, and STALL bits in the PLLCTL
register to select between the low power modes as the DSP
executes the IDLE instruction. Depending on the mode, an
IDLE shuts off clocks to different parts of the DSP in the different
modes. The low power modes are:
• Idle
• Power-Down Core
• Power-Down Core/Peripherals
• Power-Down All
Idle Mode
When the ADSP-21992 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core Mode
When the ADSP-21992 is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
Power-Down Core/Peripherals Mode
When the ADSP-21992 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline. The peripheral bus is
stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
Power-Down All Mode
When the ADSP-21992 is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to re-stabilize the PLL)
resumes executing instructions.
Clock Signals
The ADSP-21992 can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 5. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer. A parallel resonant, fundamental frequency,
microprocessor grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. This clock signal should be a TTL compatible
signal. When an external clock is used, the XTAL input must be
left unconnected.
ⴛ
The DSP provides a user programmable 1
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
BYPASS pin, and MSEL6–0 and DF bits, in the PLL configuration register, decide the PLL multiplication factor at reset. At
run time, the multiplication factor can be controlled in software.
To support input clocks greater that 100 MHz, the PLL uses an
additional bit (DF). If the input clock is greater than 100 MHz,
DF must be set. If the input clock is less than 100 MHz, DF must
be cleared. For clock multiplier settings, see the
DSP Hardware Reference Manual
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-21992 operate at the rate
set by the peripheral clock. The peripheral clock (HCLK) is
either equal to the core clock rate or one half the DSP core clock
rate (CCLK). This selection is controlled by the IOSEL bit in
the PLLCTL register. The maximum core clock is 160 MHz for
the ADSP-21992BST, 150 MHz for both the ADSP-21992BBC
.
to 32ⴛ multiplica-
ADSP-2199x
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ADSP-21992
and ADSP-21992YBC and 100 MHz for the ADSP-21992YST.
The maximum peripheral clock is 80 MHz for the ADSP21992BST, 75 MHz for both the ADSP-21992BBC and ADSP21992YBC and 50 MHz for the ADSP-21992YST—the combination of the input clock and core/peripheral clock ratios may not
exceed these limits.
CLKIN
Figure 5. External Crystal Connections
Reset and Power-On Reset (POR)
The
RESET
pin initiates a complete hardware reset of the ADSP-
21992 when pulled low. The
XTAL
ADSP-2199x
RESET
signal must be asserted
when the device is powered up to assure proper initialization. The
ADSP-21992 contains an integrated power-on reset (POR)
POR
circuit that provides an output reset signal,
, from the ADSP21992 on power-up and if the power supply voltage falls below
the threshold level. The ADSP-21992 may be reset from an
external source using the
RESET
signal, or alternatively, the
internal power-on reset circuit may be used by connecting the
POR
pin to the
RESET
pin. During power-up the
RESET
line
must be activated for long enough to allow the DSP core’s internal
clock to stabilize. The power-up sequence is defined as the total
time required for the crystal oscillator to stabilize after a valid
VDD is applied to the processor and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 512 cycles will ensure that the PLL has locked (this
does not include the crystal oscillator start-up time).
RESET
The
used to generate the
input contains some hysteresis. If an RC circuit is
RESET
signal, the circuit should use an
external Schmitt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
RESET
default values (where applicable). When
is released, if
there is no pending bus request, program control jumps to the
location of the on-chip boot ROM (0xFF0000) and the booting
sequence is performed.
Power Supplies
The ADSP-21992 has separate power supply connections for the
internal (V
) and external (V
DDINT
) power supplies. The
DDEXT
internal supply must meet the 2.5 V requirement. The external
supply must be connected to a 3.3 V supply. All external supply
pins must be connected to the same supply. The ideal power-on
sequence for the DSP is to provide power-up of all supplies simultaneously. If there is going to be some delay in power-up between
the supplies, provide V
Booting Modes
first, then V
DD
DD_IO
.
The ADSP-21992 supports a number of different boot modes
that are controlled by the three dedicated hardware boot mode
control pins (BMODE2, BMODE1, and BMODE0). The use
of three boot mode control pins means that up to eight different
boot modes are possible. Of these only five modes are valid on
the ADSP-21992. The ADSP-21992 exposes the boot
mechanism to software control by providing a nonmaskable boot
interrupt that vectors to the start of the on-chip ROM memory
block (at address 0xFF0000). A boot interrupt is automatically
initiated following either a hardware initiated reset, via the
RESET
pin, or a software initiated reset, via writing to the
Software Reset register. Following either a hardware or a software
reset, execution always starts from the boot ROM at address
0xFF0000, irrespective of the settings of the BMODE2,
BMODE1, and BMODE0 pins. The dedicated BMODE2,
BMODE1, and BMODE0 pins are sampled at hardware reset.
The particular boot mode for the ADSP-21992 associated with
the settings of the BMODE2, BMODE1, BMODE0 pins is
defined in Table 3.
Table 3. Summary of Boot Modes
Boot Mode BMODE2 BMODE1 BMODE0 Function
0 0 0 0 Illegal – Reserved
1 0 0 1 Boot from External 8-bit Memory over EMI
2 0 1 0 Execute from External 8-bit Memory
3 0 1 1 Execute from External 16-bit Memory
4100Boot from SPI ≤ 4K bits
5101Boot from SPI > 4K bits
6 1 1 0 Illegal – Reserved
7 1 1 1 Illegal – Reserved
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ADSP-21992
Instruction Set Description
The ADSP-21992 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the
unique architecture of the processor, offers the following benefits:
• ADSP-219x assembly language syntax is a superset of and
source code compatible (except for two data registers and
DAG base address registers) with ADSP-21xx family
syntax. It may be necessary to restructure ADSP-21xx
programs to accommodate the unified memory space of
the ADSP-21992 and to conform to its interrupt vector
map.
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
• Every instruction, but two, assembles into a single, 24-bit
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.
• Multifunction instructions allow parallel execution of an
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.
• Program flow instructions support a wider variety of con-
ditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.
Development Tools
The ADSP-21992 is supported with a complete set of
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++™ development environment. The emulator hardware that supports
other ADSP-219x DSPs also fully emulates the ADSP-21992.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathematical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural
features that improve the efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important features.
Data visualization is enhanced by a plotting package that offers
a significant level of flexibility. This graphical representation of
user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this
capability can have a significant influence on the design development schedule by increasing productivity. Statistical profiling
enables the programmer to non intrusively poll the processor as
it is running the program. This feature, unique to VisualDSP++,
enables the software developer to passively gather important code
execution metrics without interrupting the realtime characteristics of the program. Essentially, the developer can identify
bottlenecks in software quickly and efficiently. By using the
profiler, the programmer can focus on those areas in the program
that impact performance and take corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the
command line switches of the tool
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory
and timing constraints of DSP programming. These capabilities
enable engineers to develop code more effectively, eliminating the
need to start from the very beginning, when developing new
application code. The VDK features include Threads, Critical
and Unscheduled regions, Semaphores, Events, and Device flags.
The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the
VDK was designed to be scalable. If the application does not use
a specific feature, the support code for that feature is excluded
from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system
state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
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ADSP-21992
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization
in a color-coded graphical form, easily move code and data to
different areas of the DSP or external memory with the drag of
the mouse, examine run-time stack and heap usage. The Expert
Linker is fully compatible with existing Linker Definition File
(LDF), allowing the developer to move between the graphical
and textual environments.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-21992 processor to monitor and control
the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non intrusive incircuit emulation is assured by the use of the processor JTAG
interface—target system loading and timing are not affected by
the emulator.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x DSP PC plug-in cards. Third party
software tools include DSP libraries, real-time operating systems,
and block diagram design tools.
Designing an Emulator-Compatible DSP Board
The Analog Devices family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG Tes t
Access Port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be halted
to send data and commands, but once an operation has been
completed by the emulator, the DSP system is set running at full
speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the DSP JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan chains,
signal buffering, signal termination, and emulator pod logic, see
EE-68: Analog Devices JTAG Emulation Technical Reference
the
the Analog Devices website (www.analog.com)—use site search
on “EE-68.” This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-21992
architecture and functionality. For detailed information on the
ADSP-21992 embedded DSP core architecture, instruction set,
communications ports and embedded control peripherals, refer
ADSP-2199x Mixed Signal DSP Controller Hardware
to the
, and
.
RESET
PWMTRIP
TRST
).
or GND, except
DDEXT
TRST
, BMODE0,
)—these pins can be left floating. These
has an internal pull-down, but
Reference Manual
PIN FUNCTION DESCRIPTIONS
ADSP-21992 pin definitions are listed in Table 4. All ADSP21992 inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for
Unused inputs should be tied or pulled to V
for ADDR21–0, DATA15–0, PF7-0, and inputs that have
internal pullup or pull-down resistors (
BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL,
PWMSR
pins have a logic level hold circuit that prevents input from
floating internally.
should not be left floating to avoid unnecessary PWM shutdowns.
The following symbols appear in the Type column of Table 4:
G = Ground, I = Input, O = Output, P = Power Supply,
B = Bidirectional, T = Three-State, D = Digital, A = Analog,
CKG = Clock Generation pin, PU = Internal Pull-up,
PD = Internal Pull-Down, and OD = Open Drain.
on
Table 4. Pin Descriptions
Pin Type Function
A19–A0 D, OT External Port Address Bus
D15–D0 D, BT External Port Data Bus
RD D, OT External Port Read Strobe
WR D, OT External Port Write Strobe
ACK D, I External Port Access Ready Acknowledge
BR D, I, PU External Port Bus Request
BG D, O External Port Bus Grant
BGH D, O External Port Bus Grant Hang
MS0 D, OT External Port Memory Select Strobe 0
MS1 D, OT External Port Memory Select Strobe 1
MS2 D, OT External Port Memory Select Strobe 2
MS3 D, OT External Port Memory Select Strobe 3
IOMS D, OT External Port IO Space Select Strobe
BMS D, OT External Port Boot Memory Select Strobe
CLKIN D, I, CKG Clock Input/Oscillator Input/ Crystal Connection 0
XTAL D, O, CKG Oscillator Output/Crystal Connection 1
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