Analog Devices ADSP-2192 User Manual
a
DSP
Microcomputer
Preliminary Technical Data
ADSP-2192 DUAL-CORE DSP FEATURES
320 MIP Dual ADSP-219x DSP in a 144-lead LQFP
package with PCI, USB, Sub-ISA, and CardBus
Interfaces
3.3V/5V PCI 2.2 Compliant 33MHz / 32-bit Interface with
Bus Mastering over four DMA Channels with
Scatter-Gather Support
Integrated USB 1.1 Compliant Interface
AC ‘97 serial interface supports external modem,
handset, and audio codecs
Dual 160 MIPS ADSP-219x DSPs with 140K Words of
Memory and 4K x 16-bit Shared Data Memory
DSP P0 Memory Includes: 64K x 16-bit Data Memory,
16K x 24-bit Program Memory, and Boot ROM
DSP P1 Memory Includes: 32K x 16-bit Data Memory,
16K x 24-bit Program Memory, and Boot ROM
ADSP-219X
DSP CORE
DAG2
DAG1
4X4X16
4X4X16
INTERRUPT CONTROLLER/
PM ADDRESS BUS
DM ADDRESS BUS
TIMER/FLA GS
CACHE
64 X 24-BIT
PROGRAM
SEQUENCER
P0
MEMORY
16Kⴛ
ⴛ24 PM
ⴛⴛ
ⴛⴛⴛⴛ
64K
16 DM
BOOT ROM
ADDR DATA ADDR DATA
24
24
SHARED
MEMORY
4Kⴛ
ADDR DATA
ADSP-2192
ADSP-219X DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to 160
MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Single-cycle Instruction Execution
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
ⴛ16 DM
ⴛⴛ
P1
MEMORY
16Kⴛ
ⴛ24 PM
ⴛⴛ
ⴛⴛⴛⴛ
32K
16 DM
BOOT ROM
INTERRUPT CONTROLLER/
TIMER/FLAGS
CACHE
64 X 24-BIT
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
24
ADSP-219X
DSP CORE
DAG2
4X4X16
DAG1
4X4X16
INPUT
RESULT
PM DATA BUS
DM DATA BUS2416
BARREL
SHIFTER
ALU
CORE
INTERFACE
GP I/O PINS
(& OPTIONAL
SERIAL
EEPROM)
P0 DMA
CONTROLLER
FIFOS
SERIAL PORT
AC'97
COMPLIANT
ADDR DATA
SHARED DSP
I/O MAPPED
REGISTERS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
REGISTERS
REGISTERS
MULT
16 X 16-BIT
PROCESSOR P0 PROCESSOR P1
Figure 1. ADSP-2192 Dual-Core DSP Block Diagram
REV. PrA
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
PM DATA BUS
24
DM DATA BUS
16
CORE
INTERFACE
R
E
T
REGISTERS
REGISTERS
16 X 16-BIT
L
E
ADDR DATAADDR DATA
HOST PORT
PCI 2.2
OR
USB 1.1
P1 DMA
CONTROLLER
FIFOS
EMULATION
JTAG
PORT
ALU
BARREL
SHIFTER
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
P
Fax:781/326-8703 ©Analog Devices,Inc., 2000
INPUT
RESULT
I
C
M
H
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
N
I
N
A
D
MULT
A
I
T
C
R
A
A
Y
L
Y
R
ADSP-2192 October 2000
ADSP-219X DSP CORE FEATURES (CONTINUED)
• Single-Cycle Context Switch Between Two Sets of
R
P
• Parallel Execution of Computation and Memory
• Pipelined Architecture Supports Efficient Code Execu-
• Register File Computations with All Non-conditional,
• Powerful Program Sequencer Provides Zero- Overhead
• Architectural Enhancements for Compiled C/C++
• Architecture Enhancements Beyond ADSP-218x Fam-
ADSP-2192 DSP FEATURES (CONTINUED)
• Two ADSP-219x core processors (P0 and P1) on each
• 80K words of on-chip RAM on P0, configured as 64K
2 REV. PrA
I
L
E
C
Computational and DAG Registers
E
T
Instructions
tion at Speeds up to 160 MIPS
Non-parallel Computational Instructions
Looping and Conditional Instruction Execution
Code Efficiency
ily are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
ADSP-219x
DSP CORE
DAG1
4x4x16
CONNECT
REGISTER
MULT
ADSP-2192 DSP chip
words on-chip 16-bit RAM for Data Memory and 16K
words on-chip 24-bit RAM for Program Memory
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
A
N
I
M
N
H
A
D
DAG2
4x4x16
BUS
(PX)
DATA
FILE
Figure 2. ADSP-219x DSP Core
L
A
C
I
A
T
PM ADDRESS BUS
DM ADDRESS BUS
INPUT
REGISTERS
RESULT
REGISTERS
16 x 16-BI T
For current information contact Analog Devices at (781) 461-3881
• 48K words of on-chip RAM on P1, configured as 32K
words on-chip 16-bit RAM for Data Memory and 16K
words on-chip 24-bit RAM for Program Memory
• 4K words of additional on-chip RAM shared by both
cores, configured as 4K words on-chip 16-bit RAM
• Flexible power management with selectable
power-down and idle modes
• Programmable PLL supports frequency multiplication,
enabling full-speed operation from low-speed input
clocks
• 2.5V internal operation supports 3.3V/5.0V
compliant I/O
• A Host port that supports either PCI (PCI interface
and CardBus) or USB (USB 1.1 compliant) interfaces;
both with DMA capability
• Sub-ISA Interface
• An AC’97 port supporting AC’97 Revision 2.1 compli-
INTERRUPT CONTROLLER/
TIMER/ F LAG S
CACHE
64 x 24-BIT
PROGRAM
SEQUE NCER
24
24
PM DATA BUS
DM DATA BUS
BARREL
SHIFTER
24
16
INTERFACE
ALU
CORE
ant interface for External Audio, Modem, and Handset
Codecs with DMA capability
• Eight dedicated general-purpose I/O pins with integrated interrupt support
• Each DSP core has a programmable 32-bit
interval timer
• Five DMA channels available on each core
• Boot methods include booting through PCI port, USB
port, or serial EEPROM
• JTAG Test Access Port supports on-chip emulation
and system debugging
• 144-lead LQFP package (20x20x1.4mm)
General note
This data sheet provides preliminary information for the
ADSP-2192 Digital Signal Processor.
GENERAL DESCRIPTION
The ADSP-2192 is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high speed
numeric processing applications.
The ADSP-2192 combines the ADSP-219x family base
architecture (three computational units, two data address
generators and a program sequencer) into a chip with two
core processors. The ADSP-2192 includes a PCI-compatible port, a USB-compatible port, an AC’97-compatible
port, a DMA controller, a programmable timer, general
purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.
The ADSP-2192 architecture is code compatible with
ADSP-218x family DSPs. Though the architectures are
compatible, the ADSP-2192 architecture has many
enhancements over the ADSP-218x architecture. The
enhancements to computational units, data address genera-
P
R
E
T
L
E
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
tors, and program sequencer make the ADSP-2192 more
E
flexible and even easier to program than the
R
P
ADSP-218x DSPs.
E
T
Indirect addressing options provide addressing flexibility—
premodify with no update, post-modify with update, preand post-modify by an immediate 8-bit, two’s-complement
value and base address registers for easier implementation
of circular buffering.
The ADSP-2192 integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and
96K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery operated portable equipment. The ADSP-2192 is available in a
144-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2192 operates with a 6.25-ns instruction cycle time
(160 MIPS). All instructions, except two multiword
instructions, can execute in a single DSP cycle.
The ADSP-2192’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, each DSP core within the
ADSP-2192 can:
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
These operations take place while the processor
continues to:
• Receive and/or transmit data through the Host port
• Receive or transmit data through the AC’97
• Decrement the two timers
DSP Core Architecture
The ADSP-2192 instruction set provides flexible data
moves and multifunction (one or two data moves with a
computation) instructions. Every single-word instruction
can be executed in a single processor cycle. The
ADSP-2192 assembly language uses an algebraic syntax for
ease of coding and readability. A comprehensive set of
development tools supports program development.
Figure 1 on page 1 shows the architecture of the
ADSP-219x dual-core DSP. Each core contains three independent computational units: the ALU, the
multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data from the register file and
have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add and
multiply/subtract operations. The MAC has two 40-bit
N
H
C
A
D
(PCI or USB interfaces)
L
A
C
I
A
T
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at (781) 461-3881
ADSP-2192October 2000
accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The
shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
Register-usage rules influence placement of input and
results within the computational units. For most operations,
the computational units’ data registers act as a data register
file, permitting any input or result register to provide input
to any unit for a computation. For feedback operations, the
computational units let the output (result) of any unit be
input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data
registers may provide inputs or receive results from each
computational unit. For more information, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps,
subroutine calls, and low interrupt overhead. With internal
loop counters and loop stacks, the ADSP-2192 executes
looped code with zero overhead; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches. Each DAG maintains
and updates four 16-bit address pointers. Whenever the
pointer is used to access data (indirect addressing), it is preor post-modified by the value of one of four possible modify
registers. A length value and base address may be associated
with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow
linear or circular addressing within 64 Kword boundaries of
each of the memory pages, but these buffers may not cross
page boundaries. Secondary registers duplicate all the primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
Program memory can store both instructions and data, permitting the ADSP-2192 to fetch two operands in a single
cycle, one from program memory and one from data memory. The DSP’s dual memory buses also let the ADSP-2192
core fetch an operand from data memory and the next
instruction from program memory in a single cycle.
R
A
N
I
M
P
R
E
T
L
E
I
C
H
D
N
A
I
C
T
A
A
3REV. PrA
Y
L
Y
R
M
H
I
D
N
N
A
A
I
T
C
A
A
L
ADSP-2192 October 2000
E
T
L
E
I
C
DSP Peripherals Architecture
Figure 1 on page 1 shows the DSP’s on-chip peripherals,
R
P
which include the Host port (PCI or USB), AC’97 port,
JTAG test and emulation port, flags, and interrupt
controller.
The ADSP-2192 can respond to up to thirteen interrupts at
any given time. A list of these interrupts appears in Table 1.
The AC’97 Codec port on the ADSP-2192 provides a complete synchronous, full-duplex serial interface. This
interface completely supports the AC’97 standard.
The ADSP-2192 provides up to eight general-purpose I/O
pins, which are programmable as either inputs or outputs.
These pins are dedicated general purpose Programmable
For current information contact Analog Devices at (781) 461-3881
The programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) is decremented
every n cycles where n-1 is a scaling value stored in a 16-bit
register (TSCALE). When the value of the count register
reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD).
Memory Architecture
The ADSP-2192 provides 140K words of on-chip SRAM
memory. This memory is divided into Program and Data
Memory blocks in each DSP’s memory map. In addition to
the internal memory space, the two cores can address two
additional and separate off-core memory spaces: I/O space
and shared memory space, as shown in Figure 3 on page 4.
Flag pins.
PAGE 2
PAGE 1
PAGE 0
DSP P0
MEMORY MAP
SHARED RAM
(16x4K)
RESERVED
PROGRAM RO M ,
24x4K
PROGRAM RA M,
(24x16K )
DATA RAM
BLOCK3
(16x16K )
DATA RAM
BLOCK2
(16x16K )
DATA RAM
BLOCK1
(16x16K )
DATA RAM
BLOCK0
(16x16K )
ADDRESS
0x02 0FFF
0x02 0000
0x01 FFF F
0x01 5000
0x01 4FFF
0x01 4000
0x01 3FFF
0x01 0000
0x00 FFF F
0x00 C000
0x00 BFFF
0x00 8000
0x00 7FFF
0x00 4000
0x00 3FFF
0x00 0000
SAME
SHARED
DSP I/O
MAPPED
REGISTERS
PAGES 0-255
(16x256)
ADDRESS
0xFF FF
0x00 00
PAGE 2
PAGE 1
PAGE 0
DSP P1
MEMORY MAP
SHARED RAM
(16x4K)
RESERVED
PROGRAM RO M ,
24x4K
PROGRAM RA M,
(24x16K)
RESERVED
DATA RAM
BLOCK1
(16x16K)
DATA RAM
BLOCK0
(16x16K)
ADDRESS
0x02 0FFF
0x02 0000
0x01 FFF F
0x01 5000
0x01 4FFF
0x01 4000
0x01 3FFF
0x01 0000
0x00 FFFF
0x00 8000
0x00 7FFF
0x00 4000
0x00 3FFF
0x00 0000
Figure 3. ADSP-2192 Internal/External Memory, Boot Memory, and I/O Memory Maps
The ADSP-2192’s two cores can access 80K and 48K locations that are accessible through two 24-bit address buses,
the PMA and DMA buses. The DSP uses slightly different
N
I
M
I
L
E
4 REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
P
R
T
E
C
H
D
N
A
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
mechanisms to generate a 24-bit address for each bus. The
E
DSP has three functions that support access to the full
R
P
memory map.
E
T
• The DAGs generate 24-bit addresses for data fetches
• The Program Sequencer generates the addresses for
• For indirect jumps and calls that use a 16-bit DAG
Each ADSP-219x DSP core has an on-chip ROM that
holds boot routines. For more information, see “Booting
Modes” on page 31.
Interrupts
The interrupt controller lets the DSP respond to thirteen
interrupts with minimum overhead. The controller implements an interrupt priority scheme as shown in Table 1 on
page 5. Applications can use the unassigned slots for soft-
ware and peripheral interrupts. The DSP’s Interrupt
Control (ICNTL) register (shown in Table 3 on page 6)
provides controls for global interrupt enable, stack interrupt
configuration, and interrupt nesting.
N
H
C
A
D
from the entire DSP memory address range. Because
DAG index (address) registers are 16 bits wide and
hold the lower 16-bits of the address, each of the DAGs
has its own 8-bit page register (DMPGx) to hold the
most significant eight address bits. Before a DAG generates an address, the program must set the DAG’s
DMPGx register to the appropriate memory page.
instruction fetches. For relative addressing instructions, the program sequencer bases addresses for
relative jumps, calls, and loops on the 24-bit Program
Counter (PC). In direct addressing instructions
(two-word instructions), the instruction provides an
immediate 24-bit address value. The PC allows linear
addressing of the full 24 bit address range.
address register for part of the branch address, the Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program must set the program sequencer’s IJPG register to
the appropriate memory page.
I
C
T
A
A
L
For current information contact Analog Devices at (781) 461-3881
ADSP-2192October 2000
Table 2 on page 5 shows the interrupt vector and
DSP-to-DSP semaphores at reset of each of the peripheral
interrupts. The peripheral interrupt’s position in the
IMASK and IRPTL register and its vector address depend
on its priority level, as shown in Table 1 on page 5.
Table 1. Interrupt Vector Table
Bit
0 1 Reset (non-maskable) 0x00
12 Powerdown
2 3 Kernel interrupt (single
3 4 Stack Status 0x0C
45 Mailbox 0x10
56 Timer 0x14
6 7 Reserved 0x18
7 8 PCI Bus Master 0x1C
8 9 DSP-DSP 0x20
9 10 FIFO0 Transmit 0x24
10 11 FIFO0 Receive 0x28
11 12 FIFO1 Transmit 0x2C
12 13 FIFO1 Receive 0x30
13 14 Reserved 0x34
14 15 Reserved 0x38
15 16 AC’97 Frame 0x3C
1
Priorit
y
The interrupt vector address values are represented as offsets from
address 0x01 0000. This address corresponds to the start of Program
Memory in DSP P0 and P1.
Interrupt
(non-maskable)
step)
Vector
Address
1
Offset
0x04
0x08
Table 2. DSP-to-DSP Semaphores Register Table
Flag
Bit
0 Output DSP-DSP Semaphore 0
1 Output DSP-DSP Semaphore 1
2 Output DSP-DSP Interrupt
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Direction
Function
P
R
E
T
L
E
I
C
M
H
I
D
DSP
Core
Flag
In
N
I
N
A
A
C
T
R
A
A
Y
L
5REV. PrA
Y
R
M
H
I
D
A
N
N
A
L
A
C
I
A
T
Function
Access Status
(write from DSP pending)
ADSP-2192 October 2000
E
T
L
E
I
C
Direction
Table 2. DSP-to-DSP Semaphores Register Table
R
P
Flag
Bit
3 Reserved
4 Reserved
5 Reserved
6 Reserved
7 Output Register Bus Lock
8InputDSP-DSP Semaphore 00
9InputDSP-DSP Semaphore 11
10 Input DSP-DSP Interrupt 2
11 Input Reserved
12 Input AC’97 Register - PDC Bus
13 Input PDC Interface Busy Status
14 Input Reserved
15 Input Register Bus Lock Status 7
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially.
Interrupts can be masked or unmasked with the IMASK
register. Individual interrupt requests are logically ANDed
with the bits in IMASK; the highest priority unmasked
interrupt is then selected. The emulation, power down, and
reset interrupts are nonmaskable with the IMASK register,
but software can use the DIS INT instruction to mask the
power down interrupt.
Table 3. Interrupt Control (ICNTL) register bits
Bit Description
For current information contact Analog Devices at (781) 461-3881
Table 3. Interrupt Control (ICNTL) register bits
DSP
Core
Flag
In
4
5
Bit Description
11 Loop stack interrupt enable
12 Low power idle enable
13–15 Reserved
The IRPTL register is used to force and clear interrupts.
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. To support
interrupt, loop, and subroutine nesting, the PC stack is
33-levels deep, the loop stack is eight-levels deep, and the
status stack is sixteen-levels deep. To prevent stack overflow,
the PC stack can generate a stack level interrupt if the PC
stack falls below 3 locations full or rises above 28
locations full.
The following instructions globally enable or disable interrupt servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG
and computational registers exist. Switching between the
primary and secondary registers lets programs quickly service interrupts, while preserving the DSP’s state.
DMA Controller
The ADSP-2192 has a DMA controller that supports automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2192’s internal memory and any of its DMA capable
peripherals. Additionally, DMA transfers can also be
accomplished between any of the DMA capable peripherals. DMA capable peripherals include the PCI and AC’97
ports. Each individual DMA capable peripheral has a dedicated DMA channel. DMA sequences do not contend for
bus access with the DSP core; instead, DMAs “steal” cycles
to access memory.
All DMA transfers use the Program Memory (PMA/PMD)
buses shown in Figure 1 on page 1.
0–3 Reserved
4 Interrupt nesting enable
5 Global interrupt enable
6 Reserved
7 MAC biased rounding enable
8–9 Reserved
10 PC stack interrupt enable
6 REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
External Interfaces
There are several different interfaces supported on the
ADSP-2192. These include both internal and external
interfaces. The three separate PCI configuration spaces are
programmable to set up the device in various Plug-and-Play
configurations.
The ADSP-2192 provides the following types of external
interfaces: PCI, USB, Sub-ISA, CardBus, AC’97, and
serial EEPROM. The following sections discuss those
I
C
M
H
I
D
N
N
A
interfaces.
P
R
E
T
L
E
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
PCI 2.2 Host Interface
E
R
The ADSP-2192 includes a 33MHz, 32 bit bus master PCI
P
E
interface that is compliant with revision 2.2 of the PCI spec-
T
ification. This interface supports the high data rates.
USB 1.1 Host Interface.
The ADSP-2192 USB interface enables the host system to
configure and attach a single device with multiple interfaces
and various endpoint configurations. The advantages of this
design include:
• Programmable descriptors and class-specific command
• An on-chip 8052 compatible MCU allows the user to
• Total of 8 user-defined endpoints provided. Endpoints
Sub-ISA Interface
In systems which combine the ADSP-2192 chip with other
devices on a single PCI interface, the ADSP-2192 Sub-ISA
mode is used to provide a simpler interface which bypasses
the ADSP-2192’s PCI interface. In this mode the Combo
Master assumes all responsibility for interfacing the function to the PCI bus, including provision of Configuration
Space registers for the ADSP-2192 system as a separate
PnP function. In Sub-ISA Mode the PCI Pins are reconfigured for ISA operation.
CardBus Interface
The CardBus standard provides higher levels of performance than the 16-bit PC Card standard. For example,
32-bit CardBus cards are able to take advantage of internal
bus speeds that can be as much as four- to six-times faster
than 16-bit PC Cards. This design provides for a compact,
rugged card that can be inserted completely within its host
computer without any external cabling.
Since CardBus performance attains the same high level as
the host platform's internal (PCI) system bus, it is an excellent way to add high speed communications to the notebook
form factor. In addition, CardBus PC Cards operate at a
power-saving 3.3 volts, extending battery life in most
configurations.
This new 32-bit CardBus technology provides up to
132Mbytes per second of bandwidth. This performance
makes CardBus an ideal vehicle to furnish the demands of
high throughput communications such as ADSL.
CardBus PC Cards generate less heat and consume less
power. This is attained by:
• Low voltage operation at 3.3V.
• Software control of clock speed.
• Advanced power management mechanism
N
H
C
A
D
interpreter.
soft download different configurations and support
standard or class-specific commands.
can be configured as either BULK, ISO, or INT and
can be grouped and assigned to any interface.
L
A
C
I
A
T
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at (781) 461-3881
ADSP-2192October 2000
AC’97 2.1 External Codec Interface
The industry standard AC’97 serial interface (AC-Link)
incorporates a 7-pin digital serial interface that links compliant codecs to the ADSP-2192. The ACLink implements
a bi-directional, fixed rate, serial PCM digital stream. It
handles multiple input and output audio streams as well as
control and status register accesses using a time division
multiplex scheme.
Serial EEPROM Interface
The Serial EEPROM for the ADSP-2192 can overwrite the
following information which is returned during the USB
GET DEVICE DESCRIPTOR command. During the
Serial EEPROM initialization procedure, the DSP is
responsible for writing the USB Descriptor Vendor ID,
USB Descriptor Product ID, USB Descriptor Release
Number, and USB Descriptor Device Attributes registers
to change the default settings.
All descriptors can be changed when downloading the
RAM-based MCU re-numeration code, except for the
Manufacturer and Product, which are supported in the
CONFIG DEVICE and cannot be overwritten or changed
by the Serial EEPROM.
• Vendor ID (0x0456 ADI)
• Product ID (0x2192)
• Device Release Number (0x0100)
• Device Attributes (0x80FA): SP (1=self-powered,
0=bus-powered, default=0); RW (1=have remote
wake-up capability, 0=no remote wake-up capability,
deafult=0); C[7:0] (power consumption from bus
expressed in 2mA units; default = 0xFA 500mA)
• Manufacturer (ADI)
• Product (ADI Device)
Internal Interfaces
The ADSP-2192 provides three types of internal interfaces:
registers, codec, and DSP memory buses. The following
sections discuss those interfaces.
Register Interface
The register interface allows the PCI interface, USB interface, and both DSPs to communicate with the I/O
Registers. These registers map into DSP, PCI, and USB I/O
spaces.
Register Spaces
Several different register spaces are defined on the
ADSP-2192, as described in the following sections.
PCI Configuration Space
These registers control the configuration of the PCI Interface. Most of these registers are only accessible via the PCI
Bus although a subset is accessible to the DSP for configuration during the boot.
R
P
E
T
L
E
I
C
M
H
D
I
N
N
A
A
I
T
R
C
A
A
7REV. PrA
Y
L
Y
R
M
H
I
D
N
N
A
A
I
T
C
A
A
L
ADSP-2192 October 2000
DSP Core Register Space
Each DSP has an internal register that is accessible with no
R
P
latency. These registers are accessible only from within the
DSP, using the REG( ) instruction.
Peripheral Device Control Register Space
This Register Space is accessible by both DSPs, the PCI,
Sub-ISA, and USB Buses. Note that certain sections of this
space are exclusive to either the PCI, USB, or Sub-ISA
Buses. These registers control the operation of the peripherals of the ADSP-2192. The DSP accesses these registers
using the IO( ) instruction.
USB Register Space
These registers control the operation and configuration of
the USB Interface. Most of these registers are only accessible via the USB Bus, although a subset is accessible to the
DSP.
Card Bus interface
The ADSP-2192’s PC Card Bus interface meets the state
and timing specifications defined for PCMCIA’s PC Card
Bus Standard April 1998 Release 6.1. It supports up to
three card functions. Multiple function PC cards require a
separate set of Configuration registers per function. A primary Card Information Structure common to all functions
is required. Separate secondary Card Information Structures, one per function, are also required. Data for each CIS
is loaded by the DSP during bootstrap loading.
The host PC can read the CIS data at any time. If needed,
the WAIT control can be activated to extend the read operation to meet bus write access to the CIS data.
Using the PCI Interface
The ADSP-2192 includes a 33-Mhz, 32-bit PCI interface
to provide control and data paths between the part and the
host CPU. The PCI interface is compliant with the PCI
Local Bus Specification Revision 2.2. The interface supports both bus mastering as well as bus target interfaces.
The PCI Bus Power Management Interface Specification
Revision 1.1 is supported and additional features as needed
by PCI designs are included.
Ta rg e t / S l a ve In te r fa c e
The ADSP-2192 PCI interface contains three separate
functions, each with its own configuration space. Each
function contains four base address registers used to access
ADSP-2192 control registers and DSP memory. Base
Address Register (BAR) 1 is used to point to the control
registers. The addresses specified in these tables are offsets
from BAR1 in each of the functions. PCI memory-type
accesses are used to read and write the registers.
8 REV. PrA
I
L
E
C
E
T
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at (781) 461-3881
DSP memory accesses use BAR2 or BAR3 of each function. BAR2 is used to access 24-bit DSP memory; BAR3
accesses 16-bit DSP memory. Maps of the BAR2 and
BAR3 registers appear in Table 8 on page 14 and Table 9
on page 15.
The lower half of the allocated space pointed to by each
DSP memory BAR is the DSP memory for DSP core P0.
The upper half is the memory space associated with DSP
core P1. PCI transactions to and from DSP memory use the
DMA function within the DSP core. Thus each word transferred to or from PCI space uses a single DSP clock cycle to
perform the internal DSP data transfer. Byte-wide accesses
to DSP memory are not supported.
I/O type accesses are supported via BAR4. Both the control
registers accessible via BAR1 and the DSP memory accessible via BAR2 and BAR3 can be accessed with I/O
accesses. Indirect access is used to read and write both the
control registers and the DSP memory. For the control register accesses, a address register points to the word to be
accessed while a separate register is used to transfer the
data. Read/write control is part of the address register. Only
16-bit accesses are possible via the I/O space.
A separate set of registers is used to perform the same function for DSP memory access. Control for these accesses
includes a 24-bit/16-bit select as well as direction control.
The data register for DSP memory accesses is a full 24-bits
wide. 16-bit accesses will be loaded into the lower 16-bits of
the register. Table 10 on page 17 lists the registers directly
accessible from BAR4.
Bus Master Interface
As a bus master, the PCI interface can transfer DMA data
between system memory and the DSP. The control registers
for these transfers are available both to the host and to the
DSPs. Four channels of bus-mastering DMA are supported
on the ADSP-2192.
Two channels are associated with the receive data and two
are associated with the transmit data. The internal DSPs
will typically control initiation of bus master transactions.
DMA host bus master transfers can specify either standard
circular buffers in system memory or perform scatter-gather
DMA to host memory.
Each bus master DMA channel includes 4 registers to specify a standard circular buffer in system memory. The Base
Address points to the start of the circular buffer. The Current Address is a pointer to the current position within that
buffer. The Base Count specifies the size of the buffer in
bytes, while the Current Count keeps track of how many
bytes need to be transferred before the end of the buffer is
reached. When the end of the buffer is reached, the channel
can be programmed to loop back to the beginning and continue the transfers. When this looping occurs, a Status bit
will be set in the DMA Control Register.
P
R
E
T
L
E
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
When transferring samples to and from DSP memory, the
E
PCI DMA controller can be programmed to perform scat-
R
P
ter-gather DMA. This mode allows the data to be split up
E
T
in memory, and yet be able to be transferred to and from the
ADSP-2192 without processor intervention. In scatter-gather mode, the DMA controller can read the memory
address and word count from an array of buffer descriptors
called the Scatter-Gather Descriptor (SGD) table. This
allows the DMA engine to sustain DMA transfers until all
buffers in the SGD table are transferred.
To initiate a scatter-gather transfer between memory and
the ADSP-2192, the following steps are involved:
1. Software driver prepares a SGD table in system mem-
2. Initialize DMA control registers with transfer specific
3. Software driver initializes the hardware pointer to the
4. Engage scatter-gather DMA by writing the start value
5. The ADSP-2192 will then pull in samples as pointed to
6. Bits in the PCI Control/Status register control whether
N
H
C
A
D
ory. Each descriptor is eight bytes long and consists of
an address pointer to the starting address and the transfer count of the memory buffer to be transferred. In any
given SGD table, two consecutive SGDs are offset by
eight bytes and are aligned on a 4-byte boundary. Each
SGD contains:
a. Memory Address (Buffer Start) – 4 bytes
b. Byte Count (Buffer Size) – 3 bytes
c. End of Linked List (EOL) – 1 bit (MSBit)
d. Flag – 1 bit (MSBit – 1)
information such as number of total bytes to transfer,
direction of transfer, etc.
SGD table.
to the PCI channel Control/Status register.
by the descriptors as needed by the DMA engine.
When the EOL is reached, a status bit will be set and
the DMA will end if the data buffer is not to be looped.
If looping is to occur, DMA transfers will continue
from the beginning of the table until the channel is
turned off.
an interrupt occurs when the EOL is reached or when
the FLAG bit is set.
I
C
T
A
A
L
For current information contact Analog Devices at (781) 461-3881
ADSP-2192October 2000
Scatter-gather DMA uses four registers. In scatter-gather
mode the functions of the registers are mapped as follows:
Table 4. Register-Mapping in Scatter-Gather Mode
Standard Circular Buffer
Mode
Base Address SGD Table Pointer
Current Address SGD Current Pointer
Base Count SGD Pointer
Current Count Current SGD Count
In either mode of operation, interrupts can be generated
based upon the total number of bytes transferred. Each
channel has two 24-bit registers to count the bytes transferred and generate interrupts as appropriate. The
Interrupt Base Count register specifies the number of bytes
to transfer prior to generating an interrupt. The Interrupt
Count register specifies the current number left prior to
generating the interrupt. When the Interrupt Count register
reaches zero, a PCI interrupt can be generated. Additionally, the Interrupt Count register will be reloaded from the
Interrupt Base Count and continue counting down for the
next interrupt.
PCI Interrupts
There are a variety of potential sources of interrupts to the
PCI host besides the bus master DMA interrupts. A single
interrupt pin, INTA
to the host. The PCI Interrupt Register consolidates all of
the possible interrupt sources; the bits of this register are
shown in Table 5 on page 9. The register bits are set by the
various sources, and can be cleared by writing a 1 to the
bit(s) to be cleared.
PCI Control Register.
This register must be initialized by the DSP ROM code
prior to PCI enumeration. (It has no effect in ISA or USB
mode.) Once the Configuration Ready bit has been set to 1,
the PCI Control Register becomes read-only, and further
access by the DSP to configuration space is disallowed. The
bigs of this register are shown in Table 6 on page 10.
is used to signal these interrupts back
Scatter-Gather Mode
Function
Address
Table 5. PCI Interrupt Register
Bit Name Comments
0 Reserved Reserved
1 Rx0 DMA Channel Interrupt Receive Channel 0 Bus Master Transactions
2 Rx1 DMA Channel Interrupt Receive Channel 1 Bus Master Transactions
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
P
R
E
T
L
E
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
A
Y
L
9REV. PrA
Y
R
M
H
I
D
N
N
A
A
I
T
C
A
A
L
ADSP-2192 October 2000
E
T
L
E
I
C
Table 5. PCI Interrupt Register (Continued)
R
P
Bit Name Comments
3 Tx0 DMA Channel Interrupt Transmit Channel 0 Bus Master Transactions
4 Tx1 DMA Channel Interrupt Transmit Channel 1 Bus Master Transactions
5 Incoming Mailbox 0 PCI Interrupt PCI to DSP Mailbox 0 Transfer
6 Incoming Mailbox 1 PCI Interrupt PCI to DSP Mailbox 1 Transfer
7 Outgoing Mailbox 0 PCI Interrupt DSP to PCI Mailbox 0 Transfer
8 Outgoing Mailbox 1 PCI Interrupt DSP to PCI Mailbox 1 Transfer
9 Reserved
10 Reserved
11 GPIO Wakeup I/O Pin Initiated
12 AC’97 Wakeup AC’97 Interface Initiated
13 PCI Master Abort Interrupt PCI Interface Master Abort Detected
For current information contact Analog Devices at (781) 461-3881
14 PCI Target Abort Interrupt PCI Interface Target Abort Detected
15 Reserved
Table 6. PCI Control Register
Bit Name Comments
1-0 PCI Functions
Configured
2Configuration
Ready
15-3 Reserved
ADSP-2192 PCI Configuration Space
The ADSP-2192 PCI Interface provides three separate
configuration spaces, one for each possible function. This
document describes the registers in each function, their
reset condition, and how the three functions interact to
access and control the ADSP-2192 hardware.
Similarities Between the Three PCI Functions
Each function contains a complete set of registers in the
predefined header region as defined in the PCI Local Bus
Specification Revision 2.2. In addition, each function contains the optional registers to support PCI Bus Power
10 REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
00 = one PCI Function
enabled, 01= two functions,
10= three functions
When 0, disables PCI
accesses to the ADSP-2192
(terminated with Retry).
Must be set to 1 by DSP
ROM code after initializing
configuration space. Once
1, cannot be written to 0.
Management. Generally, registers that are unimplemented
or read-only in one function are similarly defined in the
other functions. Each function contains four base address
registers that are used to access ADSP-2192 control registers and DSP memory.
Base address register (BAR) 1 is used to access the
ADSP-2192 control registers. Accesses to the control registers via BAR1 uses PCI memory accesses. BAR1 requests a
memory allocation of 1024 bytes. Access to DSP memory
occurs via BAR2 and BAR3. BAR2 is used to access 24-bit
DSP memory (for DSP program downloading) while BAR3
is used to access 16-bit DSP memory. BAR4 provides I/O
space access to both the control registers and the DSP
memory.
Table 7 on page 11 shows the configuration space headers
for the three spaces. While these are the default uses for
each of the configurations, they can be redefined to support
any possible function by writing to the class code register of
that function during boot. Additionally, during boot time,
the DSP can disable one or more of the functions. If only
two functions are enabled, they will be functions 0 and 1. If
only one function is enabled, it will be function 0.
Interactions Between the Three PCI Configurations
Because the configurations must access and control a single
set of resources, potential conflicts can occur between the
control specified by the configuration.
N
I
M
I
L
P
R
E
T
E
C
H
D
N
A
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
Target accesses to registers and DSP memory can go
E
through any function. As long as the Memory Space access
R
P
enable bit is set in that function, then PCI memory accesses
E
T
whose addresses match the locations programmed into a
function, BARs 1-3 will be able to read or write any visible
Table 7. PCI Configuration Space 0, 1, and 2
Address Name Reset Comments
C
H
D
N
A
I
C
T
A
A
L
For current information contact Analog Devices at (781) 461-3881
register or memory location within the ADSP-2192. Similarly, if IO Space access enable is set, then PCI I/O accesses
can be performed via BAR4.
Within the Power Management section of the configuration
blocks, there are a few interactions. The part will stay in the
highest power state between the three configurations.
ADSP-2192October 2000
0x010x00
0x030x02
0x050x04
0x070x06
0x08 Revision ID 0x0 Writable from the DSP during initialization
0x0B0x09
0x0C Cache Line Size 0x0 Read-only
0x0D Latency Timer 0x0
0x0E Header Type 0x80 Multifunction bit set
0x0F BIST 0x0 Unimplemented
0x130x10
Vendor ID 0x11D4 Writable from the DSP during initialization
Config 0 Device ID 0x2192 Writable from the DSP during initialization
Config 1 Device ID 0x219A Writable from the DSP during initialization
Config 2 Device ID 0x219E Writable from the DSP during initialization
Command Register 0x0 Bus Master, Memory Space Capable, I/O
Space Capable
Status Register 0x0 Bits enabled: Capabilities List, Fast B2B,
Medium Decode
Class Code 0x48000 Writable from the DSP during initialization
Base Address1 0x08 Register Access for all ADSP-2192 Registers,
Prefetchable Memory
0x170x14
0x1B0x18
0x1F0x1C
0x230x20
0x270x24
0x2B- 0x28 Config 0 Cardbus CIS Pointer 0x1FF03 CIS RAM Pointer - Function 0 (Read Only).
Base Address2 0x08 24-bit DSP Memory Access
Base Address3 0x08 16-bit DSP Memory Access
Base Address4 0x01 I/O access for control registers and DSP
memory
Base Address5 0x0 Unimplemented
Base Address6 0x0 Unimplemented
Config 1 Cardbus CIS Pointer 0x1FE03 CIS RAM Pointer - Function 1 (Read Only).
E
T
L
E
I
C
M
H
Config 2 Cardbus CIS Pointer 0x1FD03 CIS RAM Pointer - Function 2 (Read Only).
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
P
R
I
D
N
N
A
A
I
C
T
R
A
11REV. PrA
A
Y
L
Y
R
M
H
A
N
I
D
N
A
L
A
C
I
A
T
Config 1 Subsystem Device ID 0x219A Writable from the DSP during initialization
Config 2 Subsystem Device ID 0x219E Writable from the DSP during initialization
ADSP-2192 October 2000
E
T
L
E
I
C
Table 7. PCI Configuration Space 0, 1, and 2 (Continued)
R
P
Address Name Reset Comments
0x2D- 0x2C Subsystem Vendor ID 0x11D4 Writable from the DSP during initialization
0x2F- 0x2E Config 0 Subsystem Device ID 0x2192 Writable from the DSP during initialization
0x33- 0x30 Expansion ROM Base Address 0x0 Unimplemented
0x34 Capabilities Pointer 0x40 Read-only
0x3C Interrupt Line 0x0
For current information contact Analog Devices at (781) 461-3881
0x3D Interrupt Pin 0x1 Uses INTA
0x3E Min_Gnt 0x1 Read-only
0x3F Max_Lat 0x4 Read-only
0x40 Capability ID 0x1 Power Management Capability Identifier
0x41 Next_Cap_Ptr 0x0 Read-only
0x430x42
0x450x44
0x46 Power Management Bridge 0x0 Unimplemented
0x47 Power Management Data 0x0 Unimplemented
ADSP-2192 PCI Memory Map
The ADSP-2192 On-Chip Memory is mapped to the PCI
Address Space. Because some ADSP-2192 Memory Blocks
are 24-bits wide (Program Memory) while others are
16-bits (Data Memory), two different footprints are available in PCI Address Space. These footprints are available to
each PCI function by accessing different PCI Base Address
Registers (BAR).
BAR2 supports 24-bit “Unpacked” Memory Access. BAR3
supports 16-bit “Packed” Memory Access.
In 24-bit (BAR2) Mode, each 32 bits (4 Consecutive PCI
Byte Address Locations, which make up one PCI Data
word) correspond to a single ADSP-2192 Memory Location. BAR2 Mode is typically used for Program Memory
Access. Byte3 is always unused. Bytes[2:0] are used for
24-bit Memory Locations. Bytes[2:1] are used for 16-bit
Memory Locations as shown in the example figure.
In 16-bit (BAR3) Mode, each 32-bit (4 Consecutive PCI
Byte Address Locations) PCI Data word corresponds to
two ADSP-2192 Memory Locations. Bytes[3:2] contain
one 16-bit Data Word, Bytes[1:0] contain a second 16-bit
12 REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Power Management Capabilities 0x6C22 Writable from the DSP during initialization
Power Management Control/Status 0x0 Bits 15 and 8 initialized only on Power-up
Data Word. BAR3 Mode is typically used for Data Memory
Access. Only the 16 MSBs of a Data Word are accessed in
24-bit Blocks; the 8 LSBs are ignored.
Pin
P
R
E
T
L
E
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
A
Y
L
P
R
E
T
L
E
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
A
Y
L
For current information contact Analog Devices at (781) 461-3881
PCI DWORD
BYTE3 BYTE2 BYTE1 BYTE0
ADSP-2192October 2000
DSP Word AddressPCI Byte Address
BYTE3 IS ALWAYS UNUSED.
BYTE0 IS UNUSED BY 16-BIT
MEMORY LOCATIONS.
ALLOWED BYTE ENABLES:
C/BE
= 0000
C/BE
= 1000
Figure 4. PCI Addressing for 24-bit and 16-bit Memory Blocks in 24-bit Access (BAR2) Mode
ALL BYTES ARE USED.
ALLOWED BYTE ENABLES:
C/BE
= 1100
= 0011
C/BE
C/BE
= 0000
0x0 0000
0x0 FFFC
0x1 0000
0x1 FFFC
0x0 0000
0x0 7FFE
0x0 8000
16K x 24-bit Block
UNUSED
16K x 16-bit Block
PCI DWORD
BYTE3 BYTE2 BYTE1 BYTE0
Data Word NData Word N+1
Data Word N
Data Wo rd N + 1
16K x 24-bit Block
UNUSED
UNUSED
0x0000
0x3FFF
0x4000
0x7FFF
DSP Word AddressPCI Byte Address
0x0000
0x3FFF
0x4000
16K x 16-bit Block
0x0 FFFE
Figure 5. PCI Addressing for 24-bit and 16-bit Memory Blocks in 16-bit Access (BAR3) Mode.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
UNUSED
0x7FFF
R
P
E
T
E
L
I
C
M
H
I
D
N
N
A
A
I
T
C
R
A
13REV. PrA
A
Y
L
Y
R
M
H
I
D
N
N
A
A
I
T
C
A
A
L
ADSP-2192 October 2000
E
T
L
E
I
C
24-bit PCI DSP Memory Map (BAR2)
The Complete PCI Address Footprint for the ADSP-2192
R
P
DSP Memory Spaces in 24-bit (BAR 2) Mode is as follows:
Table 8. 24-bit PCI DSP Memory Map (BAR 2 Mode)
Block Byte3 Byte2 Byte1 Byte0 Offset
DSP P0 Data RAM Block 0 UNUSED D[15:8] D[7:0] UNUSED 0x0000 0000
DSP P0 Data RAM Block 1 UNUSED D[15:8] D[7:0] UNUSED 0x0001 0000
DSP P0 Data RAM Block 2 UNUSED D[15:8] D[7:0] UNUSED 0x0002 0000
DSP P0 Data RAM Block 3 UNUSED D[15:8] D[7:0] UNUSED 0x0003 0000
DSP P0 Program RAM Block UNUSED D[23:16] D[15:8] D[7:0] 0x0004 0000
DSP P0 Program ROM Block UNUSED D[23:16] D[15:8] D[7:0] 0x0005 0000
Reserved Space RESERVED RESERVED RESERVED RESERVED 0x0005 4000
DSP P1 Data RAM Block 0 UNUSED D[15:8] D[7:0] UNUSED 0x0008 0000
For current information contact Analog Devices at (781) 461-3881
UNUSED D[15:8] D[7:0] UNUSED 0x0000 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0000 FFFC
UNUSED D[15:8] D[7:0] UNUSED 0x0001 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0001 FFFC
UNUSED D[15:8] D[7:0] UNUSED 0x0002 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0002 FFFC
UNUSED D[15:8] D[7:0] UNUSED 0x0003 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0003 FFFC
UNUSED D[23:16] D[15:8] D[7:0] 0x0004 0004
:
UNUSED D[23:16] D[15:8] D[7:0] 0x0004 FFFC
UNUSED D[23:16] D[15:8] D[7:0] 0x0005 0004
:
UNUSED D[23:16] D[15:8] D[7:0] 0x0005 3FFC
:
RESERVED RESERVED RESERVED RESERVED 0x0007 FFFC
UNUSED D[15:8] D[7:0] UNUSED 0x0008 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0008 FFFC
N
I
M
I
L
E
14 REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
P
R
T
E
C
H
D
N
A
A
I
T
C
R
A
A
Y
L
Y
R
A
N
I
M
I
L
Table 8. 24-bit PCI DSP Memory Map (BAR 2 Mode) (Continued)
E
R
P
Block Byte3 Byte2 Byte1 Byte0 Offset
E
T
DSP P1 Data RAM Block 1 UNUSED D[15:8] D[7:0] UNUSED 0x0009 0000
Reserved Space. UNUSED D[15:8] D[7:0] UNUSED 0x000A 0000
DSP P1 Program RAM Block UNUSED D[23:16] D[15:8] D[7:0] 0x000C 0000
DSP P1 Program ROM Block UNUSED D[23:16] D[15:8] D[7:0] 0x000D 0000
Reserved Space RESERVED RESERVED RESERVED RESERVED 0x000D 4000
C
H
D
N
A
I
C
T
A
A
L
For current information contact Analog Devices at (781) 461-3881
UNUSED D[15:8] D[7:0] UNUSED 0x0009 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x0009 FFFC
UNUSED D[15:8] D[7:0] UNUSED 0x000A 0004
:
UNUSED D[15:8] D[7:0] UNUSED 0x000B FFFC
UNUSED D[23:16] D[15:8] D[7:0] 0x000C 0004
:
UNUSED D[23:16] D[15:8] D[7:0] 0x000C FFFC
UNUSED D[23:16] D[15:8] D[7:0] 0x000D 0004
:
UNUSED D[23:16] D[15:8] D[7:0] 0x000D 3FFC
:
RESERVED RESERVED RESERVED RESERVED 0x000F FFFC
ADSP-2192October 2000
16-bit PCI DSP Memory Map (BAR3)
The Complete PCI Address Footprint for the ADSP-2192
DSP Memory Spaces in 16-bit (BAR 3) Mode is as follows:
Table 9. 16-bit PCI DSP Memory Map (BAR 3 Mode)
Block Byte3 Byte2 Byte1 Byte0 Offset
DSP P0 Data RAM Block 0 D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 0000
D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 0004
:
D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 7FFC
DSP P0 Data RAM Block 1 D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 8000
D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 8004
:
D[15:8] D[7:0] D[15:8] D[7:0] 0x0000 FFFC
DSP P0 Data RAM Block 2 D[15:8] D[7:0] D[15:8] D[7:0] 0x0001 0000
D[15:8] D[7:0] D[15:8] D[7:0] 0x0001 0004
:
D[15:8] D[7:0] D[15:8] D[7:0] 0x0001 7FFC
E
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
P
R
T
L
E
I
C
M
H
I
N
D
N
A
A
I
T
C
R
A
15REV. PrA
A
Y
L
Loading...