Analog Devices ADSP 2186M Datasheet
DSP
a
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.5 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words Program Memory RAM
8K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
Microcomputer
ADSP-2186M
System Interface
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
PROGRAM
SEQUENCER
SHIFTERMACALU
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAM
MEMORY
8K ⴛ 24 BIT
SERIAL PORTS
SPORT0
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FULL MEMORY MODE
DATA
MEMORY
8K ⴛ 16 BIT
SPORT1
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
ADSP-2186M
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Mapped Registers (New to the
ADSP-2186M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 13
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14
Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14
Internal Memory DMA Port
(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 15
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 16
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 16
Target Board Connector for EZ-ICE Probe . . . . . . . . . . 17
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 17
PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 17
Target System Interface Signals . . . . . . . . . . . . . . . . . . . 17
RECOMMENDED OPERATING CONDITIONS . . . . . 18
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . 19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 19
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . . 19
FREQUENCY DEPENDENCY FOR
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . 20
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . 20
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . . 30
IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . . 31
IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . . 32
IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . . 33
IDMA Read, Short Read Cycle in Short Read
Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . . 35
LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . 37
Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . 38
OUTLINE DIMENSIONS
100-Lead Metric Thin Plastic Quad Flatpack
(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
OUTLINE DIMENSIONS
144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . . 40
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Tables
Table I. Interrupt Priority and Interrupt
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11
Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12
Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13
Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14
–2–
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ADSP-2186M
GENERAL DESCRIPTION
The ADSP-2186M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high-speed numeric
processing applications.
The ADSP-2186M combines the ADSP-2100 family base architecture (three computational units, data address generators, and
a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory.
The ADSP-2186M integrates 40K bytes of on-chip memory
configured as 8K words (24-bit) of program RAM, and 8K
words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable
equipment. The ADSP-2186M is available in a 100-lead LQFP
package and 144 Ball Mini-BGA.
In addition, the ADSP-2186M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (× squared),
biased rounding, result-free ALU operations, I/O memory transfers, and global interrupt masking, for increased flexibility.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2186M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-2186M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, the ADSP-2186M can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-2186M. The System Builder provides a high-level
method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display
different portions of the hardware environment.
The EZ-KIT Lite is a hardware/software kit offering a complete
evaluation environment for the ADSP-218x family: an ADSP2189M-based evaluation board with PC monitor software plus
assembler, linker, simulator, and PROM splitter software. The
ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:
• 75 MHz ADSP-2189M
• Full 16-Bit Stereo Audio I/O with AD73322 Codec
• RS-232 Interface
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
• Evaluation Suite of VisualDSP
®
The ADSP-218x EZ-ICE
debugging of an ADSP-2186M system. The ADSP-2186M
integrates on-chip emulation support with a 14-pin ICE-Port
interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations
than other ADSP-2100 Family EZ-ICEs. The ADSP-2186M
device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
footprint of the EZ-ICE connector, emulation can be supported
in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE-Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional Information
This data sheet provides a general overview of ADSP-2186M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools
data sheet.
Emulator aids in the hardware
EZ-ICE is a registered trademark of Analog Devices, Inc.
REV. 0
–3–
ADSP-2186M
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
PROGRAM
MEMORY
8K
ⴛ
24 BIT
PROGRAM MEMORY ADDRESS
MEMORY
8K ⴛ 16 BIT
DATA
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SHIFTERMACALU
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT0
SPORT1
Figure 1. Functional Block Diagram
ARCHITECTURE OVERVIEW
The ADSP-2186M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single
processor cycle. The ADSP-2186M assembly language uses an
algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2186M. The
processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization, and
derive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine
calls, and returns in a single cycle. With internal loop counters
and loop stacks, the ADSP-2186M executes looped code with
zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
TIMER
BUS
INTERNAL
DMA
PORT
HOST MODE
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting the ADSP-2186M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2186M can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connection, the ADSP-2186M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of
–4–
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ADSP-2186M
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2186M to
continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The ADSP-2186M can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two levelsensitive, and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte DMA
port, and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2186M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2186M incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2186M
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time- division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this configuration.
PIN DESCRIPTIONS
The ADSP-2186M is available in a 100-lead LQFP package
and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some
serial port, programmable flag, interrupt and external bus pins
have dual, multiplexed functionality. The external bus pins are
configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins. In
cases where pin functionality is reconfigurable, the default state is
shown in plain text; alternate functionality is shown in italics.
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–5–
ADSP-2186M
Common-Mode Pins
Pin Name # of Pins I/O Function
RESET 1 I Processor Reset Input
BR 1 I Bus Request Input
BG 1 O Bus Grant Output
BGH 1 O Bus Grant Hung Output
DMS 1 O Data Memory Select Output
PMS 1 O Program Memory Select Output
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output
CMS 1 O Combined Memory Select Output
RD 1 O Memory Read Enable Output
WR 1 O Memory Write Enable Output
IRQ2 1 I Edge- or Level-Sensitive Interrupt Request
PF7 I/O Programmable I/O Pin
IRQL1 1 I Level-Sensitive Interrupt Requests
1
PF6 I/O Programmable I/O Pin
IRQL0 1 I Level-Sensitive Interrupt Requests
1
PF5 I/O Programmable I/O Pin
IRQE 1 I Edge-Sensitive Interrupt Requests
1
PF4 I/O Programmable I/O Pin
Mode D 1 I Mode Select Input—Checked Only During RESET
PF3 I/O Programmable I/O Pin During Normal Operation
Mode C 1 I Mode Select Input—Checked Only During RESET
PF2 I/O Programmable I/O Pin During Normal Operation
Mode B 1 I Mode Select Input—Checked Only During RESET
PF1 I/O Programmable I/O Pin During Normal Operation
Mode A 1 I Mode Select Input—Checked Only During RESET
PF0 I/O Programmable I/O Pin During Normal Operation
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
CLKOUT 1 O Processor Clock Output
SPORT0 5 I/O Serial Port I/O Pins
SPORT1 5 I/O Serial Port I/O Pins
IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts, FI, FO
PWD 1 I Power-Down Control Input
PWDACK 1 O Power-Down Control Output
FL0, FL1, FL2 3 O Output Flags
V
DDINT
V
DDEXT
2 I Internal VDD (2.5 V) Power (LQFP)
4 I External VDD (2.5 V or 3.3 V) Power (LQFP)
GND 10 I Ground (LQFP)
V
DDINT
V
DDEXT
4 I Internal VDD (2.5 V) Power (Mini-BGA)
7 I External VDD (2.5 V or 3.3 V) Power (Mini-BGA)
GND 20 I Ground (Mini-BGA)
EZ-Port 9 I/O For Emulation Use
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
1
2
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ADSP-2186M
Memory Interface Pins
The ADSP-2186M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities.
The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running.
The following tables list the active signals at specific pins of the DSP during either of the two operating modes (Full Memory or
Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinout tables.
Full Memory Mode Pins (Mode C = 0)
Pin Name # of Pins I/O Function
A13:0 14 O Address Output Pins for Program, Data, Byte, and I/O Spaces
D23:0 24 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also
used as Byte Memory Addresses.)
Host Mode Pins (Mode C = 1)
Pin Name # of Pins I/O Function
IAD15:0 16 I/O IDMA Port Address/Data Bus
A0 1 O Address Pin for External I/O, Program, Data, or Byte Access
D23:8 16 I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces
IWR 1 I IDMA Write Enable
IRD
1 I IDMA Read Enable
IAL 1 I IDMA Address Latch Pin
IS 1 I IDMA Select
IACK 1 O IDMA Port Acknowledge Configurable in Mode D; Open Drain
NOTE
1
In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
1
REV. 0
–7–
ADSP-2186M
Terminating Unused Pins
The following table shows the recommendations for terminating unused pins.
Pin Terminations
I/O 3-State Reset Hi-Z*
Pin Name (Z) State Caused By Unused Configuration
XTAL I I Float
CLKOUT O O Float
A13:1 or O (Z) Hi-Z BR, EBR Float
IAD12:0 I/O (Z) Hi-Z IS Float
A0 O (Z) Hi-Z BR, EBR Float
D23:8 I/O (Z) Hi-Z BR, EBR Float
D7 or I/O (Z) Hi-Z BR, EBR Float
IWR I I High (Inactive)
D6 or I/O (Z) Hi-Z BR, EBR Float
IRD IIBR, EBR High (Inactive)
D5 or I/O (Z) Hi-Z Float
IAL I I Low (Inactive)
D4 or I/O (Z) Hi-Z BR, EBR Float
IS I I High (Inactive)
D3 or I/O (Z) Hi-Z BR, EBR Float
IACK Float
D2:0 or I/O (Z) Hi-Z BR, EBR Float
IAD15:13 I/O (Z) Hi-Z IS Float
PMS O (Z) O BR, EBR Float
DMS O (Z) O BR, EBR Float
BMS O (Z) O BR, EBR Float
IOMS O (Z) O BR, EBR Float
CMS O (Z) O BR, EBR Float
RD O (Z) O BR, EBR Float
WR O (Z) O BR, EBR Float
BR I I High (Inactive)
BG O (Z) O EE Float
BGH O O Float
IRQ2/PF7 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float
IRQL1/PF6 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float
IRQL0/PF5 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float
IRQE/PF4 I/O (Z) I Input = High (Inactive) or Program as Output, Set to 1, Let Float
SCLK0 I/O I Input = High or Low, Output = Float
RFS0 I/O I High or Low
DR0 I I High or Low
TFS0 I/O I High or Low
DT0 O O Float
SCLK1 I/O I Input = High or Low, Output = Float
RFS1/IRQ0 I/O I High or Low
DR1/FI I I High or Low
TFS1/IRQ1 I/O I High or Low
DT1/FO O O Float
EE I I Float
EBR I I Float
EBG O O Float
ERESET I I Float
EMS O O Float
EINT I I Float
ECLK I I Float
ELIN I I Float
ELOUT O O Float
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.
2. If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as inter-
rupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1, prior to enabling interrupts, and let pins float.
3. All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0/MODE D:A are not included in the table because these pins must be used.
–8–
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ADSP-2186M
Interrupts
The interrupt controller allows the processor to respond to the
11 possible interrupts and reset with minimum overhead. The
ADSP-2186M provides four dedicated external interrupt input
pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7:4
pins). In addition, SPORT1 may be reconfigured for IRQ0,
IRQ1, FI and FO, for a total of six external interrupts. The
ADSP-2186M also supports internal interrupts from the timer,
the byte DMA port, the two serial ports, software, and the powerdown control circuit. The interrupt levels are internally prioritized
and individually maskable (except power- down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge-sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Source Of Interrupt Address (Hex)
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable) 002C
IRQ2 0004
IRQL1 0008
IRQL0 000C
SPORT0 Transmit 0010
SPORT0 Receive 0014
IRQE 0018
BDMA Interrupt 001C
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
Timer 0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
power-down interrupt is nonmaskable.
The ADSP-2186M masks all interrupts for one instruction
cycle following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts
to be either edge- or level-sensitive. The IRQE pin is an external edge sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop, and subroutine
nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power down), regardless
of the state of IMASK. Disabling the interrupts does not affect
serial port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2186M has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
•Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2186M processor has a low power feature that lets
the processor enter a very low-power dormant state through
hardware or software control. Following is a brief list of powerdown features. Refer to the ADSP-2100 Family User’s Manual,
“System Interface” chapter, for detailed information about the
power-down feature.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during powerdown without affecting the lowest power rating and 200 CLKIN
cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approximately
4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle
start-up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit. Interrupt support allows
an unlimited number of instructions to be executed before
optionally powering down. The power-down interrupt also
can be used as a nonmaskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
When the ADSP-2186M is in the Idle Mode, the processor
waits indefinitely in a low-power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA and autobuffer cycle steals
still occur.
REV. 0
–9–
ADSP-2186M
Slow Idle
The IDLE instruction is enhanced on the ADSP-2186M to let
the processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable
divisor given in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals, such
as SCLK, CLKOUT, and timer clock, are reduced by the same
ratio. The default form of the instruction, when no clock divisor
is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle
state is increased by n, the clock divisor. When an enabled interrupt is received, the ADSP-2186M will remain in the idle state
for up to a maximum of n processor cycles (n = 16, 32, 64, or
128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2186M, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (modeselectable). Programmable wait state generation allows the
processor to connect easily to slow peripheral devices. The
FULL MEMORY MODE
ADSP-2186M
ADSP-2186M
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
CLKIN
XTAL
FL0–2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR F
I
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
ADDR13–0
DATA23–0
BMS
WR
RD
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
14
A
13–0
D
A0–A21
23–16
24
D
15–8
DATA
CS
A
10–0
ADDR
D
23–8
A
13–0
D
23–0
(PERIPHERALS)
DATA
CS
ADDR
DATA
PM SEGMENTS
DM SEGMENTS
2048 LOCATIONS
OVERLAY
MEMORY
Figure 2. Basic System Interface
–10–
ADSP-2186M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Through the use
of external hardware, additional system peripherals can be added
in this mode to generate and latch address signals.
Clock Signals
The ADSP-2186M can be clocked by either a crystal or a
TTL-compatible clock signal.
The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal
operation. The only exception is while the processor is in the
power-down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, for detailed information
on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal
running at half the instruction rate. The signal is connected to
the processor’s CLKIN input. When an external clock is used,
the XTAL input must be left unconnected.
The ADSP-2186M uses an input clock with a frequency equal to
half the instruction rate; a 37.50 MHz input clock yields a 13 ns
processor cycle (which is equivalent to 75 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2186M includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on
crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled by
the CLKODIS bit in the SPORT0 Autobuffer Control Register.
HOST MEMORY MODE
ADSP-2186M
16
CLKIN
XTAL
FL0–2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
DATA23–8
BMS
WR
RD
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
1
A0
16
BYTE
MEMORY
I/O SPACE
TWO 8K
TWO 8K
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
CONTROLLER
REV. 0
CLKIN XTAL CLKOUT
DSP
Figure 3. External Crystal Connections
RESET
The RESET signal initiates a master reset of the ADSP-2186M.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for the
crystal oscillator circuit to stabilize after a valid V
is applied to
DD
the processor, and for the internal phase-locked loop (PLL) to lock
onto the specific crystal frequency. A minimum of 2000 CLKIN
cycles ensures that the PLL has locked but does not include the
crystal oscillator start-up time. During this power-up sequence
the RESET signal should be held low. On any subsequent resets,
the RESET signal must meet the minimum pulsewidth specification, t
RSP
.
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and clears the MSTAT register.
When RESET is released, if there is no pending bus request and
the chip is configured for booting, the boot-loading sequence is
ADSP-2186M
performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
Power Supplies
The ADSP-2186M has separate power supply connections for
the internal (V
) and external (V
DDINT
The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V supply.
All external supply pins must be connected to the same supply.
All input and I/O pins can tolerate input voltages up to 3.6 V,
regardless of the external supply voltage. This feature provides
maximum flexibility in mixing 2.5 V and 3.3 V components.
MODES OF OPERATION
Setting Memory Mode
Memory Mode selection for the ADSP-2186M is made during
chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive Configuration
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP
application, a weak pull-up or pull-down, on the order of 10 kΩ,
can be used. This value should be sufficient to pull the pin to the
desired level and still allow the pin to operate as a programmable
flag output without undue strain on the processor’s output driver.
For minimum power consumption during power-down, reconfigure PF2 to be an input, as the pull-up or pull-down will
hold the pin in a known state, and will not switch.
) power supplies.
DDEXT
Table II. Modes of Operation
MODE D MODE C MODE B MODE A Booting Method
X 0 0 0 BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Full Memory Mode.
1
X010No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used, but the processor does not automatically use or wait for these
operations.
0100BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Host Mode. IACK has active
pull-down. (REQUIRES ADDITIONAL HARDWARE).
0101IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written
to. Chip is configured in Host Mode. IACK has active pull-down.
1
1100BDMA feature is used to load the first 32 program memory words from
the byte memory space. Program execution is held off until all 32 words
have been loaded. Chip is configured in Host Mode; IACK requires external pull down. (REQUIRES ADDITIONAL HARDWARE)
1101IDMA feature is used to load any internal memory as desired. Program
execution is held off until internal program memory location 0 is written
to. Chip is configured in Host Mode. IACK requires external pull-down.
NOTE
1
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
1
REV. 0
–11–
ADSP-2186M
Active Configuration
Active Configuration involves the use of a three-statable external
driver connected to the Mode C pin. A driver’s output enable
should be connected to the DSP’s RESET signal such that it
only drives the PF2 pin when RESET is active (low). When
RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level, and will not oscillate should the three-state driver’s level
hover around the logic switching point.
IACK Configuration
Mode D = 0 and in host mode: IACK is an active, driven signal
and cannot be “wire OR’d.”
Mode D = 1 and in host mode: IACK is an open drain and
requires an external pull-down, but multiple IACK pins can be
“wire OR’d” together.
PM (MODE B = 0)
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
PMOVLAY = 0
RESERVED
ACCESSIBLE WHEN
PMOVLAY = 1
EXTERNAL
MEMORY
0x2000 –
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 2
0x2000 –
0
x
3FFF
2
0x2000 –
0
x
3FFF
PM (MODE B = 1)
2
MEMORY ARCHITECTURE
The ADSP-2186M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2186M.
Program Memory
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The ADSP2186M has 8K words of Program Memory RAM on chip, and
the capability of accessing up to two 8K external memory overlay spaces using the external data bus.
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16 bits wide only.
1
RESERVED
RESERVED
ACCESSIBLE WHEN
PMOVLAY = 0
EXTERNAL
MEMORY
NOTES:
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
2
SEE TABLE III FOR PMOVLAY BITS
0x2000 –
0x3FFF
RESERVED
0
x
0
x
0000 –
1FFF
0x0000 –
0
2
x
1FFF
2
PROGRAM MEMORY
MODE B = 0
8K EXTERNAL
PMOVLAY = 1, 2
8K
INTERNAL
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
PROGRAM MEMORY
MODE B = 1
RESERVED
8K EXTERNAL
PMOVLAY = 0
ADDRESS
0x3FFF
0x2000
0x1FFF
0x0000
Figure 4. Program Memory
Table III. PMOVLAY Bits
PMOVLAY Memory A13 A12:0
0 Reserved Not Applicable Not Applicable
1 External Overlay 1 0 13 LSBs of Address Between 0x2000 and 0x3FFF
2 External Overlay 2 1 13 LSBs of Address Between 0x2000 and 0x3FFF
–12–
REV. 0
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