ANALOG DEVICES ADSP-21477, ADSP-21478, ADSP-21479 Service Manual

SHARC Processor

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 Stage

Sequencer

PEx PEy

PMD

64-BIT

IOD0 32-BIT

EPD BUS 64-BIT

Core Bus

Cross Bar

S/PDIF Tx/Rx

PCG A

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI

SDRAM

CTL

External Port Pin MUX

TIMER

SPORT

ASRC

3-0

PWM

DAG1/2

Core

Timer

PDAP/

IDP 7

TWI

IOD0 BUS

DTCP/

MTM

PCG C

PERIPHERAL BUS 32-BIT

CORE

FLAGS/

PWM3

JTAG

Internal Memory

DMD

64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1 32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals

DAI Peripherals

Peripherals

External Port

SIMD Core

THERMAL

DIODE

FFT FIR

IIR

MLB

SPEP BUS

DMD

64-BIT

FLAGx/IRQx/ TMREXP

WDT

RTC

SHIFT

REG

DAI Routing/Pins

ADSP-21477/ADSP-21478/ADSP-21479

SUMMARY

High performance 32-bit/40-bit floating-point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—up to 5M bits of on-chip RAM, 4M bits of

on-chip ROM Up to 300 MHz operating frequency Qualified for automotive applications. See Automotive Prod-

ucts on Page 74

Code compatible with all other members of the SHARC family

The ADSP-2147x processors are available with unique

audio-centric peripherals, such as the digital applications interface, serial ports, precision clock generators, S/PDIF transceiver, asynchronous sample rate converters, input data port, and more.

Factory programmed ROM versions containing latest audio

decoders from Dolby and DTS, available to IP licenses

For complete ordering information, see Ordering Guide on

Page 75.

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

Figure 1. Functional Block Diagram

ADSP-21477/ADSP-21478/ADSP-21479

Summary ............................................................... 1

Product Application Restriction .................................. 2

General Description ................................................. 3

Family Core Architecture ........................................ 4

Family Peripheral Architecture ................................ 8

I/O Processor Features ......................................... 12

System Design .................................................... 13

Development Tools ............................................. 13

Additional Information ........................................ 14

Related Signal Chains .......................................... 14

Pin Function Descriptions ....................................... 15

Specifications ........................................................ 20

Operating Conditions .......................................... 20

Electrical Characteristics ....................................... 21

Maximum Power Dissipation ................................ 23

Package Information ........................................... 23

REVISION HISTORY

3/12—Rev. A to Rev. B

Revised Real Time Clock, SR_LDO and EMU

in Pin Function Descriptions .................................... 15

, t

Corrected t

Sequencing Timing Requirements (Processor Startup) ... . 26

Revised note in Figure 8, 266 MHz Operation (Fundamental

Mode Crystal) ....................................................... 28

Added additional models to:

Automotive Products .............................................. 74

Ordering Guide ..................................................... 75

Added the 88-lead LFCSP_VQ package and the ADSP-21477 model. General information, specifications, and ordering information for this package and model can be found in the following sections:

ADSP-2147x Family Features ...................................... 3

ADSP-21477 Internal Memory Space, 2M bits . . .............. 6

Operating Conditions ............................................. 20

Core Timer .......................................................... 30

Timer PWM_OUT Cycle Timing .............................. 30

Precision Clock Generator (Direct Pin Routing) ............ 33

Serial Ports ........................................................... 40

Input Data Port (IDP) ............................................. 46

Parallel Data Acquisition Port (PDAP) ........................ 47

Sample Rate Converter—Serial Output Port ................. 49

Pulse-Width Modulation Generators (PWM) ............... 50

PLLRST

timing in Table 19, Power-Up

CLKRST

Pin Descriptions

ESD Sensitivity ................................................... 23

Absolute Maximum Ratings ................................... 23

Timing Specifications ........................................... 24

Output Drive Currents ......................................... 64

Test Conditions .................................................. 64

Capacitive Loading .............................................. 64

Thermal Characteristics ........................................ 65

88-LFCSP_VQ Lead Assignment ................................ 67

100-LQFP_EP Lead Assignment ................................ 69

196-BGA Ball Assignment ........................................ 71

Outline Dimensions ................................................ 72

Surface-Mount Design .......................................... 74

Automotive Products .............................................. 74

Ordering Guide ..................................................... 75

S/PDIF Transmitter Input Data Timing ....................... 53

SPI Interface—Master ............................................. 55

SPI Interface—Slave ................................................ 56

JTAG Test Access Port and Emulation ......................... 63

Thermal Characteristics for 88-Lead LFCSP_VQ ........... 65

88-LFCSP_VQ Lead Assignment ................................ 67

88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

(CP-88-5) Dimensions Shown in Millimeters ................ 72

Automotive Products .............................................. 74

Ordering Guide ..................................................... 75

PRODUCT APPLICATION RESTRICTION

Not for use in in-vivo applications for body fluid constituent monitoring, including monitoring one or more of the components that form, or may be a part of, or contaminate human blood or other body fluids, such as, but not limited to, carboxyhemoglobin, methemoglobin total hemoglobin, oxygen saturation, oxygen content, fractional arterial oxygen saturation, bilirubin, glucose, drugs, lipids, water, protein, and pH.

Rev. B | Page 2 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

GENERAL DESCRIPTION

The ADSP-2147x SHARC SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (singleinstruction, single-data) mode. These processors are 32-bit/ 40-bit floating-point processors optimized for high performance audio applications with a large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative digital applications interface (DAI).

Table 1 shows performance benchmarks for the ADSP-2147x

processors. Table 2 shows the features of the individual product offerings.

Table 1. Processor Benchmarks

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with Reversal)

FIR Filter (per Tap) IIR Filter (per Biquad) Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1] [4 × 4] × [4 × 1]

Divide (y/×) 11.61 ns 17.41 ns Inverse Square Root 18.08 ns 27.12 ns

Assumes two files in multichannel SIMD mode.

Table 2. ADSP-2147x Family Features

processors are members of the

Speed (at 300 MHz)

Speed (at 200 MHz)

30.59 s 45.885 s

1.66 ns 2.49 ns

6.65 ns 9.975 ns

14.99 ns

26.66 ns

22.485 ns

39.99 ns

Table 2. ADSP-2147x Family Features (Continued)

Feature

Watch Dog Timer

Real-Time Clock2,

Shift Register

ADSP-21477

ADSP-21478

No Yes

IDP/PDAP Yes

UART 1

DAI (SRU)/DPI (SRU2) 20/14 Pins

S/PDIF Transceiver 1

SPI 2

TWI 1

SRC SNR Performance –128 dB

Thermal Diode

Ye s

VISA Support Yes

100-Lead LQFP

Package

The 100-lead and 88-lead packages of the processors do not contain an external

Available on the 196-ball CSP_BGA package only.

Real Time Clock (RTC) is supported only for products with a temperature range

Available on the 88-lead and 100-lead packages only.

port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function Descriptions on Page 16.

of 0°C to +70°C and not supported for all other temperature grades.

88-Lead LFCSP_VQ

196-Ball CSP_BGA

100-Lead LQFP

88-lead LFCSP_VQ

ADSP-21479

Feature

ADSP-21477

ADSP-21478

Frequency 200 MHz Up to 300 MHz

RAM 2M bits 3M bits 5M bits

ROM N/A 4M bits

4 units (3 in 100-lead

Pulse-Width Modulation 3

External Port Interface (SDRAM, AMI)

No Yes, 16-Bit

package)

Serial Ports 8

Direct DMA from SPORTs to External Memory No Yes

FIR, IIR, FFT Accelerator Yes

Automotive models

MediaLB Interface No

only

Rev. B | Page 3 of 76 | March 2012

The diagram on Page 1 shows the two clock domains (core and

ADSP-21479

I/O processor) that make up the ADSP-2147x processors. The core clock domain contains the following features.

• Two processing elements (PEx, PEy), each of which comprises an ALU, multiplier, shifter, and data register file

• Two data address generators (DAG1, DAG2)

• A program sequencer with instruction cache

• PM and DM buses capable of supporting 2 × 64-bit data transfers between memory and the core at every core processor cycle

• One periodic interval timer with pinout

• On-chip SRAM (up to 5M bit)

• A JTAG test access port for emulation and boundary scan. The JTAG provides software debug through user breakpoints, which allows flexible exception handling.

ADSP-21477/ADSP-21478/ADSP-21479

The block diagram of the ADSP-2147x on Page 1 also shows the peripheral clock domain (also known as the I/O processor), which contains the following features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers

• Peripheral and external port buses for core connection

• External port with an asynchronous memory interface (AMI) and SDRAM controller

•4 units for pulse width modulation (PWM) control

• 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers

• Digital applications interface that includes four precision clock generators (PCG), an input data port (IDP/PDAP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a shift register, and a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, a 2wire interface, one UART, two serial peripheral interfaces (SPI), two precision clock generators (PCG), three pulse width modulation (PWM) units, and a flexible signal routing unit (DPI SRU).

As shown in the SHARC core block diagram on Page 5, the processors use two computational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms. With its SIMD computational hardware, the processors can perform 1.8 GFLOPS running at 300 MHz.

FAMILY CORE ARCHITECTURE

The processors are code compatible at the assembly level with the ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-2147x share architectural features with the ADSP-2126x, ADSP-2136x, ADSP2137x, ADSP-2146x, and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections.

SIMD Computational Engine

The processors contain two computational processing elements that operate as a single-instruction, multiple-data (SIMD) engine. The processing elements are referred to as PEX and PEY and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. SIMD mode allows the processor to execute the same instruction in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms.

SIMD mode also affects the way data is transferred between memory and the processing elements because twice the data bandwidth is required to sustain computational operation in the processing elements. Therefore, entering SIMD mode also doubles the bandwidth between memory and the processing

elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each memory or register file access.

SIMD mode is supported from external SDRAM but is not supported in the AMI.

Independent, Parallel Computation Units

Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform all operations in a single cycle. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, and 32-bit fixed-point data formats.

Timer

The processor contains a core timer that can generate periodic software interrupts. The core timer can be configured to use FLAG3 as a timer expired signal.

Data Register File

Each processing element contains a general-purpose data register file. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the processor’s enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that can be activated during interrupt servicing for a fast context switch. The data registers in the register file, the DAG registers, and the multiplier result registers all have secondary registers. The primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register.

Universal Registers

Universal registers can be used for general-purpose tasks. The USTAT (4) registers allow easy bit manipulations (Set, Clear, Toggle, Test, XOR) for all peripheral control and status registers.

The data bus exchange register (PX) permits data to be passed between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data bus. These registers contain hardware to handle the data width difference.

Single-Cycle Fetch of Instruction and Four Operands

The processors feature an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 2). With its separate program and data memory

Rev. B | Page 4 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1 16×32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

Rx/Fx

PEx

16×40-BIT

JTAG

DMD/PMD 64

ASTATx

STYKx

ASTATy

STYKy

TIMER

Sx/SFx

PEy

16×40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

US TAT

4×32-BIT

64-BIT

DAG2 16×32

ALU

MULTIPLIER

SHIFTER

DATA SWAP

PM ADDRESS 24

PM DATA 48

buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processor includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective—only the instructions whose fetches conflict with PM bus data accesses are cached. This cache allows full speed execution of core looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The processor’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16

Figure 2. SHARC Core Block Diagram

Rev. B | Page 5 of 76 | March 2012

primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the processors can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction.

Variable Instruction Set Architecture (VISA)

In addition to supporting the standard 48-bit instructions from previous SHARC processors, the processors support new instructions of 16 and 32 bits. This feature, called Variable Instruction Set Architecture (VISA), drops redundant/unused

ADSP-21477/ADSP-21478/ADSP-21479

bits within the 48-bit instruction to create more efficient and compact code. The program sequencer supports fetching these 16-bit and 32-bit instructions from both internal and external SDRAM memory. This support is not extended to the asynchronous memory interface (AMI). Source modules need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes.

On-Chip Memory

The processors contain varying amounts of internal RAM and internal ROM which is shown in Table 3 through Table 5. Each block can be configured for different combinations of code and data storage. Each memory block supports single-cycle, independent accesses by the core processor and I/O processor.

The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5M bits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit

Table 3. ADSP-21477 Internal Memory Space, 2M bits

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 8FFF

Block 0 SRAM 0x0004 9000–0x0004 BFFF

Reserved 0x0004 C000–0x0004 FFFF

Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF Reserved 0x0005 8000–0x0005 8FFF

Block 1 SRAM 0x0005 9000–0x0005 BFFF

Reserved 0x0005 C000–0x0005 FFFF Block 2 SRAM 0x0006 0000–0x0006 0FFF

Reserved 0x0006 1000– 0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 0FFF Reserved 0x0007 1000–0x0007 FFFF

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 BFFF Block 0 SRAM 0x0008 C000–0x0008 FFFF

Reserved 0x0009 000–0x0009 5554

Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9 Reserved 0x000A AAAA–0x000A BFFF

Block 1 SRAM 0x000A C000–0x000A FFFF

Reserved 0x000B 0000–0x000B 5554 Block 2 SRAM 0x000C 0000–0x000C 1554

Reserved 0x000C 1555–0x000D 5554

Block 3 SRAM 0x000E 0000–0x000E 1554 Reserved 0x000E 1555–0x000F 5554

floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.

The memory maps in Table 3 through Table 5 display the internal memory address space of the processors. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory.

Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 1FFF Block 0 SRAM 0x0009 2000–0x0009 7FFF

Reserved 0x0009 8000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000AFFFF Reserved 0x000B 0000–0x000B 1FFF

Block 1 SRAM 0x000B 2000–0x000B 7FFF

Reserved 0x000B 8000–0x000B FFFF Block 2 SRAM 0x000C 0000–0x000C 1FFF

Reserved 0x000C 2000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 1FFF Reserved 0x000E 2000–0x000F FFFF

Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 FFFF Block 0 SRAM 0x0012 4000–0x0012 FFFF

Reserved 0x0013 0000–0x0013 FFFF

Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF Reserved 0x0016 0000–0x0016 3FFF

Block 1 SRAM 0x0016 4000–0x0016 FFFF

Reserved 0x0017 0000–0x0017 FFFF Block 2 SRAM 0x0018 0000–0x0018 3FFF

Reserved 0x0018 4000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C 3FFF Reserved 0x001C 4000–0x001F FFFF

Rev. B | Page 6 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Table 4. ADSP-21478 Internal Memory Space (3M bits)

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 8FFF

Block 0 SRAM 0x0004 9000–0x0004 CFFF

Reserved 0x0004 D000–0x0004 FFFF

Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 8FFF

Block 1 SRAM 0x0005 9000–0x0005 CFFF

Reserved 0x0005 D000–0x0005 FFFF

Block 2 SRAM 0x0006 0000–0x0006 1FFF

Reserved 0x0006 2000– 0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 1FFF

Reserved 0x0007 2000–0x0007 FFFF

Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 BFFF

Block 0 SRAM 0x0008 C000–0x0009 1554

Reserved 0x0009 1555–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9

Reserved 0x000A AAAA–0x000A BFFF

Block 1 SRAM 0x000A C000–0x000B 1554

Reserved 0x000B 1555–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 2AA9

Reserved 0x000C 2AAA–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 2AA9

Reserved 0x000E 2AAA–0x000F FFFF

Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 1FFF

Block 0 SRAM 0x0009 2000–0x0009 9FFF

Reserved 0x0009 A000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A FFFF

Reserved 0x000B 0000–0x000B 1FFF

Block 1 SRAM 0x000B 2000–0x000B 9FFF

Reserved 0x000B A000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 3FFF

Reserved 0x000C 4000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 3FFF

Reserved 0x000E 4000–0x000F FFFF

Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 3FFF

Block 0 SRAM 0x0012 4000–0x0013 3FFF

Reserved 0x0013 4000–0x0013 FFFF

Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 3FFF

Block 1 SRAM 0x0016 4000–0x0017 3FFF

Reserved 0x0017 4000–0x0017 FFFF

Block 2 SRAM 0x0018 0000–0x0018 7FFF

Reserved 0x0018 8000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C 7FFF

Reserved 0x001C 8000–0x001F FFFF

Rev. B | Page 7 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Table 5. ADSP-21479 Internal Memory Space (5M bits)

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Block 0 ROM (Reserved) 0x0004 0000–0x0004 7FFF

Reserved 0x0004 8000–0x0004 8FFF

Block 0 SRAM 0x0004 9000–0x0004 EFFF

Reserved 0x0004 F000–0x0004 FFFF

Block 1 ROM (Reserved) 0x0005 0000–0x0005 7FFF

Reserved 0x0005 8000–0x0005 8FFF

Block 1 SRAM 0x0005 9000–0x0005 EFFF

Reserved 0x0005 F000–0x0005 FFFF

Block 2 SRAM 0x0006 0000–0x0006 3FFF

Reserved 0x0006 4000– 0x0006 FFFF

Block 3 SRAM 0x0007 0000–0x0007 3FFF

Reserved 0x0007 4000–0x0007 FFFF

Some processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog Devices sales

representative for additional details.

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Block 0 ROM (Reserved) 0x0008 0000–0x0008 AAA9

Reserved 0x0008 AAAA–0x0008 BFFF

Block 0 SRAM 0x0008 C000–0x0009 3FFF

Reserved 0x0009 4000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000A AAA9

Reserved 0x000A AAAA–0x000A BFFF

Block 1 SRAM 0x000A C000–0x000B 3FFF

Reserved 0x000B 4000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 5554

Reserved 0x000C 5555–0x0000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 5554

Reserved 0x000E 5555–0x0000F FFFF

Block 0 ROM (Reserved) 0x0008 0000–0x0008 FFFF

Reserved 0x0009 0000–0x0009 1FFF

Block 0 SRAM 0x0009 2000–0x0009 DFFF

Reserved 0x0009 E000–0x0009 FFFF

Block 1 ROM (Reserved) 0x000A 0000–0x000AFFFF

Reserved 0x000B 0000–0x000B 1FFF

Block 1 SRAM 0x000B 2000–0x000B DFFF

Reserved 0x000B E000–0x000B FFFF

Block 2 SRAM 0x000C 0000–0x000C 7FFF

Reserved 0x000C 8000–0x000D FFFF

Block 3 SRAM 0x000E 0000–0x000E 7FFF

Reserved 0x000E 8000–0x000F FFFF

Block 0 ROM (Reserved) 0x0010 0000–0x0011 FFFF

Reserved 0x0012 0000–0x0012 3FFF

Block 0 SRAM 0x0012 4000–0x0013 BFFF

Reserved 0x0013 C000–0x0013 FFFF

Block 1 ROM (Reserved) 0x0014 0000–0x0015 FFFF

Reserved 0x0016 0000–0x0016 3FFF

Block 1 SRAM 0x0016 4000–0x0017 BFFF

Reserved 0x0017 C000–0x0017 FFFF

Block 2 SRAM 0x0018 0000–0x0018 FFFF

Reserved 0x0019 0000–0x001B FFFF

Block 3 SRAM 0x001C 0000–0x001C FFFF

Reserved 0x001D 0000–0x001F FFFF

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). The total bandwidth is realized using the DMD and PMD buses (2 × 64-bit at CCLK speed) and the IOD0/1 buses (2 × 32-bit at PCLK speed).

ROM Based Security

The processors have a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code. When using this feature, the processors do not boot-load any external code, executing exclusively from internal ROM. Additionally, the processor is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port, is assigned to each customer. The device ignores an incorrect key. Emulation features are available after the correct key is scanned.

Rev. B | Page 8 of 76 | March 2012

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting, and tampering as it traverses high performance digital buses, such as the IEEE 1394 standard. Only legitimate entertainment content delivered to a source device via another approved copy protection system (such as the DVD content scrambling system) is protected by this copy protection system. For more information on this feature, contact your local ADI sales office.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-2147x family contains a rich set of peripherals that support a wide variety of applications including high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recognition, motor control, imaging, and other applications.

ADSP-21477/ADSP-21478/ADSP-21479

External Memory

The external memory interface supports access to the external memory through core and DMA accesses. The external memory address space is divided into four banks. Any bank can be programmed as either asynchronous or synchronous memory. The external ports are comprised of the following modules.

• An AMI which communicates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 6M words of external memory in Bank 0 and 8M words of external memory in Bank 1, Bank 2, and Bank 3.

• An SDRAM controller that supports a glueless interface with any of the standard SDRAMs. The SDC supports 62M words of external memory in Bank 0, and 64M words of external memory in Bank 1, Bank 2, and Bank 3.

• Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port.

External Port

The external port provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port, available on the 196-ball CSP_BGA, may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-standard synchronous DRAM devices while the second is an asynchronous memory controller intended to interface to a variety of memory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. Non-SDRAM external memory address space is shown in Table 6.

Table 6. External Memory for Non-SDRAM Addresses

Size in

Bank

Bank 0 6M 0x0020 0000–0x007F FFFF Bank 1 8M 0x0400 0000–0x047F FFFF Bank 2 8M 0x0800 0000–0x087F FFFF Bank 3 8M 0x0C00 0000–0x0C7F FFFF

SIMD Access to External Memory

The SDRAM controller supports SIMD access on the 64-bit external port data bus (EPD) which allows access to the complementary registers on the PEy unit in the normal word space (NW). This improves performance since there is no need to explicitly load the complementary registers (as in SISD mode).

VISA and ISA Access to External Memory

The SDRAM controller supports VISA code operation which reduces the memory load since the VISA instructions are compressed. Moreover, bus fetching is reduced because, in the best case, one 48-bit fetch contains three valid instructions. Code execution from the traditional ISA operation is also supported.

Words Address Range

Note that code execution is only supported from Bank 0 regardless of VISA/ISA. Table 7 shows the address ranges for instruction fetch in each mode.

Table 7. External Bank 0 Instruction Fetch

Size in

Access Type

ISA (NW) 4M 0x0020 0000–0x005F FFFF

VISA (SW) 10M 0x0060 0000–0x00FF FFFF

Words Address Range

SDRAM Controller

The SDRAM controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides an interface of up to four separate banks of industry-standard SDRAM devices or DIMMs, at speeds up to f SDRAM standard, each bank has its own memory select line

–MS3), and can be configured to contain between

(MS0 4 Mbytes and 256 Mbytes of memory. SDRAM external memory address space is shown in Table 8.

Table 8. External Memory for SDRAM Addresses

Size in

Bank

Bank 0 62M 0x0020 0000–0x03FF FFFF

Bank 1 64M 0x0400 0000–0x07FF FFFF

Bank 2 64M 0x0800 0000–0x0BFF FFFF

Bank 3 64M 0x0C00 0000–0x0FFF FFFF

A set of programmable timing parameters is available to configure the SDRAM banks to support slower memory devices. The SDRAM and the AMI interface do not support 32-bit wide devices.

The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF.

Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap.

Words Address Range

. Fully compliant with the

SDCLK

Asynchronous Memory Controller

The asynchronous memory controller, available on the ADSP-2147x in the 196-ball CSP_BGA package, provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with different timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 6M word window and Banks 1, 2, and 3

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ADSP-21477/ADSP-21478/ADSP-21479

occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic.

External Port Throughput

The throughput for the external port, based on 133 MHz clock and 16-bit data bus, is 88 Mbytes/sec for the AMI and 266 Mbytes/sec for SDRAM.

MediaLB

The automotive models of the processors have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin and 5-pin MLB protocols. It supports speeds up to 1024 FS (49.25M bits/sec, FS = 48.1 kHz) and up to 31 logical channels, with up to 124 bytes of data per media local bus frame. For a list of automotive products, see Automotive Products on Page 74.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to connect various peripherals to any of the DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit (SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the DAI to be interconnected under software control. This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with non configurable signal paths.

The associated peripherals include eight serial ports, four precision clock generators (PCG), a S/PDIF transceiver, four ASRCs, and an input data port (IDP). The IDP provides an additional input path to the SHARC core, configurable as either eight channels of serial data, or a single 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the processor’s serial ports.

Serial Ports (SPORTs)

The processors feature eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as Analog Devices’ AD183x family of audio codecs, ADCs, and DACs. The serial ports are made up of two data lines, a clock, and frame sync. The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel.

Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTs are enabled, or four full duplex TDM streams of 128 channels per frame.

Serial port data can be automatically transferred to and from on-chip memory/external memory via dedicated DMA channels. Each of the serial ports can work in conjunction with another serial port to provide TDM support. One SPORT provides two transmit signals while the other SPORT provides the two receive signals. The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard serial mode

•Multichannel (TDM) mode

•I

S mode

•Packed I

• Left-justified mode

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The S/PDIF receiver/transmitter has no separate DMA channels. It receives audio data in serial format and converts it into a bi phase encoded signal. The serial data input to the receiver/transmitter can be formatted as left justified, I right-justified with word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF receiver/transmitter are routed through the signal routing unit (SRU). They can come from a variety of sources, such as the SPORTs, external pins, the precision clock generators (PCGs), and are controlled by the SRU control registers.

Asynchronous Sample Rate Converter (SRC)

The sample rate converter contains four blocks and is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter. The SRC block provides up to 128 dB SNR and is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. The four SRC blocks can also be configured to operate together to convert multichannel audio data without phase mismatches. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver.

Input Data Port

The IDP provides up to eight serial input channels—each with its own clock, frame sync, and data inputs. The eight channels are automatically multiplexed into a single 32-bit by eight-deep FIFO. Data is always formatted as a 64-bit frame and divided into two 32-bit words. The serial protocol is designed to receive audio channels in I mode.

The IDP also provides a parallel data acquisition port (PDAP) which can be used for receiving parallel data. The PDAP port has a clock input and a hold input. The data for the PDAP can be received from DAI pins or from the external port pins. The PDAP supports a maximum of 20-bit data and four different packing modes to receive the incoming data.

Precision Clock Generators

The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D are identical in functionality and operate independently of each other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair.

The outputs of PCG A and B can be routed through the DAI pins and the outputs of PCG C and D can be driven on to the DAI as well as the DPI pins.

S mode

S, left-justified sample pair, or right-justified

S or

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Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), one universal asynchronous receiver-transmitter (UART), 12 flags, a 2-wire interface (TWI), three PWM modules (PWM3–1), and two generalpurpose timers.

Serial Peripheral (Compatible) Interface (SPI)

The SPI is an industry-standard synchronous serial link, enabling the SPI-compatible port to communicate with other SPI compatible devices. The SPI consists of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multi-master environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The SPI-compatible peripheral implementation also features programmable baud rate and clock phase and polarities. The SPI-compatible port uses open drain drivers to support a multi-master configuration and to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. The UART also has multiprocessor communication capability using 9-bit address detection. This allows it to be used in multidrop networks through the RS-485 data interface standard. The UART port also includes support for 5 to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The UART port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives data by writing or reading I/O-mapped UART registers. The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller transfers both transmit and receive data. This reduces the number and frequency of interrupts required to transfer data to and from memory. The UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower default priority than most DMA channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:

• Support for bit rates ranging from (f (f

/16) bits per second.

PCLK

• Support for data formats from 7 to 12 bits per frame.

• Both transmit and receive operations can be configured to generate maskable interrupts to the processor.

In conjunction with the general-purpose timer functions, autobaud detection is supported.

/1,048,576) to

PCLK

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform generator that can be programmed to generate the required switching patterns for various applications related to motor and engine control or audio power control. The PWM generator can generate either center-aligned or edge-aligned PWM waveforms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in nonpaired mode (applicable to a single group of four PWM waveforms).

The entire PWM module has four groups of four PWM outputs generating 16 PWM outputs in total. Each PWM group produces two pairs of PWM signals on the four PWM outputs.

The PWM generator is capable of operating in two distinct modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode the duty cycle values are programmable only once per PWM period. This results in PWM patterns that are symmetrical about the midpoint of the PWM period. In double update mode, a second updating of the PWM registers is implemented at the midpoint of the PWM period. In this mode, it is possible to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters.

PWM signals can be mapped to the external port address lines or to the DPI pins.

Ti me rs

The processors have a total of three timers: a core timer that can generate periodic software interrupts and two general-purpose timers that can generate periodic interrupts and be independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watch dog mode

The core timer can be configured to use FLAG3 as a timer expired signal, and the general-purpose timers have one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A single control and status register enables or disables the generalpurpose timer.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the I The TWI master incorporates the following features:

• 7-bit addressing

• Simultaneous master and slave operation on multiple device systems with support for multi-master data arbitration

• Digital filtering and timed event processing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

C bus protocol.

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ADSP-21477/ADSP-21478/ADSP-21479

Shift Register

The shift register can be used as a serial to parallel data converter. The shift register module consists of an 18-stage serial shift register, 18-bit latch, and three-state output buffers. The shift register and latch have separate clocks. Data is shifted into the serial shift register on the positive-going transitions of the shift register serial clock (SR_SCLK) input. The data in each flip-flop is transferred to the respective latch on a positive-going transition of the shift register latch clock (SR_LAT) input.

The shift register’s signals can be configured as follows.

• The SR_SCLK can come from any of the SPORT0–7 SCLK outputs, PCGA/B clock, any of the DAI pins (1–8), and one dedicated pin (SR_SCLK).

• The SR_LAT can come from any of SPORT0–7 frame sync outputs, PCGA/B frame sync, any of the DAI pins (1–8), and one dedicated pin (SR_LAT).

• The SR_SDI input can from any of SPORT0–7 serial data outputs, any of the DAI pins (1–8), and one dedicated pin (SR_SDI).

Note that the SR_SCLK, SR_LAT, and SR_SDI inputs must come from same source except in the case of where SR_SCLK comes from PCGA/B or SR_SCLK and SR_LAT come from PCGA/B.

If SR_SCLK comes from PCGA/B, then SPORT0–7 generates the SR_LAT and SR_SDI signals. If SR_SCLK and SR_LAT come from PCGA/B, then SPORT0–7 generates the SR_SDI signal.

I/O PROCESSOR FEATURES

The I/O processor provides up to 65 channels of DMA as well as an extensive set of peripherals.

DMA Controller

The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the processor’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP) or the UART.

Up to 65 channels of DMA are available on the processors as shown in Table 9.

Programs can be downloaded using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers.

Table 9. DMA Channels

Peripheral DMA Channels

SPORTs 16 PDAP 8 SPI 2 UART 2

Table 9. DMA Channels (Continued)

Peripheral DMA Channels

External Port 2 Accelerators 2 Memory-to-Memory 2 MediaLB

Automotive models only.

Delay Line DMA

The processor provides delay line DMA functionality. This allows processor reads and writes to external delay line buffers (and therefore to external memory) with limited core interaction.

Scatter/Gather DMA

The processor provides scatter/gather DMA functionality. This allows processor DMA reads/writes to/from noncontiguous memory blocks.

FFT Accelerator

The FFT accelerator implements radix-2 complex/real input, complex output FFTs with no core intervention. The FFT accelerator runs at the peripheral clock frequency.

FIR Accelerator

The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency.

IIR Accelerator

The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coefficients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accelerator runs at the peripheral clock frequency.

Watchdog Timer ( WDT)

The processors include a 32-bit watchdog timer that can be used to implement a software watchdog function. A software watchdog can improve system reliability by forcing the processor to a known state through generation of a system reset if the timer expires before being reloaded by software. Software initializes the count value of the timer, and then enables the timer.

The WDT is used to supervise the stability of the system software. When used in this way, software reloads the WDT in a regular manner so that the downward counting timer never expires. An expiring timer then indicates that system software might be out of control.

The WDT resets both the core and the internal peripherals. Software must be able to determine if the watch dog was the source of the hardware reset by interrogating a status bit in the watch dog timer control register.

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ADSP-21477/ADSP-21478/ADSP-21479

RTXO

C1 C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAI LS. C1 AND C2 SPECIFICATIONS ASSUME BOARD TRACE CAPACIT ANCE OF 3 pF.

RTXI

The watch dog timer also has an internal RC oscillator that can be used as the clock source. The internal RC oscillator can be used as an optional alternative to using an external clock applied to the WDT_CLIN pin.

Real-Time Clock

The real-time clock (RTC) provides a robust set of digital watch features, including current time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz crystal external to the SHARC processor. Connect RTC pins RTXI and RTXO with external components as shown in Figure 3.

The RTC peripheral has dedicated power supply pins so that it can remain powered up and clocked even when the rest of the processor is in a low power state. The RTC provides several programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. An RTCLKOUT signal that operates at 1 Hz is also provided for calibration.

Figure 3. External Components for RTC

The 32.768 kHz input clock frequency is divided down to a 1 Hz signal by a prescaler. The counter function of the timer consists of four counters: a 60-second counter, a 60-minute counter, a 24-hour counter, and a 32,768-day counter. When the alarm interrupt is enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. There are two alarms: The first alarm is for a time of day. The second alarm is for a day and time of that day.

The stopwatch function counts down from a programmed value, with one-second resolution. When the stopwatch interrupt is enabled and the counter underflows, an interrupt is generated.

SYSTEM DESIGN

The following sections provide an introduction to system design options and power supply issues.

Program Booting

The internal memory boots at system power-up from an 8-bit EPROM via the external port, an SPI master, or an SPI slave. Booting is determined by the boot configuration (BOOT_CFG2–0) pins in Table 10.

Table 10. Boot Mode Selection

BOOT_CFG2–01Booting Mode

000 SPI Slave Boot 001 SPI Master Boot (from Flash and Other Slaves) 010 AMI User Boot (for 8-bit Flash Boot) 011 No Boot (Processor Executes from Internal

ROM After Reset) 100 Reserved 1xx Reserved

The BOOT_CFG2 pin is not available on the 100-lead or 88-lead packages.

A running reset feature is used to reset the processor core and peripherals without resetting the PLL and SDRAM controller, or performing a boot. The functionality of the RESETOUT /RUNRSTIN

pin has now been extended to also act as the input for initiating a running reset. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.

Power Supplies

The processors have separate power supply connections for the internal (V internal and analog supplies must meet the V tions. The external supply must meet the V

) and external (V

DD_INT

) power supplies. The

DD_EXT

DD_INT

DD_EXT

specifica-

specification. All external supply pins must be connected to the same power supply.

To reduce noise coupling, the PCB should use a parallel pair of power and ground planes for V

DD_INT

and GND.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the processors to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP Tools product line of JTAG emulator operation, see the appropriate emulator hardware user’s guide.

DEVELOPMENT TOOLS

The processors are supported with a complete set of CROSSCORE including Analog Devices emulators and VisualDSP++ opment environment. The same emulator hardware that supports other SHARC processors also fully emulates the processors.

EZ-KIT Lite Evaluation Board

For evaluation of the processors, use the EZ-KIT Lite® board being developed by Analog Devices. The board comes with onchip emulation capabilities and is equipped to enable software development. Multiple daughter cards are available.

software and hardware development tools,

devel-

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ADSP-21477/ADSP-21478/ADSP-21479

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. Nonintrusive incircuit emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing. The emulator uses the TAP to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical layout, single processor connections, signal buffering, signal termination, and emulator pod logic, see the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)—use site search on “EE-68.” This document is updated regularly to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation platforms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors, platforms, and software tools. Each EZ-KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment with the C/C++ compiler, assembler, and linker. Also included are sample application programs, power supply, and a USB cable. All evaluation versions of the software tools are limited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the board to the USB port of the user’s PC, enabling the VisualDSP++ evaluation suite to emulate the on-board processor in-circuit. This permits the customer to download, execute, and debug programs for the EZ-KIT Lite system. It also allows in-circuit programming of the on-board Flash device to store user-specific boot code, enabling the board to run as a standalone unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any custom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high speed, nonintrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2147x architecture and functionality. For detailed information on the family core architecture and instruction set, refer to the SHARC Processor Programming Reference.

RELATED SIGNAL CHAINS

A signal chain is a series of signal conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. For more information about this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well. A tool for viewing relationships between specific applications and related components is available on the

www.analog.com website.

The Circuits from the Lab

chains) provides:

• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection guides and application information

• Reference designs applying best practice design techniques

site (www.analog.com/signal

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PIN FUNCTION DESCRIPTIONS

Table 11. Pin Descriptions

State During/

Name Type

ADDR

DATA

23–0

15–0

I/O/T (ipu) High-Z/driven

I/O/T (ipu) High-Z External Data. The data pins can be multiplexed to support the external memory

AMI_ACK I (ipu) Memory Acknowle dge. External devices can deassert AMI_ACK (low) to add wait

0–1

O/T (ipu) High-Z Memory Select Lines 0–1. These lines are asserted (low) as chip selects for the

AMI_RD O/T (ipu) High-Z AMI Port Read Enable. AMI_RD is asser ted whenever the processor reads a word

AMI_WR O/T (ipu) High-Z AMI Port Write Enable. AMI_WR is asserted when the processor writes a word to

FLAG0/IRQ0

FLAG1/IRQ1

FLAG2/IRQ2

/MS2 I/O (ipu) FLAG[2] INPUT FLAG2/Interrupt Request2/Memory Select2. This pin is multiplexed with MS2

FLAG3/TMREXP/MS3

I/O (ipu) FLAG[0] INPUT FLAG0/Interrupt Request0.

I/O (ipu) FLAG[1] INPUT FLAG1/Interrupt Request1.

I/O (ipu) FLAG[3] INPUT FLAG3/Timer Expired/Memory Select3. This pin is multiplexed with MS3 in the

The following symbols appear in the Type column of Tabl e 11: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive, O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor. The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be 26 k to 63 k. The range of an ipd resistor can be 31 k to 85 k. The three-state voltage of ipu pads will not reach to full the V the voltage is in the range of 2.3 V to 2.7 V. In this table, all pins are LVTTL compliant with the exception of the thermal diode, shift register, and real-time clock (RTC) pins. Not all pins are available in the 88-lead LFCSP_VQ and 100-lead LQFP package. For more information, see Table 2 on Page 3 and Table 62 on

Page 69.

After Reset Description

External Address. The processor outputs addresses for external memory and

low (boot)

peripherals on these pins. The ADDR pins can be multiplexed to support the external memory interface address, FLAGS15–8 (I/O) and PWM (O). After reset, all ADDR pins are in EMIF mode, and FLAG(0–3) pins are in FLAGS mode (default). When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the ADDR pins for parallel input data.

interface data (I/O) and FLAGS

states to an external memory access. AMI_ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access.

corresponding banks of external memory. The MS address lines that change at the same time as the other address lines. When no external memory access is occurring the MS however when a conditional memory access instruction is executed, whether or not the condition is true. The MS1

pin can be used in EPORT/FLASH boot mode. For more information on

processor booting, see the ADSP-214xx SHARC Processor Hardware Reference.

from external memory.

external memory.

in the 196-ball BGA package only.

196-ball BGA package only.

7–0

(I/O).

lines are decoded memory

1-0

lines are inactive; they are active

1-0

level; at typical conditions

DD_EXT

23–4

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Table 11. Pin Descriptions (Continued)

State During/

Name Type

SDRAS O/T (ipu) High-Z/

SDCAS O/T (ipu) High-Z/

SDWE O/T (ipu) High-Z/

SDCKE O/T (ipu) High-Z/

SDA10 O/T (ipu) High-Z/

SDDQM O/T (ipu) High-Z/

SDCLK O/T (ipd) High-Z/

DAI _P

20–1

DPI _P

14–1

WDT_CLKIN I Watch Dog Timer Clock Input. This pin should be pulled low when not used.

WDT_CLKO O Watch Dog Resonator Pad Output.

WDTRSTO

Page 69.

I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the

I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI

O (ipu) Watch Dog Timer Reset Out.

After Reset Description

SDRAM Row Address Strobe. Connect to SDRAM’s RAS pin. In conjunction with

driven high

driving

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Column Address Select. Connect to SDRAM’s CAS pin. In conjunction with other SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Write Enable. Connect to SDRAM’s WE or W buffer pin.

SDRAM Clock Enab le. Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with nonSDRAM accesses. This pin replaces the DSP’s ADDR10 pin only during SDRAM accesses.

DQM Data Mask. SDRAM input mask signal for write accesses and output enable signal for read accesses. Input data is masked when DQM is sampled high during a write cycle. The SDRAM output buffers are placed in a High-Z state when DQM i s s a mp l e d h i gh d u ri n g a r ea d c yc l e. S DD Q M is d ri v e n h i gh f ro m re s e t d e - as s er t i on until SDRAM initialization completes. Afterwards, it is driven low irrespective of whether any SDRAM accesses occur or not.

SDRAM Clock Output. Clock driver for this pin differs from all other clock drivers. See Figure 47 on Page 64. For models in the 100-lead package, the SDRAM interface should be disabled to avoid unnecessary power switching by setting the DSDCTL bit in SDCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.

DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio-centric peripheral inputs or outputs connected to the pin and to the pin’s output enable. The configuration registers of these peripherals then determines the exact behavior of the pin. Any input or output signal present in the DAI SRU may be routed to any of these pins.

SRU. The DPI SRU configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to the pin's output enable. The configuration registers of these peripherals then determine the exact behavior of the pin. Any input or output signal present in the DPI SRU may be routed to any of these pins.

level; at typical conditions

DD_EXT

Rev. B | Page 16 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Table 11. Pin Descriptions (Continued)

State During/

Name Type

THD_P I Thermal Diode Anode. When not used, this pin can be left floating.

THD_M O Thermal Diode Cathode. When not used, this pin can be left floating.

MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is

MLBDAT I/O/T in 3 pin

mode. I in 5 pin mode.

MLBSIG I/O/T in 3 pin

mode. I in 5 pin mode

MLBDO O/T High-Z Media Local Bus Data Output (in 5 Pin Mode). This pin is used only in 5-pin MLB

MLBSO O/T High-Z Media Local Bus Signal Output (in 5 Pin Mode). This pin is used only in 5-pin

SR_SCLK I (ipu) Shift Register Serial Clock. (Active high, rising edge sensitive)

SR_CLR

SR_SDI I (ipu) Shift Register Serial Data Input.

SR_SDO O (ipu) Driven Low Shift Register Serial Data Output.

SR_LAT I (ipu) Shift Register Latch Clock Input. (Active high, rising edge sensitive)

SR_LDO

RTXI I RTC Crystal Input. If RTC is not used, then this pin needs to be NC (no connect)

RTXO O RTC Crystal Output. If RTC is not used, then this pin needs to be NC (No Connect).

RTCLKOUT O (ipd) RTC Clock Output. For calibration purposes. The clock runs at 1 Hz. If RTC is not

Page 69.

17–0

I (ipu) Shift Register Reset. (Active low)

O/T (ipu) High-Z Shift Register Parallel Data Output.

After Reset Description

synchronized to the MOST network and provides the timing for the entire MLB interface at 49.152 MHz at FS = 48 kHz. When the MLB controller is not used, this pin should be grounded.

High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device

and is received by all other MLB devices including the MLB controller. The MLBDAT line carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB controller is not used, this pin should be grounded.

High-Z Media Local Bus Signal. This is a multiplexed signal which carries the

Channel/Address generated by the MLB Controller, as well as the Command and RxStatus bytes from MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, this pin should be grounded.

mode and serves as the output data pin. When the MLB controller is not used, this pin should be grounded.

MLB mode and serves as the output signal pin. When the MLB controller is not used, this pin should be grounded.

and the RTC_PDN and RTC_BUSDIS bits of RTC_INIT register must be set to 1.

used, then this pin needs to be NC (No Connect).

level; at typical conditions

DD_EXT

Rev. B | Page 17 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Table 11. Pin Descriptions (Continued)

State During/

Name Type

TDI I (ipu) Test Data Input (JTAG). Provides serial data for the boundary scan logic.

TDO O/T High-Z Test Data Output (JTAG). Serial scan output of the boundary scan path.

TMS I (ipu) Tes t Mode Select ( JTAG). Used to control the test state machine.

TCK I Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

TRST

EMU

CLK_CFG

CLKIN I Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It

XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

RESET

RESETOUT

BOOT_CFG

Page 69.

1–0

/RUNRSTIN I/O (ipu) Reset Out/Running Reset In. The default setting on this pin is reset out. This pin

2–0

I (ipu) Test Reset (JTAG ). Resets the test state machine. TRST must be asserted (pulsed

O (O/D, ipu) High-Z Emulation Status. Must be connected to the Analog Devices DSP Tools product

I Core to CLKIN Ratio Control. These pins set the startup clock frequency.

I Processor Reset. Resets the processor to a known state. Upon deassertion, there

I Boot Configuration Select. These pins select the boot mode for the processor.

After Reset Description

(pulsed low) after power-up or held low for proper operation of the device.

low) after power-up or held low for proper operation of the processor.

line of JTAG emulators target board connector only.

Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset. The allowed values are: 00 = 8:1

01 = 32:1 10 = 16:1

11 = reserved

configures the processors to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the ex ternal clock to CLKIN while leaving XTAL unconnected configures the processors to use the external clock source such as an external clock oscillator. CLKIN may not be halted, changed, or operated below the specified frequency.

crystal.

is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution from the hardware reset vector address. The RESET be asserted (low) at power-up.

also has a second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register. For more information, see the ADSP-214xx SHARC Processor Hardware Reference.

The BOOT_CFG pins must be valid before RESET asserted. The BOOT_CFG2 pin is only available on the 196-lead package.

input must

(hardware and software) is de-

level; at typical conditions

DD_EXT

Rev. B | Page 18 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Table 12. Pin List, Power and Ground

Name Type Description

DD_INT

DD_EXT

DD_RTC

GND

DD_THD

The exposed pad is required to be electrically and thermally connected to GND. Implement this by soldering the exposed pad to a GND PCB land that is the same size as the

exposed pad. The GND PCB land should be robustly connected to the GND plane in the PCB for best electrical and thermal performance. See also 88-LFCSP_VQ Lead

Assignment on Page 67 and 100-LQFP_EP Lead Assignment on Page 69.

P Internal Power Supply.

P I/O Power Supply.

P Real-Time Clock Power Supply.

G Ground.

P Thermal Diode Power Supply. When not used, this pin can be left floating.

Rev. B | Page 19 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

SPECIFICATIONS

OPERATING CONDITIONS

200 MHz 266 MHz 300 MHz

Parameter

DD_INT

DD_EXT

DD_THD

DD_RTC

IH_CLKIN

IL_CLKIN

Specifications subject to change without notice.

Applies to input and bidirectional pins: ADDR23–0, DATA15–0, FLAG3–0, DAI_Px, DPI_Px, BOOT_CFGx, CLK_CFGx, RUNRSTIN, RESET, TCK, TMS, TDI, TRST, SDA10,

AMI_ACK, MLBCLK, MLBDAT, MLBSIG.

Applies to input pin CLKIN, WDT_CLKIN.

Applies to automotive models only. See Automotive Products on Page 74.

Real Time Clock (RTC) is supported only for products with a temperature range of 0°C to +70°C and not supported for all other temperature grades. For the status of unused

RTC pins please see Table 11 on Page 15.

Description Min Nom Max Min Nom Max Min Nom Max Unit

Internal (Core) Supply Voltage 1.14 1.2 1.26 1.14 1.2 1.26 1.25 1.3 1.35 V External (I/O) Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V Thermal Diode Supply Voltage 3.13 3.3 3.47 3.13 3.3 3.47 3.13 3.3 3.47 V Real-Time Clock Power Supply Voltage 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.6 V High Level Input Voltage @ V Low Level Input Voltage @ V

High Level Input Voltage @ V Low Level Input Voltage @ V Junction Temperature 88-Lead LFCSP_VQ @

0°C to +70°C

AMBIENT

Junction Temperature 88-Lead LFCSP_VQ @

–40°C to +85°C

AMBIENT

Junction Temperature 88-Lead LFCSP_VQ @ T

–40°C to +105°C

AMBIENT

Junction Temperature 100-Lead LQFP_EP @

0°C to +70°C

AMBIENT

Junction Temperature 100-Lead LQFP_EP @ T

–40°C to +85°C

AMBIENT

Junction Temperature 100-Lead LQFP_EP @

–40°C to +105°C

AMBIENT

Junction Temperature 196-Ball CSP_BGA @ T

0°C to +70°C

AMBIENT

Junction Temperature 196-Ball CSP_BGA @

–40°C to +85°C

AMBIENT

= Max 2.0 2.0 2.0 V

DD_EXT

= Min 0.8 0.8 0.8 V

DD_EXT

= Max 2.2 V

DD_EXT

= Max –0.3 0.8 –0.3 0.8 –0.3 0.8 V

DD_EXT

2.2 V

DD_EXT

0 105 N/A N/A N/A N/A °C

–40 +115 N/A N/A N/A N/A °C

–40 +125 N/A N/A N/A N/A °C

0 105 0 105 N/A N/A °C

N/A N/A –40 +125 N/A N/A °C

–40 +125 –40 +125 N/A N/A °C

N/A N/A 0 105 0 100 °C

N/A N/A –40 +125 N/A N/A °C

DD_EXT

Rev. B | Page 20 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

ELECTRICAL CHARACTERISTICS

200 MHz 266 MHz 300 MHz

Description Test Conditions Min Max Min Max Min Max

I I

ILPU

4, 5

High Level Output Voltage @ V

Low Level Output Voltage @ V

IOL = 1.0 mA

High Level Input Current @ V

Low Level Input Current @ V Low Level Input Current

@ V

= Min,

DD_EXT

= –1.0 mA

DD_EXT

= V

DD_EXT

= Min,

= Max,

Max

DD_EXT

= Max, VIN = 0 V –10 –10 –10 µA = Max, VIN = 0 V 200 200 200 µA

2.4 2.4 2.4 V

0.4 0.4 0.4 V

10 10 10 µA

Pull-up

OZH

OZL

6, 7

Three-State Leakage Current

Three-State Leakage

@ V

DD_EXT

VIN = V @ V

DD_EXT

= Max,

DD_EXT

Max

10 10 10 µA

= Max, VIN = 0 V –10 –10 –10 µA

Current

OZLPU

Three-State Leakage

@ V

= Max, VIN = 0 V 200 200 200 µA

DD_EXT

Current Pull-up

OZHPD

DD_RTC

Three-State Leakage Current Pull-down

Current @ V

DD_RTC

@ V

DD_EXT

VIN = V

DD_RTC

= Max,

DD_EXT

= 3.0,

200 200 200 µA

Max

0.76 0.76 0.76 µA

TJ = 25°C

DD-INTYP

10, 11

Specifications subject to change without notice.

Applies to output and bidirectional pins: ADDR23-0, DATA15-0, AMI_RD, AMI_WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, RESETOUT,MLBSIG, MLBDAT, MLBDO,

MLBSO, SDRAS, SDCAS, SDWE, SDCKE, SDA10, SDDQM, MS0-1.

See Output Drive Currents on Page 64 for typical drive current capabilities.

Applies to input pins: BOOT_CFGx, CLK_CFGx, TCK, RESET, CLKIN.

Applies to input pins with internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: TDO, MLBDAT, MLBSIG, MLBDO, and MLBSO.

Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU.

Applies to three-statable pin with pull-down: SDCLK.

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for further information.

Applies to all signal pins.

Guaranteed, but not tested.

Supply Current (Internal) f

Input Capacitance T

> 0 MHz Tab le 1 4

CCLK

Tab le 1 5

× ASF

= 25°C 5 5 5 pF

CASE

Tab le 1 4

Tab le 1 5

× ASF

Tab le 1 4

Tab le 1 5

× ASF

UnitParameter

Rev. B | Page 21 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

Total Power Dissipation

Total power dissipation has two components:

1. Internal power consumption

2. External power consumption

Internal power consumption also comprises two components:

1. Static, due to leakage current. Table 14 shows the static current consumption (I temperature (T

2. Dynamic (I

DD-DYNAMC

DD-STATIC

) and core voltage (V

) as a function of junction

DD_INT

), due to transistor switching characteristics and activity level of the processor. The activity level is reflected by the Activity Scaling Factor (ASF), which represents application code running on the processor core and having various levels of peripheral and external port activity (Table 13). Dynamic current consumption is calculated by scaling the specific application by the ASF and using baseline dynamic current consumption as a reference. The ASF is combined with the CCLK frequency and V

DD_INT

dependent data in Table 15 to calculate this part.

External power consumption is due to the switching activity of the external pins.

Table 13. Activity Scaling Factors (ASF)

Activity Scaling Factor (ASF)

Idle 0.31 Low 0.53 Medium Low 0.62 Medium High 0.78 Peak-Typical (50:50) Peak-Typical (60:40) Peak-Typical (70:30) High Typical 1.18 High 1.28 Peak 1.34

See Estimating Power for ADSP-214xx SHARC Processors (EE-348) for more

information on the explanation of the power vectors specific to the ASF table.

Ratio of continuous instruction loop (core) to SDRAM control code reads and

writes.

0.85

0.93

1.00

Table 14. Static Current—I

TJ (°C)

1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V

DD-STATIC

(mA)

(V)

DD_INT

–45 < 0.1 < 0.1 0.4 0.8 1.3 2.1 3.3 –35 < 0.1 < 0.1 0.4 0.7 1.1 1.7 2.9 –25 < 0.1 0.2 0.4 0.8 1.2 1.7 2.9 –15 < 0.1 0.4 0.6 1.0 1.4 1.9 3.2 –5 0.2 0.6 0.9 1.3 1.8 2.3 3.7 +5 0.5 0.9 1.3 1.8 2.3 3.0 4.4 +15 0.8 1.4 1.8 2.3 3.0 3.7 5.1 +25 1.3 1.9 2.5 3.1 3.9 4.7 6.2 +35 2.0 2.8 3.4 4.2 5.1 6.0 8.0 +45 3.0 3.9 4.7 5.7 6.7 7.8 10.1 +55 4.3 5.4 6.3 7.6 8.8 10.3 12.9 +65 6.0 7.3 8.6 10.1 11.7 13.5 16.4 +75 8.3 9.9 11.5 13.3 15.3 17.4 21.2 +85 11.2 13.2 15.3 17.5 19.9 22.6 27.1 +95 15.2 17.6 20.1 22.9 26.1 29.4 34.6 +100 17.4 20.2 22.9 25.9 29.4 33.0 39.2 +105 20.0 23.0 26.1 29.5 33.4 N/A N/A +115 26.3 30.0 33.9 38.2 42.9 N/A N/A +125 34.4 38.9 43.6 48.8 54.8 N/A N/A

Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 20.

Rev. B | Page 22 of 76 | March 2012

ADSP-21477/ADSP-21478/ADSP-21479

vvvvvv.x n.n

tppZ-cc

ADSP-2147x

#yyww country_of_origin

ESD

(electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

Table 15. Baseline Dynamic Current in CCLK Domain (mA, with ASF = 1.0)

Voltage (V

CCLK

(MHz)

1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V

1, 2

DD_INT

)

10075788286909598 150 111 117 122 128 134 141 146 200 N/A N/A 162 170 178 186 194 266 N/A N/A 215 225 234 246 256 300 N/A N/A N/A N/A 264 279 291

The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 21.

Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 20.

MAXIMUM POWER DISSIPATION

ESD SENSITIVITY

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2147x SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Thermal

Characteristics on Page 65.

PACKAGE INFORMATION

The information presented in Figure 4 provides details about the package branding. For a complete listing of product availability, see Ordering Guide on Page 75.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 17 may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in Operating Conditions on

Page 20 is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Table 17. Absolute Maximum Ratings

Parameter Rating

Figure 4. Typical Package Brand

Table 16. Package Brand Information

Brand Key Field Description

t Temperature Range pp Package Type Z RoHS Compliant Option

Internal (Core) Supply Voltage (V External (I/O) Supply Voltage (V Real Time Clock Voltage (V

DD_RTC

Thermal Diode Supply Voltage (V Input Voltage –0.5 V to +3.8 V Output Voltage Swing –0.5 V to V Storage Temperature Range –65°C to +150°C Junction Temperature While Biased 125°C

) –0.3 V to +1.35 V

DD_INT

)–0.3 V to +4.6 V

DD_EXT

)–0.3 V to +4.6 V

DD_THD

+0.5 V

DD_EXT

cc See Ordering Guide vvvvvv.x Assembly Lot Code n.n Silicon Revision # RoHS Compliant Designation yyww Date Code

Nonautomotive only. For branding information specific to automotive products,

contact Analog Devices Inc.

Rev. B | Page 23 of 76 | March 2012

+ 53 hidden pages

ANALOG DEVICES ADSP-21477, ADSP-21478, ADSP-21479 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SUMMARY

TABLE OF CONTENTS

REVISION HISTORY

PRODUCT APPLICATION RESTRICTION

GENERAL DESCRIPTION

FAMILY CORE ARCHITECTURE

SIMD Computational Engine

Independent, Parallel Computation Units

Timer

Data Register File

Context Switch

Universal Registers

Single-Cycle Fetch of Instruction and Four Operands

Instruction Cache

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

Flexible Instruction Set

Variable Instruction Set Architecture (VISA)

On-Chip Memory

On-Chip Memory Bandwidth

ROM Based Security

Digital Transmission Content Protection

FAMILY PERIPHERAL ARCHITECTURE

External Memory

External Port

SIMD Access to External Memory

VISA and ISA Access to External Memory

SDRAM Controller

Asynchronous Memory Controller

External Port Throughput

MediaLB

Digital Applications Interface (DAI)

Serial Ports (SPORTs)

S/PDIF-Compatible Digital Audio Receiver/Transmitter

Asynchronous Sample Rate Converter (SRC)

Input Data Port

Precision Clock Generators

Digital Peripheral Interface (DPI)

Serial Peripheral (Compatible) Interface (SPI)

UART Port

Pulse-Width Modulation

Ti me rs

2-Wire Interface Port (TWI)

Shift Register

I/O PROCESSOR FEATURES

DMA Controller

Delay Line DMA

Scatter/Gather DMA

FFT Accelerator

FIR Accelerator

IIR Accelerator

Watchdog Timer ( WDT)

Real-Time Clock

SYSTEM DESIGN

Program Booting

Power Supplies

Target Board JTAG Emulator Connector

DEVELOPMENT TOOLS

EZ-KIT Lite Evaluation Board

Designing an Emulator-Compatible DSP Board (Target)

Evaluation Kit

ADDITIONAL INFORMATION

RELATED SIGNAL CHAINS

PIN FUNCTION DESCRIPTIONS

SPECIFICATIONS

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Total Power Dissipation

MAXIMUM POWER DISSIPATION

ESD SENSITIVITY

PACKAGE INFORMATION

ABSOLUTE MAXIMUM RATINGS