ANALOG DEVICES ADSP-21371, ADSP-21375 Service Manual

SHARC Processor

Internal Memory I/F

Block 0

RAM/ROM

B0D

64-BIT

Instruction

Cache

5 stage

Sequencer

PEx PEy

PMD 64-BIT

IODO 32-BIT

EPD BUS 48-BIT

Core Bus

Cross Bar

DAI Routing/Pins

PCG
A

-

D

DPI Routing/Pins

SPI/B UART

Block 1

RAM/ROM

Block 2

RAM

Block 3

RAM

AMI

SDRAM

EP

External Port Pin MUX

TIMER

1

-

0

SPORT

7

-

0

PWM

3

-

0

DAG1/2 Timer

IDP/

PDAP

7

-

0

TWI

IOD0 BUS

MTM/

PCG
C

-

D

PERIPHERAL BUS

32-BIT

CORE

FLAGS

FLAGx/IRQx/
TMREXP

JTAG

Internal Memory

DMD 64-BIT

PMD 64-BIT

CORE

FLAGS

IOD1
32-BIT

PERIPHERAL BUS

B1D

64-BIT

B2D

64-BIT

B3D

64-BIT

DPI Peripherals DAI Peripherals Peripherals

External
Port

SIMD Core

S

DTCP

S/PDIF
Tx/Rx

DMD 64-BIT

ADSP-21371/ADSP-21375

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory, ADSP-21371—1M bits of on-chip SRAM

and 4M bits of on-chip mask-programmable ROM

On-chip memory, ADSP-21375—0.5M bits of on-chip

SRAM and 2M bits of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family

The ADSP-21371/ADSP-21375 processors are available with a

200/266 MHz core instruction rate with unique audiocen­tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-

ing Guide on Page 52.

DEDICATED AUDIO COMPONENTS

ADSP-21371—S/PDIF-compatible digital audio

receiver/transmitter

ADSP-21371—8 dual data line serial ports that operate at up

to 50 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a

receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios
Available in a 208-lead LQFP_EP package

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

Figure 1. Functional Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2009 Analog Devices, Inc. All rights reserved.

ADSP-21371/ADSP-21375

TABLE OF CONTENTS

Summary ............................................................... 1

Dedicated Audio Components .................................... 1

Revision History ...................................................... 2

General Description ................................................. 3

SHARC Family Core Architecture ............................ 4

Family Peripheral Architecture ................................ 6

I/O Processor Features ......................................... 10

System Design .................................................... 11

Development Tools ............................................. 11

Additional Information ........................................ 12

Pin Function Descriptions ....................................... 13

ADSP-21371/ADSP-21375 Specifications .. . ................. 16

Operating Conditions .......................................... 16

Electrical Characteristics ....................................... 16

Package Information ........................................... 17

REVISION HISTORY

9/09—Rev. B to Rev. C

Corrected all outstanding document errata. Also replaced core
clock references (CCLK) in the timing specifications with
peripheral clock references (PCLK).

Added operating conditions and electrical characteristics
for the 1.0 V, 200 MHz parts.

For this revision the following sections have been removed. For
information see the ADSP-2137x SHARC Processor Hardware
Reference: “Address Data Pins as Flags”, “Address/Data Modes”,
Core Instruction Rate to CLKIN Ratio Modes.”

Revised Figure 1, Functional Block Diagram ....................1

Added Table 2, ADSP-21371/ADSP-21375 Features ..........3

Added Figure 2, SHARC Core Block Diagram ..................4

Added Context Switch ...............................................5

Added Universal Registers ..........................................5

Added Timer ...........................................................5

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

ESD Sensitivity ................................................... 17

Timing Specifications ........................................... 17

Output Drive Currents ......................................... 45

Test Conditions .................................................. 45

Capacitive Loading .............................................. 45

Thermal Characteristics ........................................ 46

208-Lead LQFP_EP Pinout ....................................... 47

Package Dimensions ............................................... 51

Automotive Products .............................................. 52

Ordering Guide ..................................................... 52

Added On-Chip Memory Bandwidth ............................ 5

Added External Port Throughput ................................. 8

Added Input Data Port (IDP) ...................................... 9

Added Precision Clock Generator (PCG) ....................... 9

Added Scatter/Gather DMA .......................................11

Clarified VCO operations in

Voltage Controlled Oscillator .....................................18

Corrected the pins names for the DAI and DPI in 208-Lead

LQFP_EP Pinout .....................................................47

Added Automotive Products ......................................52

Rev. C | Page 2 of 52 | September 2009

GENERAL DESCRIPTION

ADSP-21371/ADSP-21375

The ADSP-21371/ADSP-21375 SHARC® processors are mem­bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code compatible with the ADSP-2126x, ADSP-2136x, and
ADSP-2116x DSPs, as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces­sors optimized for high performance automotive audio
applications with their large on-chip SRAM and mask-pro­grammable ROM, multiple internal buses to eliminate I/O
bottlenecks, and an innovative digital applications interface
(DAI).

As shown in the functional block diagram on Page 1, the pro­cessors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the processors achieve an instruction
cycle time of 3.75 ns at 266 MHz. With its SIMD computational
hardware, the processors can perform 1.596 GFLOPS running
at 266 MHz.

Table 1 shows performance benchmarks for these devices.
Table 2 shows the features of the individual product offerings.

Table 1. Processor Benchmarks (at 266 MHz)

Speed

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, With Reversal) 34.5 μs
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply (Pipelined)

[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]

Divide (y/x) 13.1 ns
Inverse Square Root 20.4 ns

1

Assumes two files in multichannel SIMD mode

1

1

(at 266 MHz)

1.88 ns

7.5 ns

16.91 ns

30.07 ns

Table 2. ADSP-21371/ADSP-21375 Features

Feature ADSP-21371 ADSP-21375

Frequency 266 MHz

(3.75 ns)

RAM 1M bit 0.5M bit

ROM 4M bits 2M bits

Pulse-Width
Modulation

Serial Ports 8 4

UART 1 1

Digital Application
Interface (DAI)

Ye s N o

Ye s Ye s

266 MHz
(3.75 ns)

Table 2. ADSP-21371/ADSP-21375 Features (Continued)

Feature ADSP-21371 ADSP-21375

Digital Peripheral
Interface (DPI)

S/PDIF Transceiver Yes No

SPI 2 2

TWI Yes Yes

Package 208-Lead LQFP_EP 208-Lead LQFP_EP

Ye s Ye s

The diagram on Page 1 shows the two clock domains that make
up the ADSP-2137x processors. The core clock domain contains
the following features:

• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

• One periodic interval timer with pinout

• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
ADSP-21375)

• On-chip mask-programmable ROM (4M bit, ADSP-21371;
2M bit, ADSP-21375)

• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break­points which allow flexible exception handling.

The diagram on Page 1 also shows the peripheral clock domains
(also known as the I/O processor) and contains the following
features:

•IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers

• Peripheral and external port bus for core connection

• Digital applications interface that includes four precision
clock generators (PCG), an S/PDIF-compatible digital
audio receiver/transmitter, an input data port (IDP), eight
serial ports, eight serial interfaces, a 20-bit parallel input
port (PDAP), and a flexible signal routing unit (DAI SRU).

• Digital peripheral interface that includes two timers, one
UART, two serial peripheral interfaces (SPI), a 2-wire
interface (TWI), and a flexible signal routing unit
(DPI SRU).

• External port with AMI and SDRAM controller

• Four units for PWM control

• One MTM for internal to internal memory transfers

Rev. C | Page 3 of 52 | September 2009

ADSP-21371/ADSP-21375

S

SIMD Core

CACHEINTERRUPT

5 STAGE

PROGRAM SEQUENCER

PM ADDRESS 32

DM ADDRESS 32

DM DATA 64

PM DATA 64

DAG1
16x32

MRF

80-BIT

ALU

MULTIPLIER

SHIFTER

RF

Rx/Fx

PEx

16x40-BIT

JTAG

DMD/PMD 64

PM DATA 48

ASTATx

STYKx

ASTATy

STYKy

TIMER

RF

Sx/SFx

PEy

16x40-BIT

MRB

80-BIT

MSB

80-BIT

MSF

80-BIT

FLAG

SYSTEM

I/F

US TAT

4x32-BIT

PX

64-BIT

DAG2
16x32

ALU

MULTIPLIER

SHIFTER

DATA
SWAP

PM ADDRESS 24

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21371/ADSP-21375 processors are code compatible
at the assembly level with the ADSP-2136x, ADSP-2126x,
ADSP-21160x, and ADSP-21161N, and with the first generation
ADSP-2106x SHARC processors. The ADSP-21371/
ADSP-21375 processors share architectural features with the
ADSP-2126x, ADSP-2136x, and ADSP-2116x SIMD SHARC
processors, as shown in Figure 2 and detailed in the following
sections.

SIMD Computational Engine

The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and
PEY, and each contains an ALU, multiplier, shifter, and register
file. PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele­ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele­ments. These computation units support IEEE 32-bit single­precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Figure 2. SHARC Core Block Diagram

Rev. C | Page 4 of 52 | September 2009

ADSP-21371/ADSP-21375

Data Register File

Each processing element contains a general-purpose data regis­ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the SHARC’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.

Context Switch

Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.

Universal Registers

Universal registers can be used for general purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.

The data bus exchange register PX permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These reg­isters contain hardware to handle the data width difference.

Tim er

The processors contain a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.

Single-Cycle Fetch of an Instruction and Four Operands

The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the processor’s separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch four operands (two over each data bus)
and one instruction (from the cache), all in a single cycle.

Instruction Cache

The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators with Zero-Overhead Hardware Circular Buffer Support

The processors’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal

processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim­plify implementation. Circular buffers can start and end at any
memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the proces­sors can conditionally execute a multiply, an add, and a subtract
in both processing elements while branching and fetching up to
four 32-bit values from memory—all in a single instruction.

On-Chip Memory

The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM (see

Table 3 on Page 6) and the ADSP-21375 processor contains 0.5

megabits of internal RAM and two megabits of internal mask­programmable ROM (see Table 4 on Page 7). Each block can be
configured for different combinations of code and data storage.
Each memory block supports single-cycle, independent accesses
by the core processor and I/O processor. The processor’s mem­ory architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.

The ADSP-21371 processor’s SRAM can be configured as a
maximum of 32k words of 32-bit data, 64k words of 16-bit data,

21.3k words of 48-bit instructions (or 40-bit data), or combina­tions of different word sizes up to 1 megabit. All of the memory
can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16­bit floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conver­sion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem­ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.

On-Chip Memory Bandwidth

The internal memory architecture allows four accesses at the
same time to any of the four blocks, assuming no block con­flicts. The total bandwidth is gained with DMD and PMD buses
(2 × 64-bits, core CLK) and the IOD0/1 buses (2 × 32-bit,
PCLK).

ROM-Based Security

The processors have a ROM security feature that provides hard­ware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any

Rev. C | Page 5 of 52 | September 2009

ADSP-21371/ADSP-21375

Table 3. ADSP-21371 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

BLOCK 0 ROM
0x0004 0000–0x0004 7FFF

Reserved
0x0004 8000–0x0004 BFFF

BLOCK 0 RAM
0x0004 C000–0x0004 CFFF

Reserved
0x0004 D000–0x0004 FFFF

BLOCK 1 ROM
0x0005 0000–0x0005 7FFF

Reserved
0x0005 8000–0x0005 BFFF

BLOCK 1 RAM
0x0005 C000–0x0005 CFFF

Reserved
0x0005 D000–0x0005 FFFF

BLOCK 2 RAM
0x0006 0000–0x0006 0FFF

Reserved
0x0006 1000–0x0006 FFFF

BLOCK 3 RAM
0x0007 0000–0x0007 0FFF

Reserved
0x0007 1000–0x0007 FFFF

Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM
0x0008 0000–0x0008 AAA9

Reserved
0x0008 AAAA–0x0008 FFFF

BLOCK 0 RAM
0x0009 0000–0x0009 1554

Reserved
0x0009 1555–0x0009 FFFF

BLOCK 1 ROM
0x000A 0000–0x000A AAA9

Reserved
0x000A AAAA–0x000A FFFF

BLOCK 1 RAM
0x000B 0000–0x000B 1554

Reserved
0x000B 1555–0x000B FFFF

BLOCK 2 RAM
0x000C 0000–0x000C 1554

Reserved
0x000C 1555–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 1554

Reserved
0x000E 1555–0x000F FFFF

BLOCK 0 ROM
0x0008 0000–0x0008 FFFF

Reserved
0x0009 0000–0x0009 7FFF

BLOCK 0 RAM
0x0009 8000–0x0009 9FFF

Reserved
0x0009 A000–0x0009 FFFF

BLOCK 1 ROM
0x000A 0000–0x000A FFFF

Reserved
0x000B 0000–0x000B 7FFF

BLOCK 1 RAM
0x000B 8000–0x000B 9FFF

Reserved
0x000B A000–0x000B FFFF

BLOCK 2 RAM
0x000C 0000–0x000C 1FFF

Reserved
0x000C 2000–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 1FFF

Reserved
0x000E 2000–0x000F FFFF

BLOCK 0 ROM
0x0010 0000–0x0011 FFFF

Reserved
0x0012 0000–0x0012 FFFF

BLOCK 0 RAM
0x0013 0000–0x0013 3FFF

Reserved
0x0013 4000–0x0013 FFFF

BLOCK 1 ROM
0x0014 0000–0x0015 FFFF

Reserved
0x0016 0000–0x0016 FFFF

BLOCK 1 RAM
0x0017 0000–0x0017 3FFF

Reserved
0x0017 4000–0x0017 FFFF

BLOCK 2 RAM
0x0018 0000–0x0018 3FFF

Reserved
0x0018 4000–0x001B FFFF

BLOCK 3 RAM
0x001C 0000–0x001C 3FFF

Reserved
0x001C 4000–0x001F FFFF

external code, executing exclusively from internal ROM. Addi­tionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.

FAMILY PERIPHERAL ARCHITECTURE

The ADSP-21371/ADSP-21375 family contains a rich set of
peripherals that support a wide variety of applications, includ­ing high quality audio, medical imaging, communications,
military, test equipment, 3D graphics, speech recognition, mon­itor control, imaging, and other applications.

Rev. C | Page 6 of 52 | September 2009

External Port

The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchro­nous and/or asynchronous memory devices through the use of
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asyn­chronous device types.

Table 4. ADSP-21375 Internal Memory Space

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 bits)

BLOCK 0 ROM
0x0004 0000–0x0004 3FFF

Reserved
0x0004 4000–0x0004 BFFF

BLOCK 0 RAM
0x0004 C000–0x0004 C7FF

Reserved
0x0004 C800–0x0004 FFFF

BLOCK 1 ROM
0x0005 0000–0x0005 3FFF

Reserved
0x0005 4000–0x0005 BFFF

BLOCK 1 RAM
0x0005 C000–0x0005 C7FF

Reserved
0x0005 C800–0x0005 FFFF

BLOCK 2 RAM
0x0006 0000–0x0006 07FF

Reserved
0x0006 0800–0x0006 FFFF

BLOCK 3 RAM
0x0007 0000–0x0007 07FF

Reserved
0x0007 0800–0x0007 FFFF

Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM
0x0008 0000–0x0008 5554

Reserved
0x0008 5555–0x0008 FFFF

BLOCK 0 RAM
0x0009 0000–0x0009 0AAA

Reserved
0x0009 0AAB–0x0009 FFFF

BLOCK 1 ROM
0x000A 0000–0x000A 5554

Reserved
0x000A 5555–0x000A FFFF

BLOCK 1 RAM
0x000B 0000–0x000B 0AAA

Reserved
0x000B 0AAB–0x000B FFFF

BLOCK 2 RAM
0x000C 0000–0x000C 0AAA

Reserved
0x000C 0AAB–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 0AAA

Reserved
0x000E 0AAB–0x000F FFFF

ADSP-21371/ADSP-21375

BLOCK 0 ROM
0x0008 0000–0x0008 7FFF

Reserved
0x0008 8000–0x0009 7FFF

BLOCK 0 RAM
0x0009 8000–0x0009 8FFF

Reserved
0x0009 9000–0x0009 FFFF

BLOCK 1 ROM
0x000A 0000–0x000A 7FFF

Reserved
0x000A 8000–0x000B 7FFF

BLOCK 1 RAM
0x000B 8000–0x000B 8FFF

Reserved
0x000B 9000–0x000B FFFF

BLOCK 2 RAM
0x000C 0000–0x000C 0FFF

Reserved
0x000C 1000–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 0FFF

Reserved
0x000E 1000–0x000F FFFF

BLOCK 0 ROM
0x0010 0000–0x0010 FFFF

Reserved
0x0011 0000–0x0012 FFFF

BLOCK 0 RAM
0x0013 0000–0x0013 1FFF

Reserved
0x0013 2000–0x0013 FFFF

BLOCK 1 ROM
0x0014 0000–0x0014 FFFF

Reserved
0x0015 0000–0x0016 FFFF

BLOCK 1 RAM
0x0017 0000–0x0017 1FFF

Reserved
0x0017 2000–0x0017 FFFF

BLOCK 2 RAM
0x0018 0000–0x0018 1FFF

Reserved
0x0018 2000–0x001B FFFF

BLOCK 3 RAM
0x001C 0000–0x001C 1FFF

Reserved
0x001C 2000–0x001F FFFF

Rev. C | Page 7 of 52 | September 2009

ADSP-21371/ADSP-21375

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa­rate banks of industry-standard SDRAM devices or DIMMs.
Fully compliant with the SDRAM standard, each bank has its
own memory select line (MS0
contain between 16M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 5.

The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the
different banks.

A set of programmable timing parameters is available to config­ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as 16 bits wide or as
32 bits wide. The SDRAM controller address, data, clock, and
command pins can drive loads up to 30 pF. For larger memory
systems, the SDRAM controller external buffer timing should
be sel ect ed a nd e xte rna l bu ffe rin g sh ould be pro vid ed s o th at t he
load on the SDRAM controller pins does not exceed 30 pF.

Table 5. External Memory for SDRAM Addresses

Bank Size in Words Address Range

Bank 0 62M 0x0020 0000–0x03FF FFFF
Bank 1 64M 0x0400 0000–0x07FF FFFF
Bank 2 64M 0x0800 0000–0x0BFF FFFF
Bank 3 64M 0x0C00 0000–0x0FFF FFFF

Note that the external memory bank addresses shown in Table 5
are for normal word accesses. If 48-bit instructions are placed in
any such bank (with two instructions packed into three 32-bit
locations), then care must be taken to map data buffers in the
same bank. For example, if 2k instructions are placed starting at
the bank 0 base address (0x0020 0000), then the data buffers can
be placed starting at an address that is offset by 3k words
(0x0020 0C00).

–MS3), and can be configured to

External Memory Code Execution

The program sequencer can execute code directly from external
memory bank 0 (SRAM, SDRAM) over the 48-bit external port
data bus (EPD). This allows a reduction in internal memory
size, thereby reducing the die area. With external execution,
programs run at slower speeds since 48-bit instructions are
fetched in parts from a 16-bit external bus coupled with the
inherent latency of fetching instructions from SDRAM. Fetch­ing instructions from external memory generally takes 1.5
peripheral clock cycles per instruction. Non SDRAM external
memory address space is shown in Table 6.

Table 6. External Memory for Non SDRAM Addresses

Bank Size in Words Address Range

Bank 0 14M 0x0020 0000–0x00FF FFFF
Bank 1 16M 0x0400 0000–0x04FF FFFF
Bank 2 16M 0x0800 0000–0x08FF FFFF
Bank 3 16M 0x0C00 0000–0x0CFF FFFF

External Port Throughput

The throughput for the external port, based on 133 MHz clock
and 32-bit data bus, is 177M bytes/s for the AMI and 532M
bytes/s for SDRAM.

Asynchronous Memory Controller

The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif­ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, flash, and EPROM,
as well as I/O devices that interface with standard memory con­trol lines. Bank 0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit or 16-bit wide buses for ease of interfac­ing to a range of memories and I/O devices tailored either to
high performance or to low cost and power.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave­forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non­paired mode (applicable to a single group of four PWM
waveforms).

The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.

The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a sec­ond updating of the PWM registers is implemented at the mid­point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis­tortion in three-phase PWM inverters.

Digital Applications Interface (DAI)

The digital applications interface (DAI) provides the ability to
connect various peripherals to any of the processor’s DAI pins
(DAI_P1 to DAI_P20).

Programs make these connections using the signal routing unit
(SRU), shown in Figure 1.

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI

Rev. C | Page 8 of 52 | September 2009

ADSP-21371/ADSP-21375

associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon­figurable signal paths.

In the ADSP-21371, the DAI includes eight serial ports, four
precision clock generators (PCG), and an input data port (IDP).
For the ADSP-21375, the DAI includes four serial ports, four
precision clock generators (PCG) and an input data port (IDP).

The IDP provides an additional input path to the core of the
processor, configurable as either eight channels of I

2

S serial
data, or a single 20-bit wide synchronous parallel data acquisi­tion port. Each data channel has its own DMA channel that is
independent from the processor’s serial ports.

Serial Ports

The processors feature eight synchronous serial ports on the
ADSP-21371 and four on the ADSP-21375. The SPORTs pro­vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices’
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.

For the ADSP-21371, serial ports are enabled via 16 program­mable pins and simultaneous receive or transmit pins that
support up to 32 transmit or 32 receive channels of audio data
when all eight SPORTs are enabled, or eight duplex TDM
streams of 128 channels per frame.

For the ADSP-21375, serial ports are enabled via eight program­mable pins and simultaneous receive or transmit pins that
support up to 16 transmit or 16 receive channels of audio data
when all four SPORTs are enabled, or four duplex TDM streams
of 128 channels per frame.

The serial ports operate at a maximum data rate of 50 Mbps.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig­nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

•Multichannel (TDM) mode with support for packed I

2

S

mode

2

•I

S mode

•Packed I

2

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

2

and I

S protocols (I2S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs such as the

Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I

2

S channels (using two stereo

2

S chan­nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I

2

S modes, data­word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional μ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter­nally or externally generated.

The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep­tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

The ADSP-21371 S/PDIF receiver/transmitter has no separate
DMA channels. It receives audio data in serial format and con­verts it into a biphase encoded signal. The serial data input to
the receiver/transmitter can be formatted as left justified, I

2

S or
right justified with word widths of 16, 18, 20, or
24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF
receiver/transmitter are routed through the signal routing unit
(SRU). They can come from a variety of sources such as the
SPORTs, external pins, the precision clock generators (PCGs),
and are controlled by the SRU control registers.

The ADSP-21375 does not have an S/PDIF-compatible digital
receiver/transmitter.

Input Data Port (IDP)

The IDP provides up to eight serial input channels—each with
its own clock, frame sync, and data inputs. The eight channels
are automatically multiplexed into a single 32-bit by eight-deep
FIFO. Data is always formatted as a 64-bit frame and divided
into two 32-bit words. The serial protocol is designed to receive
audio channels in I

2

S, left-justified sample pair, or right-justified
mode. One frame sync cycle indicates one 64-bit left/right pair,
but data is sent to the FIFO as 32-bit words (that is, one-half of a
frame at a time). The processor supports 24- and 32-bit I

2

S, 24­and 32-bit left-justified, and 24-, 20-, 18- and 16-bit right-justi­fied formats.

Precision Clock Generator (PCG)

The precision clock generators (PCG) consist of four units, each
of which generates a pair of signals (clock and frame sync)
derived from a clock input signal. The units, A B, C, and D, are
identical in functionality and operate independently of each
other. The two signals generated by each unit are normally used
as a serial bit clock/frame sync pair.

Rev. C | Page 9 of 52 | September 2009

ADSP-21371/ADSP-21375

Digital Peripheral Interface (DPI)

The digital peripheral interface provides connections to two
serial peripheral interface (SPI) ports, one universal asynchro­nous receiver-transmitter (UART), 12 flags, a 2-wire interface
(TWI), and two general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21371/ADSP-21375 SHARC processors contain two
serial peripheral interface ports (SPIs). The SPI is an industry­standard synchronous serial link, enabling the SPI-compatible
ports of the processors to communicate with other SPI compati­ble devices. The SPI consists of two data pins, one device select
pin, and one clock pin. It is a full-duplex synchronous serial
interface, supporting both master and slave modes. The SPI port
can operate in a multimaster environment by interfacing with
up to four other SPI-compatible devices, either acting as a mas­ter or slave device.

The SPI-compatible peripheral implementation also features
programmable baud rates and clock phases and polarities. The
SPI-compatible port uses open drain drivers to support a multi­master configuration and to avoid data contention.

UART Port

The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli­fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa­bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface stan­dard. The UART port also includes support for 5 to 8 data bits, 1
or 2 stop bits, and none, even, or odd parity. The UART port
supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans­fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

The UART port’s baud rate, serial data format, error code gen­eration and status, and interrupts are programmable. The port:

• Supports bit rates ranging from (f
(f

/16) bits per second.

PCLK

/1,048,576) to

PCLK

• Supports data formats from 7 to 12 bits per frame.

• Can be configured to generate maskable interrupts for both
transmit and receive operations.

In conjunction with the general-purpose timer functions, auto­baud detection is supported.

Peripheral Timers

Two general-purpose timers can generate periodic interrupts
and be independently set to operate in one of three modes:

•Pulse waveform generation mode

•Pulse width count/capture mode

• External event watchdog mode

Each general-purpose timer has one bidirectional pin and four
registers that implement its mode of operation: a 6-bit configu­ration register, a 32-bit count register, a 32-bit period register,
and a 32-bit pulse width register. A single control and status
register enables or disables the general-purpose timers
independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit
data while maintaining compliance with the I

2

C bus protocol.

The TWI master incorporates the following features:

• Simultaneous master and slave operation on multiple
device systems with support for multi master data
arbitration

• Digital filtering and timed event processing

• 7-bit addressing

• 100 kbps and 400 kbps data rates

• Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processor provides many channels of DMA and con­trols the extensive set of peripherals described in the previous
sections.

DMA Controller

The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe­cuting its program instructions. DMA transfers can occur
between the ADSP-2137x processor’s internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
ports, the IDP (input data port), the parallel data acquisition
port (PDAP), or the UART (see Table 7).

Table 7. DMA Channels

Peripheral ADSP-21371 ADSP-21375

SPORT 16 8
PDAP 8 8
SPI 2 2
UART 2 2
EP 2 2
MTM/DTCP 2 2
Total DMA Channels 32 24

Rev. C | Page 10 of 52 | September 2009

ADSP-21371/ADSP-21375

Delay Line DMA

The processors provide delay line DMA functionality. This
allows processor reads and writes to external delay line buffers
(and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The ADSP-2137x processor provides scatter/gather DMA func­tionality. This allows processor DMA reads/writes to/from non­contiguous memory blocks.

SYSTEM DESIGN

The following sections provide an introduction to system design
options and power supply issues. For complete system design
information, see the ADSP-2137x SHARC Processor Hardware
Reference.

Program Booting

The internal memory of the processor boots at system power-up
from an 8-bit EPROM via the external port, an SPI master, or an
SPI slave. Booting is determined by the boot configuration
(BOOT_CFG1–0) pins in Table 8. Selection of the boot source
is controlled via the SPI as either a master or slave device, or it
can immediately begin executing from ROM.

Table 8. Boot Mode Selection

BOOT_CFG1–0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 EPROM/FLASH Boot
11 Reserved

The “Running Reset” feature allows programs to perform a reset
of the processor core and peripherals, but without resetting the
PLL and SDRAM controller, or performing a boot. The
RESETOUT

Power Supplies

The processors have separate power supply connections for the
internal (V
internal supplies must meet the 1.2 V requirement. The external
supply must meet the 3.3 V requirement. All external supply
pins must be connected to the same power supply.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the processor to moni­tor and control the target board processor during emulation.
Analog Devices DSP Tools product line of JTAG emulators pro­vides emulation at full processor speed, allowing inspection and
modification of memory, registers, and processor stacks. The
processor’s JTAG interface ensures that the emulator will not
affect target system loading
or timing.

For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate “Emulator Hardware User’s Guide”.

pin acts as the input for initiating a running reset.

), and external (V

DDINT

) power supplies. The

DDEXT

DEVELOPMENT TOOLS

The processors are supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21371/ADSP-21375.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC pro­cessor has architectural features that improve the efficiency of
compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel­opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and
generate outputs

®

software and hardware development tools,

®

devel-

Rev. C | Page 11 of 52 | September 2009

ADSP-21371/ADSP-21375

• Maintain a one-to-one correspondence with the tool’s
command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre­emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi­nition File (LDF), allowing the developer to move between the
graphical and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family.
Hardware tools include SHARC processor PC plug-in cards.
Third party software tools include DSP libraries, real-time oper­ating systems, and block diagram design tools.

JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite® evaluation plat­forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standal­one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high speed, non­intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the processor’s
architecture and functionality. For detailed information on the
core architecture and instruction set, refer to the ADSP-2137x
SHARC Processor Hardware Reference.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in­circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com­mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter­mination, and emulator pod logic, see the EE-68: Analog Devices

Rev. C | Page 12 of 52 | September 2009

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 9:
A = asynchronous, I = input, O = output, S = synchronous,
(A/D) = active drive, (O/D) = open drain, and T = three-state,
(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 9. Pin Descriptions

State During
and After

Name Type

Reset Description

ADSP-21371/ADSP-21375

ADDR

DATA

DAI _P

DPI _P

23–0

31–0

20–1

14–1

O/T (pu) Pulled high/

driven low

I/O (pu) Pulled high/

pulled high

I/O with
programmable

1

(pu)

I/O with
programmable

1

(pu)

Pulled high/
pulled high

Pulled high/
pulled high

External Address.

erals on these pins.

External Data.

interface data (I/O), the PDAP (I) (PDAP for ADSP-21371), FLAGS (I/O) and PWM (O). After
reset, all DATA pins are in EMIF mode and FLAG(0–3) pins are in FLAGS mode (default).
When configured in the IDP_PDAP_CTL register, IDP channel 0 scans the external port
data pins for parallel input data. PDAP over 16-bit external port DATA is not supported
on the ADSP-21375 processor.

Digital Applications Interface Pins

DAI SRU. The DAI SRU configuration registers define the combination of on-chip audio­centric peripheral inputs or outputs connected to the pin and to the pin’s output enable.
The configuration registers of these peripherals then determine the exact behavior of
the pin. Any input or output signal present in th e DA I SR U may be r ou ted to a ny of t hes e
pins. The DAI SRU provides the connection from the serial ports, the S/PDIF module
(ADSP-21371), IDP (2), and the PCGs (4), to the DAI_P20–1 pins. Pullups can be disabled
via the DAI_PIN_PULLUP register.

Digital Peripheral Interface.

The DPI SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the DPI SRU may be routed to any of these pins. The DPI SRU
provides the connection from the timers (2), SPIs (2), UART (1), flags (12), and general­purpose I/O (9) to the DPI_P14–1 pins. Pull-ups can be disabled via the DPI_PIN_PULLUP
register.

The processor outputs addresses for external memory and periph-

The data pins can be multiplexed to support the external memory

. These pins provide the physical interface to the

These pins provide the physical interface to the DPI SRU.

ACK I (pu)

RD

WR

SDRAS

SDCAS

SDWE

O/T (pu) Pulled high/

O/T (pu) Pulled high/

O/T (pu) Pulled high/

O/T (pu) Pulled high/

O/T (pu) Pulled high/

driven high

driven high

driven high

driven high

driven high

Memory Acknowledge.

an external memory access. ACK is used by I/O devices, memory controllers, or other
peripherals to hold off completion of an external memory access.

External Port Read Enable.

external memory. RD

External Port Write Enable.

external memory. WR

SDRAM Row Address Strobe.

SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Column Address Select.

other SDRAM command pins, defines the operation for the SDRAM to perform.

SDRAM Write Enable.

Rev. C | Page 13 of 52 | September 2009

External devices can deassert ACK (low) to add wait states to

RD is asserted whenever the processor reads a word from

has a 22.5 kΩ internal pull-up resistor.

WR is asserted when the processor writes a word to

has a 22.5 kΩ internal pull-up resistor.

Connect to SDRAM’s RAS pin. In conjunction with other

Connect to SDRAM’s WE or W buffer pin.

Connect to SDRAM's CAS pin. In conjunction with

ADSP-21371/ADSP-21375

Table 9. Pin Descriptions (Continued)

State During
and After

Name Type

Reset Description

SDCKE O/T (pu) Pulled high/

driven high

SDA10 O/T (pu) Pulled high/

driven low

SDCLK O/T High-Z/driving

MS

0–1

O/T (pu) Pulled high/

driven high

FLAG[0]/IRQ0 I/O FLAG[0] INPUT

FLAG[1]/IRQ1 I/O FLAG[1] INPUT

FLAG[2]/IRQ2/
MS2

I/O with
programmable pu

FLAG[2] INPUT

(for MS mode)

FLAG[3]/
TMREXP/ MS3

I/O with
programmable pu

FLAG[3] INPUT

(for MS mode)

TDI I (pu)

SDRAM Clock Enable.

Connect to SDRAM’s CKE pin. Enables and disables the CLK

signal. For details, see the data sheet supplied with the SDRAM device.

SDRAM A10 Pin.

Enables applications to refresh an SDRAM in parallel with a non-

SDRAM accesses. This pin replaces the DSP’s A10 pin only during SDRAM accesses.

SDRAM Clock.

Memory Select Lines 0–1.

sponding banks of external memory. The MS

These lines are asserted (low) as chip selects for the corre-

lines are decoded memory address lines

3-0

that change at the same time as the other address lines. When no external memory
access is occurring the MS

lines are inactive; they are active however when a condi-

3-0

tional memory access instruction is executed, whether or not the condition is true.

pin can be used in EPORT/FLASH boot mode. For more information, see the

The MS1

ADSP-2137x SHARC Processor Hardware Reference.

FLAG0/Interrupt Request0.

FLAG1/Interrupt Request1.

FLAG2/Interrupt Request/Memory Select2.

FLAG3/Timer Expired/Memory Select3.

Test Data Input (JTAG).

Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

TDO O/T

TMS I (pu)

TCK I

TRST

EMU

CLK_CFG

BOOT_CFG

1–0

1–0

I (pu)

O/T (pu)

I

I

Test Data Output (JTAG).

Test Mode Select (JTAG).

Serial scan output of the boundary scan path.

Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Test Clock (JTAG).

Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processor.

Test Reset (JTAG).

Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor. TRST
internal pull-up resistor.

Emulation Status.

Must be connected to the processor. Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU
pull-up resistor.

Core to CLKIN Ratio Control.

These pins set the start up clock frequency. See the

ADSP-2137x SHARC Processor Hardware Reference

ration modes.
Note that the operating frequency can be changed by programming the PLL multiplier

and divider in the PMCTL register at any time after the core comes out of reset.

Boot Configuration Select.

These pins select the boot mode for the processor. The

BOOT_CFG pins must be valid before reset is asserted. See the

Processor Hardware Reference

Rev. C | Page 14 of 52 | September 2009

for information about boot modes.

has a 22.5 kΩ

has a 22.5 kΩ internal

for a description of the clock configu-

ADSP-2137x SHARC

Table 9. Pin Descriptions (Continued)

Name Type

ADSP-21371/ADSP-21375

State During
and After
Reset Description

RESET I

XTAL O

CLKIN I

RESETOUT
RUNRSTIN

1

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

/

I/O (pu)

Processor Reset.

4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program
execution from the hardware reset vector address. The RESET
(low) at power-up.

Crystal Oscillator Terminal.

Local Clock In.

configures the processor to use either its internal clock generator or an external clock
source. Connecting the necessary components to CLKIN and XTAL enables the internal
clock generator. Connecting the external clock to CLKIN while leaving XTAL uncon­nected configures the processor to use the external clock source such as an external
clock oscillator. CLKIN may not be halted, changed, or operated below the specified
frequency.

Reset Out/Running Reset In.

function as RUNRSTIN, which is enabled by setting bit 0 of the RUNRSTCTL register. For
more information, see the

Resets the processor to a known state. Upon deassertion, there is a

input must be asserted

Used in conjunction with CLKIN to drive an external crystal.

Used in conjunction with XTAL. CLKIN is the processor clock input. It

The default setting is reset out. This pin also has a second

ADSP-2137x SHARC Processor Hardware Reference

.

Rev. C | Page 15 of 52 | September 2009

ADSP-21371/ADSP-21375

ADSP-21371/ADSP-21375 SPECIFICATIONS

OPERATING CONDITIONS

1.0 V, 200 MHz 1.2 V, 266 MHz

Parameter

V

DDINT

V

DDEXT

2

V

IH

2

V

IL

V

IH_CLKIN

V

IL_CLKIN

T

JUNCTION

T

AMBIENT

1

Specifications subject to change without notice.

2

Applies to input and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), FLAG3–0, DAI_Px, DPI_Px, SPIDS, BOOT_CFGx, CLKCFGx, RUNRSTIN ,

RESET, TCK, TMS, TDI, TRST.

3

Applies to input pin CLKIN.

ELECTRICAL CHARACTERISTICS

1

Description

Internal (Core) Supply Voltage 0.95 1.05 1.14 1.26 V
External (I/O) Supply Voltage 3.13 3.47 3.13 3.47 V
High Level Input Voltage @ V

Low Level Input Voltage @ V

3

High Level Input Voltage @ V

3

Low Level Input Voltage @ V
Junction Temperature 208-Lead LQFP_EP @ T
Ambient Temperature 208-Lead LQFP_EP @ T

= max 2.0 V

DDEXT

= min –0.5 +0.8 –0.5 +0.8 V

DDEXT

= max 1.74 V

DDEXT

= min –0.5 +1.10 –0.5 +1.10 V

DDEXT

0ºC to +70ºC 0 115 0 115 ºC

AMBIENT

0ºC to +70ºC –40 105 –40 105 ºC

AMBIENT

+ 0.5 2.0 V

DDEXT

+ 0.5 1.74 V

DDEXT

DDEXT

DDEXT

UnitMin Max Min Max

+ 0.5 V

+ 0.5 V

1.0 V, 200 MHz 1.2 V, 266 MHz

Parameter

V

OH

2

V

OL

4, 5

I

IH

4

I

IL

I

ILPU

1

Description Test Conditions Min Typ Max Min Typ Max Unit

2

5

High Level Output Voltage @ V
Low Level Output Voltage @ V
High Level Input Current @ V
Low Level Input Current @ V
Low Level Input Current

@ V

= min, IOH = –1.0 mA

DDEXT

= min, IOL = 1.0 mA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 10 μA

DDEXT

= max, VIN = 0 V 200 200 μA

DDEXT

3

3

max 10 10 μA

DDEXT

2.4 2.4 V

0.4 0.4 V

Pull-up

I

OZH

I

OZL

I

OZLPU

6, 7

6

7

Three-State Leakage Current @ V
Three-State Leakage Current @ V
Three-State Leakage Current

@ V

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 10 μA

DDEXT

= max, VIN = 0 V 200 200 μA

DDEXT

max 10 10 μA

DDEXT

Pull-up

8, 9

I

DD-INTYP

10, 11

C

IN

1

Specifications subject to change without notice.

2

Applies to output and bidirectional pins: ADDR23–0, DATA31–0 (DATA15–0 on ADSP-21375), RD, WR, FLAG3–0, DAI_Px, DPI_Px, EMU, TDO, SDRAS, SDCAS, SDWE,

SDCKE, SDA10, and SDCLK.

3

See Output Drive Currents on Page 45 for typical drive current capabilities.

4

Applies to input pins: BOOT_CFGx, CLKCFGx, TCK, RESET, CLKIN.

5

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

6

Applies to three-statable pins: FLAG3–0.

7

Applies to three-statable pins with 22.5 kΩ pull-ups: DAI_Px, DPI_Px, EMU.

8

Typical internal current data reflects nominal operating conditions.

9

See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2137x SHARC Processors” (EE-318) for further information.

10

Applies to all signal pins.

11

Guaranteed, but not tested.

Supply Current (Internal) 1.0V, 200 MHz: t

V

= 1.0 V, 25ºC

DDINT

1.2V, 266 MHz: t
V

= 1.2 V, 25ºC

DDINT

Input Capacitance fIN = 1 MHz, T

CASE

= 5.00 ns,

CCLK

= 3.75 ns,

CCLK

400

600

mA

mA

= 25°C, VIN= 1.2 V 4.7 4.7 pF

Rev. C | Page 16 of 52 | September 2009