Analog Devices ADSP 21368 pra Datasheet

a

SHARC® Processor

JTAG TEST & EMULATION

Preliminary Technical Data

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance automotive audio
processing

Audio decoder and post processor-algorithm support with

32-bit floating-point implementations
Non-volatile memory may be configured to support audio

decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, Dolby Digital Plus, Dolby
headphone, DTS 96/24, Neo:6, DTS ES, DTS Lossless,
MPEG2 AAC, MPEG2 2channel, MP3, WMAPro, and Multi­channel encoder. Functions like Bass management, Delay,
Speaker equalization, Graphic equalization, Decoder/post­processor algorithm combination support will vary
depending upon the chip version and the system configu­rations. Please visit www.analog.com

COREPROCESSOR

INSTRUCTION

CACHE

32 X48-BIT

PROGRAM

SEQU ENCER

DAG1

8X4 X32

DAG2

8X 4X32

TIMER

Single-Instruction Multiple-Data (SIMD) computational

architecture

On-chip memory—2M bit of on-chip SRAM and a dedicated

6M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21368 is available with a 400 MHz core instruction

rate with unique audio centric peripherals such as the Digi-

tal Audio Interface, S/PDIF transceiver, serial ports, 8-

channel asynchronous sample rate converter, precision

clock generators and more. For complete ordering infor-

mation, see Ordering Guide on page 46

4BLOCKSOF

ON-CHIPMEMORY

2 M BI T R AM , 6 M BI T RO M

ADDR DATA

EXTERNAL PORT

SDRAM

CONTROLLER

ASYNCHRONOUS

ME MO RY

INTERFACE

MULTIPROCESSOR

INTERFACE

ADSP-21368

S
N

I
P

L
O
R
T
N
O
C

24

ADDRESS

18

CONTROL

32

DATA

8

3

7

PROCES SIN G

EL EMEN T

(P EX)

4

GPI O FLA GS/

PWM (16)

IRQ/TIMEXP

PROC ESSI NG

ELEMENT

S

(P EY)

P X REG IST ER

PRECI SION C LOCK

GENERATORS (4)

SRC (8 CHANNELS)

SPDIF (RX/TX)

DIGITALAUDIO INTERFACE

DAI ROUTING UNIT

SERIAL PORTS (8)

INPUT DATAPORT/

Figure 1. Functional Block Diagram – Processor Core

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

IOA(24)

IOP REGISTER (MEMORY MAPPED)

CONTROL, STATUS, & DATA BUFFERS

PDAP

DAI P IN S

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:[phone] www.analog.com
Fax:[phone] © 2004 Analog Devices, Inc. All rights reserved.

IOD(32)

SPI PORT (2)

TWO WIRE

INTERFACE

32 PM ADDRE SS BUS

D PI ROU T I NG UNI T

32
64

64

ME M ORY D M A (2 )

DMA

CONTROLLER

34CHANNELS

DPI PINS

DI GI T AL PER IP HE RA L I NTE RF A CE

14

I/O PROCESSOR

DMADDRESS BUS
PM DATA BUS
DM DATA BUS

ME M ORY -T O-

UART (2)

TIMERS (3)

ADSP-21368 Preliminary Technical Data

KEY FEATURES – PROCESSOR CORE

At 400 MHz (2.5 ns) core instruction rate, the ADSP-21368

performs 2.4 GFLOPS/800 MMACS

2M bit on-chip SRAM (0.75M Bit in blocks 0 and 1, and 250K

Bit in blocks 2 and 3) for simultaneous access by the core
processor and DMA

6M bit on-chip mask-programmable ROM (3M bit in block 0

and 3M bit in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at

the assembly level

Parallelism in busses and computational units allows: Sin-

gle cycle executions (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch

Transfers between memory and core at a sustained 6.0G

bytes/s bandwidth at 400 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA Controller supports:

34 zero-overhead DMA channels for transfers between

ADSP-21368 internal memory and a variety of
peripherals

32-bit DMA transfers at core clock speed, in parallel with

full-speed processor execution

32-Bit Wide External Port Provides Glueless Connection to

both Synchronous (SDRAM) and Asynchronous Memory
Devices

Programmable wait state options: 2 to 31 SCLK cycles
Delay-line DMA engine maintains circular buffers in exter-

nal memory with tap/offset based reads

SDRAM accesses at 166MHz and Asynchronous accesses at

66MHz

Shared-memory support allows multiple DSPs to automat-

ically arbitrate for the bus and gluelessly access a
common memory device

Multiprocessing Support Provides:

Glueless Connection for Scalable DSP Multiprocessing
Architecture

Distributed On-Chip Bus Arbitration for Parallel Bus

Connect of Up to Four ADSP-21368s and Global Memory

4 Memory Select lines allows multiple external memory

devices

Digital Audio Interface (DAI) includes eight serial ports, four

Precision Clock Generators, an Input Data Port, an S/PDIF
transceiver, an 8-channel asynchronous sample rate con­verter, and a Signal Routing Unit

Digital Peripheral Interface (DPI) includes, three timers, two

UARTs, two SPI ports, and a two wire interface port
Outputs of PCG's C and D can be driven on to DPI pins

Eight dual data line serial ports that operate at up to 50M

bits/s on each data line — each has a clock, frame sync and
two data lines that can be configured as either a receiver or
transmitter pair

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces
such as H.100/H.110

Up to 16 TDM stream support, each with 128 channels per

frame
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data

or seven channels of serial data and a single channel of up

to a 20-bit wide parallel data
Signal routing unit provides configurable and flexible con-

nections between all DAI/DPI components
2 Muxed Flag/IRQ
1 Muxed Flag/Timer expired line /MS
1 Muxed Flag/IRQ

lines

pin

/MS pin

DEDICATED AUDIO COMPONENTS

S/PDIF Compatible Digital Audio receiver/transmitter sup-

ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I

16, 18, 20 or 24-bit word widths (transmitter)
Sample Rate Converter (SRC) contains a Serial Input Port, De-

emphasis Filter, Sample Rate Converter (SRC) and Serial

Output Port providing up to -128db SNR performance.

Supports Left Justified, I2S, TDM and Right Justified 24, 20,

18 and 16-bit serial formats (input)
Pulse Width Modulation provides:

16 PWM outputs configured as four groups of four outputs

supports center-aligned or edge-aligned PWM waveforms
ROM Based Security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios
Dual voltage: 3.3 V I/O, 1.3 V core
Available in 256-ball BGA Package (see Ordering Guide on

page 46)

2

S or right-justified serial data input with

Rev. PrA | Page 2 of 48 | November 2004

TABLE OF CONTENTS

ADSP-21368Preliminary Technical Data

Summary ............................................................... 1

Key Features – Processor Core ................................. 2

Input/Output Features ........................................... 2

Dedicated Audio Components ................................. 2

General Description ................................................. 4

ADSP-21367 Family Core Architecture ...................... 4

SIMD Computational Engine ............................... 4

Independent, Parallel Computation Units ................ 4

Data Register File ............................................... 5

Single-Cycle Fetch of Instruction and Four Operands . 5

Instruction Cache .............................................. 5

Data Address Generators With Zero-Overhead Hardware

Circular Buffer Support .................................... 5

Flexible Instruction Set ....................................... 6

ADSP-21367 Memory ............................................ 6

On-Chip Memory .............................................. 6

External Memory .................................................. 6

SDRAM Controller ............................................ 7

Asynchronous Controller .................................... 7

ADSP-21367 Input/Output Features .......................... 7

DMA Controller ................................................ 7

Digital Audio Interface (DAI) ............................... 7

Serial Ports ....................................................... 8

S/PDIF Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample

Rate Converter ............................................... 8

Digital Peripheral Interface (DPI) .......................... 8

Serial Peripheral (Compatible) Interface .................. 8

UART Port ...................................................... 8

Timers ............................................................ 9

Two Wire Interface Port (TWI) ............................. 9

Pulse Width Modulation ..................................... 9

ROM Based Security ........................................... 9

System Design ...................................................... 9

Program Booting .............................................. 10

Power Supplies ................................................. 10

Target Board JTAG Emulator Connector ................ 10

Development Tools .............................................. 10

Designing an Emulator-Compatible DSP

Board(Target) .............................................. 11

Evaluation Kit .................................................. 11

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Modes ............................................ 14

Boot Modes ....................................................... 14

Core Instruction Rate to CLKIN Ratio Modes ............ 14

ADSP-21367 Specifications ....................................... 15

Recommended Operating Conditions ...................... 15

Electrical Characteristics ....................................... 15

Absolute Maximum Ratings ................................... 16

ESD Sensitivity ................................................... 16

Timing Specifications ........................................... 16

Power-Up Sequencing ....................................... 18

Clock Input .................................................... 19

Clock Signals ................................................... 19

Reset ............................................................. 20

Interrupts ....................................................... 20

Core Timer ..................................................... 21

Timer PWM_OUT Cycle Timing ......................... 21

Timer WDTH_CAP Timing ............................... 22

DAI and DPI Pin to Pin Direct Routing ................. 22

Precision Clock Generator (Direct Pin Routing) ...... 23

Flags ............................................................. 24

SDRAM Interface Timing .................................. 25

External Port Bus Request and Grant Cycle Timing .. 26

Serial Ports ..................................................... 27

Input Data Port ............................................... 30

Parallel Data Acquisition Port (PDAP) .................. 31

Sample Rate Converter—Serial Input Port .............. 32

Sample Rate Converter—Serial Output Port ........... 33

SPDIF Transmitter ........................................... 34

SPDIF Receiver ................................................ 36

SPI Interface—Master ....................................... 38

SPI Interface—Slave .......................................... 39

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit Timing ...... 40

JTAG Test Access Port and Emulation .................. 41

Output Drive Currents ......................................... 42

Test Conditions .................................................. 42

Capacitive Loading .............................................. 42

Thermal Characteristics ........................................ 43

Ordering Guide ..................................................... 45

Rev. PrA | Page 3 of 48 | November 2004

ADSP-21368 Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-21368 SHARC processor is a members of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Har­vard Architecture. The ADSP-21368 is source code compatible
with the ADSP-2126x, and ADSP-2116x, DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin­gle-Instruction, Single-Data) mode. The ADSP-21368 is a 32­bit/40-bit floating point processors optimized for high perfor­mance automotive audio applications with its large on-chip
SRAM and mask-programmable ROM, multiple internal buses
to eliminate I/O bottlenecks, and an innovative Digital Audio
Interface (DAI).

As shown in the functional block diagram on page 1, the
ADSP-21368 uses two computational units to deliver a signifi­cant performance increase over the previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21368 processor achieves
an instruction cycle time of 2.5 ns at 400 MHz. With its SIMD
computational hardware, the ADSP-21368 can perform 2.4
GFLOPS running at 400 MHz.

Table 1 shows performance benchmarks for the ADSP-21368.

Table 1. ADSP-21368 Benchmarks (at 400 MHz)

Benchmark Algorithm Speed

(at 400 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 23.25 µs
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)

[3x3] × [3x1]
[4x4] × [4x1]

Divide (y/×) 8.75 ns
Inverse Square Root 13.5 ns

1

Assumes two files in multichannel SIMD mode

1

1

1.25 ns

5.0 ns

11.25 ns

20.0 ns

The ADSP-21368 continues SHARC’s industry leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21368 on page 1, illustrates the
following architectural features:

• Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File

• Data Address Generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

• Three Programmable Interval Timers with PWM Genera­tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities

•On-Chip SRAM (2M bit)

• On-Chip mask-programmable ROM (6M bit)

• JTAG test access port

The block diagram of the ADSP-21368 on page 1 also illustrates
the following architectural features:

• DMA controller

• Eight full duplex serial ports

• Two SPI-compatible interface ports

• Digital Audio Interface that includes four precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, eight serial ports, eight serial interfaces, a
20-bit parallel input port, a flexible signal routing unit
(SRU), and a Digital Peripheral Interface (DPI)

ADSP-21368 FAMILY CORE ARCHITECTURE

The ADSP-21368 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The ADSP­21368 shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as detailed in the fol­lowing sections.

SIMD Computational Engine

The ADSP-21368 contains two computational processing ele­ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg­ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro­cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.

Entering SIMD mode also has an effect on the way data is trans­ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band­width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera­tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-

Rev. PrA | Page 4 of 48 | November 2004

ADSP-21368Preliminary Technical Data

ments. These computation units support IEEE 32-bit single­precision floating-point, 40-bit extended precision floating­point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro­cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har­vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21368 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 1 on page 1). With the ADSP-21368’s separate pro­gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin­gle cycle.

Instruction Cache

The ADSP-21368 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators With Zero-Overhead Hardware Circular Buffer Support

The ADSP-21368’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program­ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21368 contain

sufficient registers to allow the creation of up to 32 circular buff­ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over­head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21368 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch­ing up to four 32-bit values from memory—all in a single
instruction.

ADSP-21368 MEMORY

The ADSP-21368 adds the following architectural features to
the SIMD SHARC family core.

On-Chip Memory

The ADSP-21368 contains two megabits of internal RAM and
six megabits of internal mask-programmable ROM. Each block
can be configured for different combinations of code and data
storage (see Table 2). Each memory block supports single-cycle,
independent accesses by the core processor and I/O processor.
The ADSP-21368 memory architecture, in combination with its
separate on-chip buses, allow two data transfers from the core
and one from the I/O processor, in a single cycle.

The ADSP-21368’s, SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ­ent word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float­ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for­mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Table 2. ADSP-21368 Internal Memory Space

IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits) Extended Precision Normal or

Instruction Word (48 bits)

BLOCK 0 ROM
0x0004 0000–0x0004 BFFF

Reserved
0x0004 F000–0x0004 FFFF

BLOCK 0 RAM
0x0004 C000–0x0004 EFFF

BLOCK 1 ROM
0x0005 0000–0x0005 BFFF

BLOCK 0 ROM
0x0008 0000–0x0008 FFFF

Reserved
0x0009 4000–0x0009 FFFF

BLOCK 0 RAM
0x0009 0000–0x0009 3FFF

BLOCK 1 ROM
0x000A 0000–0x000A FFFF

Rev. PrA | Page 5 of 48 | November 2004

Normal Word (32 bits) Short Word (16 bits)

BLOCK 0 ROM
0x0008 0000–0x0009 7FFF

Reserved
0x0009 E0000–0x0009 FFFF

BLOCK 0 RAM
0x0009 8000–0x0009 DFFF

BLOCK 1 ROM
0x000A 0000– 0x000B 7FFF

BLOCK 0 ROM
0x0010 0000–0x0012 FFFF

Reserved
0x0013 C000–0x0013 FFFF

BLOCK 0 RAM
0x0013 0000–0x0013 BFFF

BLOCK 1 ROM
0x0014 0000–0x0016 FFFF

ADSP-21368 Preliminary Technical Data

Table 2. ADSP-21368 Internal Memory Space (Continued)

IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits) Extended Precision Normal or

Instruction Word (48 bits)

Reserved
0x0005 F000–0x0005 FFFF

BLOCK 1 RAM
0x0005 C000–0x0005 EFFF

BLOCK 2 RAM
0x0006 0000–0x0006 0FFF

Reserved
0x0006 1000– 0x0006 FFFF

BLOCK 3 RAM
0x0007 0000–0x0007 0FFF

Reserved
0x0007 1000– 0x0007 FFFF

Reserved
0x000B 4000–0x000B FFFF

BLOCK 1 RAM
0x000B 0000–0x000B 3FFF

BLOCK 2 RAM
0x000C 0000–0x000C 1554

Reserved
0x000C 1555–0x000C 3FFF

BLOCK 3 RAM
0x000E 0000–0x000E 1554

Reserved
0x000E 1555–0x000F FFFF

Normal Word (32 bits) Short Word (16 bits)

Reserved
0x000B E000– 0x000B FFFF

BLOCK 1 RAM
0x000B 8000–0x000B DFFF

BLOCK 2 RAM
0x000C 0000–0x000C 1FFF

Reserved
0x000C 2000–0x000D FFFF

BLOCK 3 RAM
0x000E 0000–0x000E 1FFF

Reserved
0x000E 2000–0x000F FFFF

Reserved
0x0017 C000–0x0017 FFFF

BLOCK 1 RAM
0x0017 0000–0x0017 BFFF

BLOCK 2 RAM
0x0018 0000–0x0018 3FFF

Reserved
0x0018 4000–0x001B FFFF

BLOCK 3 RAM
0x001C 0000–0x001C 3FFF

Reserved
0x001C 4000–0x001F FFFF

Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.

EXTERNAL MEMORY

The External Port on the ADSP-21368 SHARC provides a high
performance, glueless interface to a wide variety of industry­standard memory devices. The 32-bit wide bus may be used to
interface to synchronous and/or asynchronous memory devices
through the use of it's separate internal memory controllers: the
first is an SDRAM controller for connection of industry-stan­dard synchronous DRAM devices and DIMMs (Dual Inline
Memory Module), while the second is an asynchronous mem­ory controller intended to interface to a variety of memory
devices. Four memory select pins enable up to four separate
devices to coexist, supporting any desired combination of syn­chronous and asynchronous device types.

SDRAM Controller

The SDRAM controller provides an interface to up to four sepa­rate banks of industry-standard SDRAM devices or DIMMs, at
speeds up to f
each bank can has it's own memory select line (MS0
can be configured to contain between 16M bytes and
128M bytes of memory.

The controller maintains all of the banks as a contiguous
address space so that the processor sees this as a single address
space, even if different size devices are used in the different
banks.

A set of programmable timing parameters is available to config­ure the SDRAM banks to support slower memory devices. The
memory banks can be configured as either 32 bits wide for max­imum performance and bandwidth or 16 bits wide for
minimum device count and lower system cost.

. Fully compliant with the SDRAM standard,

SCLK

–MS3), and

The SDRAM controller address, data, clock, and command pins
can drive loads up to 30 pF. For larger memory systems, the
SDRAM controller external buffer timing should be selected
and external buffering should be provided so that the load on
the SDRAM controller pins does not exceed 30 pF.

Asynchronous Controller

The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif­ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, ROM, and flash EPROM,
as well as I/O devices that interface with standard memory con­trol lines. Bank0 occupies a 14.7M word window and banks 1, 2,
and 3 occupy a 16M word window in the processor’s address
space but, if not fully populated, these windows are not made
contiguous by the memory controller logic. The banks can also
be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of
interfacing to a range of memories and I/O devices tailored
either to high performance or to low cost and power.

The asynchronous memory controller is capable of a maximum
throughput of 267M bytes/sec using a 66MHz external bus
speed. Other features include 8 to 32-bit and 16 to 32-bit pack­ing and unpacking, booting from Bank Select 1, and support for
delay line DMA.

Shared External Memory

The ADSP-21368 supports connecting to common shared
external memory with other ADSP-21368s to create shared
external bus processor systems. This support includes:

• Distributed, on-chip arbitration for the shared external bus

• Fixed and rotating priority bus arbitration

• Bus time-out logic

• Bus lock

Rev. PrA | Page 6 of 48 | November 2004

ADSP-21368Preliminary Technical Data

Multiple processors can share the external bus with no addi­tional arbitration logic. Arbitration logic is included on-chip to
allow the connection of up to four processors.

Bus arbitration is accomplished through the BR1-4

signals and
the priority scheme for bus arbitration is determined by the set­ting of the RPBA pin. Table 3 on page 12 provides descriptions
of the pins used in multiprocessor systems.

ADSP-21368 INPUT/OUTPUT FEATURES

The ADSP-21368 I/O processor provides 34 channels of DMA,
as well as an extensive set of peripherals. These include a 20 pin
Digital Audio Interface which controls:

• Eight Serial ports

• S/PDIF Receiver/Transmitter

• Four Precision Clock generators

• Four Sample Rate Converters

• Internal Data port/Parallel Data Acquisition port

The ADSP-21368 processor also contains a 14 pin Digital
Peripheral Interface which controls:

• Three general-purpose timers

• Two Serial Peripheral Interfaces

•Two Universal Asynchronous Receiver/Transmitters
(UARTs)

2

• A Two Wire Interface/I

DMA Controller

The ADSP-21368’s on-chip DMA controller allows data trans­fers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta­neously executing its program instructions. DMA transfers can
occur between the ADSP-21368’s internal memory and its serial
ports, the SPI-compatible (Serial Peripheral Interface) ports, the
IDP (Input Data Port), the Parallel Data Acquisition Port
(PDAP) or the UART. Thirty-four channels of DMA are avail­able on the ADSP-21368—sixteen via the serial ports, eight via
the Input Data Port, four for the UARTs, two for the SPI inter­face, two for the external port, and two for memory-to-memory
transfers. Programs can be downloaded to the ADSP-21368
using DMA transfers. Other DMA features include interrupt
generation upon completion of DMA transfers, and DMA
chaining for automatic linked DMA transfers.

Delay Line DMA

The ADSP-21368 processor provides Delay Line DMA func­tionality. This allows processor reads and writes to external
Delay Line Buffers (and hence to external memory) with limited
core interaction.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con­nect various peripherals to any of the DSPs DAI pins
(DAI_P20–1).

C

Programs make these connections using the Signal Routing
Unit (SRU, shown in TBD).

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non con­figurable signal paths.

The DAI also includes eight serial ports, an S/PDIF
receiver/transmitter, four precision clock generators (PCG),
eight channels of synchronous sample rate converters, and an
input data port (IDP). The IDP provides an additional input
path to the ADSP-21368 core, configurable as either eight chan­nels of I

2

S serial data or as seven channels plus a single 20-bit
wide synchronous parallel data acquisition port. Each data
channel has its own DMA channel that is independent from the
ADSP-21368's serial ports.

For complete information on using the DAI, see the ADSP-
2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21368 features eight synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog devices AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has a dedicated DMA channel.

Serial ports are enabled via 16 programmable and simultaneous
receive or transmit pins that support up to 32 transmit or 32
receive channels of audio data when all eight SPORTS are
enabled, or eight full duplex TDM streams of 128 channels per
frame.

The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig­nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

2

•Multichannel (TDM) mode with support for Packed I

S

mode

2

•I

S mode

2

•Packed I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­ious attributes of this mode.

Rev. PrA | Page 7 of 48 | November 2004

ADSP-21368 Preliminary Technical Data

Each of the serial ports supports the left-justified sample pair

2

S protocols (I2S is an industry standard interface com-

and I
monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I
devices) per serial port, with a maximum of up to 32 I

2

S channels (using two stereo

2

S chan­nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I

2

S modes, data­word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter­nally or externally generated.

The serial ports also contain frame sync error detection logic
where the serial ports detect frame syncs that arrive early (for
example frame syncs that arrive while the transmission/recep­tion of the previous word is occurring). All the serial ports also
share one dedicated error interrupt.

S/PDIF Compatible Digital Audio Receiver/Transmitter and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left justified, I

2

S or right justified with word

widths of 16, 18, 20, or 24 bits.
The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the Signal Routing Unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.

The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
Asynchronous Sample Rate Converter and provides up to
128dB SNR. The SRC block is used to perform synchronous or
asynchronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con­vert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.

Digital Peripheral Interface (DPI)

The Digital Peripheral Interface provides connections to two
serial peripheral interface ports, two universal asynchronous
receiver-transmitters (UARTs), a Two Wire Interface (TWI), 12
Flags, and three general-purpose timers.

Serial Peripheral (Compatible) Interface

The ADSP-21368 SHARC processor contains two Serial Periph­eral Interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21368 SPI compati­ble port to communicate with other SPI compatible devices. The
SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup-

porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21368 SPI compatible peripheral implemen­tation also features programmable baud rate and clock phase
and polarities. The ADSP-21368 SPI compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.

UART Port

The ADSP-21368 processor provides a full-duplex Universal
Asynchronous Receiver/Transmitter (UART) port, which is
fully compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. The UART also has multiprocessor com­munication capability using 9-bit address detection. This allows
it to be used in multidrop networks through the RS-485 data
interface standard. The UART port also includes support for 5
to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. The
UART port supports two modes of operation:

• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.

• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen­eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f
(f

/16) bits per second.

SCLK

/ 1,048,576) to

SCLK

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

f

UART Clock Rate

----------------------------------- ----------------=
16 UART_Divisor×

SCLK

Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8bits).

In conjunction with the general-purpose timer functions, auto­baud detection is supported.

Rev. PrA | Page 8 of 48 | November 2004

ADSP-21368Preliminary Technical Data

Timers

The ADSP-21368 has a total of four timers: a core timer that can
generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be indepen­dently set to operate in one of three modes:

• Pulse Waveform Generation mode

• Pulse Width Count /Capture mode

• External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general purpose timer has one bidirec­tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin­gle control and status register enables or disables all three
general purpose timers independently.

Two Wire Interface Port (TWI)

The TWI is a bi-directional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I2C bus protocol.
The TWI Master incorporates the following features:

• Simultaneous Master and Slave operation on multiple
device systems with support for multi master data
arbitration

• Digital filtering and timed event processing

• 7 and 10 bit addressing

• 100K bits/s and 400K bits/s data rates

• Low interrupt rate

Pulse Width Modulation

The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave­forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non
paired mode (applicable to a single group of four PWM
waveforms).

The entire PWM module has four groups of four PWM outputs
each. Therefore, this module generates 16 PWM outputs in
total. Each PWM group produces two pairs of PWM signals on
the four PWM outputs.

The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period.
This results in PWM patterns that are symmetrical about the
mid-point of the PWM period. In double update mode, a sec­ond updating of the PWM registers is implemented at the mid­point of the PWM period. In this mode, it is possible to produce
asymmetrical PWM patterns that produce lower harmonic dis­tortion in three-phase PWM inverters.

ROM Based Security

The ADSP-21368 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
external code, executing exclusively from internal SRAM/ROM.
Additionally, the processor is not freely accessible via the JTAG
port. Instead, a unique 64-bit key, which must be scanned in
through the JTAG or Test Access Port will be assigned to each
customer. The device will ignore a wrong key. Emulation fea­tures and external boot modes are only available after the
correct key is scanned.

SYSTEM DESIGN

The following sections provide an introduction to system design
options and power supply issues.

Program Booting

The internal memory of the ADSP-21368 boots at system
power-up from an 8-bit EPROM via the external port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1–0) pins (see Table 4 on

page 14). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe­cuting from ROM.

Power Supplies

The ADSP-21368 has separate power supply connections for the
internal (V
power supplies. The internal and analog supplies must meet the

1.3V requirement. The external supply must meet the 3.3V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply (A
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A

VDD

an example circuit, see Figure 2. To prevent noise coupling, use
a wide trace for the analog ground (A
decoupling capacitor as close as possible to the pin. Note that

VSS

and A

the A
processor and not the analog ground plane on the board. For

more information, see Electrical Characteristics on page 15.

V

DDINT

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21368 pro­cessor to monitor and control the target board processor during

DDINT

), external (V

), and analog (A

DDEXT

) powers the ADSP-21368’s

VDD

VDD/AVSS

pin. Place the filter as close as possible to the pin. For

) signal and install a

VSS

pins specified in Figure 2 are inputs to the

VDD

10⍀

A

VDD

Figure 2. Analog Power (A

A

VSS

) Filter Circuit

VDD

0.01␮F0.1␮F

)

Rev. PrA | Page 9 of 48 | November 2004

ADSP-21368 Preliminary Technical Data

emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces­sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro­priate “Emulator Hardware User's Guide”.

DEVELOPMENT TOOLS

The ADSP-21368 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel­opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21368.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel­opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and
generate outputs

• Maintain a one-to-one correspondence with the tool’s
command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica­tions. Download components from the Web and drop them into
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi­nition File (LDF), allowing the developer to move between the
graphical and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard­ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

Rev. PrA | Page 10 of 48 | November 2004

ADSP-21368Preliminary Technical Data

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in­circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com­mands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter­mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat­forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board Flash device to store
user-specific boot code, enabling the board to run as a standal­one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, non­intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21368
architecture and functionality. For detailed information on the
ADSP-2136x Family core architecture and instruction set, refer
to the ADSP-2136x SHARC Processor Hardware Reference and
the ADSP-2136x SHARC Processor Programming Reference.

Rev. PrA | Page 11 of 48 | November 2004

ADSP-21368 Preliminary Technical Data

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of TBD:
A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pull-down
resistor, (pu) = pull-up resistor.

Table 3. Pin List

Name Type State During

and After
Reset

ADDR

DATA

23–0

31–0

I/O with programmable

1

PUP

I/O with programmable

Three-state

Three-state

PUP

DAI _P

DPI _P

20–1

14–1

I/O with programma-

2

PUP

ble

I/O with programma-

Three-state

Three-state

ble3 PUP

ACK Input with programma-

RD

1

ble PUP

I/O with programmable

1

PUP

Description

External Address Bus.

External Data Bus.

Digital Audio Interface Pins

. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin’s output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any
input or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gen­erators and timers, sample rate converters and SPI to the DAI_P20–1 pins These pins

Ω

have internal 22.5 k

pull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

Digital Peripheral Interface.

Memory Acknowledge.

External devices can deassert ACK (low) to add wait states
to an external memory access. ACK is used by I/O devices, memory controllers, or
other peripherals to hold off completion of an external memory access.

External Port Read Enable.

RD is asserted low whenever the processor reads 8-bit
or 16-bit data from an external memory device. When AD15–0 are flags, this pin
remains deasserted. RD

has a 22.5 kΩ internal pull-up resistor.

WR

SDRAS

SDCAS

SDWE

SDCKE Output with program-

SDA10 Output with program-

SDCLK

0–-1

Output with program­mable PUP

Output with program­mable PUP

Output with program­mable PUP

Output with program­mable PUP

mable PUP

mable PUP

1

1

1

1

1

1

I/O

External Port Write Enable.

WR is asserted low whenever the processor writes 8-bit
or 16-bit data to a n external memory devi ce. When AD15–0 are flags, this pin remains
deasserted. WR

has a 22.5 kΩ internal pull-up resistor.

SDRAM Row Address Strobe.

SDRAM column address select.

SDRAM Write Enable.

SDRAM Clock Enable.

SDRAM A10.

SDRAM Clock Configure.

Rev. PrA | Page 12 of 48 | November 2004

Connect to SDRAM’s WE or W buffer pin.

Connect to SDRAM’s CKE pin.

Connect to SDRAM’s RAS pin.

Connect to SDRAM’s CAS pin.

Table 3. Pin List

ADSP-21368Preliminary Technical Data

Name Type State During

and After
Reset

MS

0–1

FLAG[0]/IRQ0

I/O with programmable

1

PUP

I/O

FLAG[1]/IRQ1 I/O

FLAG[2]/IRQ2/
MS2

I/O with
programmable1 pull­up (for MS mode)

FLAG[3]/TIMEX
P/MS3

I/O with
programmable

1

pull-

up (for MS mode)

TDI Input with pull-up

TDO Output

Description

Memory Select Lines 0–1.

These lines are asserted (low) as chip selects for the cor­responding banks of external memory. Memory bank size must be defined in the
ADSP-21062’s system control register (SYSCON). The MS

lines are decoded memory

3-0

address lines that change at the same time as the other address lines. When no
external memory access is occurring the MS3-0 lines are inactive; they are active
however when a conditional memory access instruction is executed, whether or not
the condition is true. In a multiprocessing system the MS

lines are output by the

3-0

bus master.

FLAG0/Interrupt Request 0.

FLAG1/Interrupt Request 1.

FLAG2/Interrupt Request/Memory Select 2.

FLAG3/Timer Expired/Memory Select 3.

Test Data Input (JTAG).

Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Test Data Output (JTAG).

Serial scan output of the boundary scan path.

TMS Input with pull-up

TCK Input

TRST

EMU

CLK_CFG

BOOT_CFG

RESET

1–0

Input with pull-up

Output with pull-up

Input

Input

1–0

Input

XTAL Output

Test Mode Se lec t ( JTAG).

Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Test Clock ( JTAG).

Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the ADSP-21368.

Te st Re se t (J TAG ).

after power-up or held low for proper operation of the ADSP-21368. TRST

Ω

internal pull-up resistor.

k

Emulation Status.

product line of JTAG emulators target board connector only. EMU

Resets the test state machine. TRST must be asserted (pulsed low)

has a 22.5

Must be connected to the ADSP-21368 Analog Devices DSP Tools

has a 22.5 kΩ

internal pull-up resistor.

Core/CLKIN Ratio Control.

These pins set the start up clock frequency. See Table5

for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi­plier and divider in the PMCTL register at any time after the core comes out of reset.

Boot Configuration Select.

This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See Tab le 4 for a description
of the boot modes.

Processor Reset.

Resets the ADSP-21368 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program exe cution from the ha rdware reset vecto r address. The RES ET

input must be

asserted (low) at power-up.

Crystal Oscillator Terminal.

Used in conjunction with CLKIN to drive an external

crystal.

Rev. PrA | Page 13 of 48 | November 2004

ADSP-21368 Preliminary Technical Data

Table 3. Pin List

Name Type State During

and After
Reset

CLKIN

CLKOUT Output

BR

ID

4–1

2–0

Input/Output

Description

Local Clock In.

Used in conjunction with XTAL. CLKIN is the ADSP-21368 clock input.
It configures the ADSP-21368 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21368 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.

Local Clock O ut.

CL KOUT c an als o be c onf igur ed as a reset out pin.The functionality
can be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTREG register. The default is reset out.

External Bus Request.

Used by processors to arbitrate for bus mastership. A
processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs)
and monitors all others. In a system with less than four processors, the unused BRx
pins should be tied high; the processor's own BRx line must not be tied high or low
because it is an output.

Processor ID.

Determines which bus request (BR1-BR4) is used by the processor.
ID=001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or
001 in single-processor systems. These lines are a system configuration selection that
should be hardwired or only changed at reset. ID=101,110 and 111 are reserved.

RPBA Output

Rotating Priority Bus Arbitration Select.

external bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection which must be set to the same value on
every DSP. If the value of RPBA is changed during system operation, it must be
changed in the same CLKIN cycle on every DSP.

1

Pull-up is always enabled for ID - 000 in uniprocessor mode and ID- 001 in Multiprocessing mode.

2

Pull-up can be enabled/disabled, value of pull-up cannot be programmed.

3

OP is three-statable

ADDRESS/DATA MODES

TBD

BOOT MODES

Table 4. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot
01 SPI Master Boot
10 AMI boot via EPROM

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 3 on page 17.

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1
01 32:1
10 16:1

When RPBA is high, rotating priority for

Rev. PrA | Page 14 of 48 | November 2004

ADSP-21368 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ADSP-21368Preliminary Technical Data

K Grade

Parameter

V

DDINT

A

VDD

V

DDEXT

2

V

IH

2

V

IL

V

IH_CLKIN

V

IL_CLKIN

T

AMB

1

Specifications subject to change without notice.

2

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

3

Applies to input pin CLKIN.

4

See Thermal Characteristics on page 43 for information on thermal specifications.

5

See Engineer-to-Engineer Note (No. TBD) for further information.

1

Internal (Core) Supply Voltage 1.235 1.365 V

Analog (PLL) Supply Voltage 1.235 1.365 V

External (I/O) Supply Voltage 3.13 3.47 V

High Level Input Voltage @ V

Low Level Input Voltage @ V

3

High Level Input Voltage @ V

Low Level Input Voltage @ V

4, 5

Ambient Operating Temperature 0 +70 °C

= max 2.0 V

DDEXT

= min –0.5 +0.8 V

DDEXT

= max 1.74 V

DDEXT

= min –0.5 +1.19 V

DDEXT

Min Max Unit

+ 0.5 V

DDEXT

+ 0.5 V

DDEXT

ELECTRICAL CHARACTERISTICS

2

2

5

6, 7

6

1

High Level Output Voltage @ V
Low Level Output Voltage @ V
High Level Input Current @ V
Low Level Input Current @ V
Low Level Input Current Pull-up @ V
Three-State Leakage Current @ V
Three-State Leakage Current @ V

7

8, 9

10

Three-State Leakage Current Pull-up @ V
Supply Current (Internal) t
Supply Current (Analog) A
Input Capacitance fIN=1 MHz, T

Test Conditions Min Max Unit

= min, IOH = –1.0 mA

DDEXT

= min, IOL = 1.0 mA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= max, VIN = V

DDEXT

= max, VIN = 0 V 10 µA

DDEXT

= max, VIN = 0 V 200 µA

DDEXT

= 5.0 ns, V

CCLK

= max 10 mA

VDD

= 1.3 500 mA

DDINT

=25°C, VIN=1.3V 4.7 pF

CASE

3

3

max 10 µA

DDEXT

max 10 µA

DDEXT

2.4 V

0.4 V

Parameter

V

OH

V

OL

4, 5

I

IH

4

I

IL

I

ILPU

I

OZH

I

OZL

I

OZLPU

I

DD-INTYP

AI

DD

11, 12

C

IN

1

Specifications subject to change without notice.

2

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

3

See Output Drive Currents on page 42 for typical drive current capabilities.

4

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

5

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

6

Applies to three-statable pins: FLAG3–0.

7

Applies to three-statable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.

8

Typical internal current data reflects nominal operating conditions.

9

See Engineer-to-Engineer Note (No. TBD) for further information.

10

Characterized, but not tested.

11

Applies to all signal pins.

12

Guaranteed, but not tested.

Rev. PrA | Page 15 of 48 | November 2004