Analog Devices ADSP-21065L c Datasheet
a
DSP Microcomputer
ADSP-21065L
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC
®
)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
2
S Support, for Eight Simultaneous Receive and Trans-
I
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
CORE PROCESSOR
INSTRUCTION
CACHE
32 ⴛ 48 BIT
ADDR
DAG1
8 ⴛ 4 ⴛ 32
DAG2
8 ⴛ 4 ⴛ 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
32
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT I/O PORT
ADDR
DATA DATA
DATA
ADDR
IOA
17
ADDR
DATA
IOD
48
BLOCK 0
BLOCK 1
JTAG
TEST &
EMULATION
EXTERNAL
PORT
SDRAM
INTERFACE
ADDR BUS
MUX
7
24
PM DATA BUS
DATA
FILE
48
40
DM DATA BUS
BARREL
SHIFTER
ALUMULTIPLIER
BUS
CONNECT
(PX)
REGISTER
16 ⴛ 40 BIT
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
MULTIPROCESSOR
INTERFACE
32
S)
S)
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
DMA
CONTROLLER
SPORT 0
SPORT 1
DATA BUS
MUX
HOST PORT
4
(2 Rx, 2Tx)
2
(I
(2 Rx, 2Tx)
2
(I
I/O PROCESSOR
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADSP-21065L
544 Kbits Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable in Combinations of 16-, 32-, 48-Bit Data and
Program Words in Block 0 and Block 1
DMA Controller
Ten DMA Channels—Two Dedicated to the External Port
and Eight Dedicated to the Serial Ports
Background DMA Transfers at up to 66 MHz, in Parallel
with Full Speed Processor Execution
Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices
Host Processor Interface
Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21065L IOP Registers
Multiprocessing
Distributed On-Chip Bus Arbitration for Glueless, Parallel
Bus Connect Between Two ADSP-21065Ls Plus Host
132 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Independent Transmit and Receive Functions
Programmable 3-Bit to 32-Bit Serial Word Width
I2S Support Allowing Eight Transmit and Eight Receive
Channels
Glueless Interface to Industry Standard Codecs
TDM Multichannel Mode with -Law/A-Law Hardware
Companding
Multichannel Signaling Protocol
–2–
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ADSP-21065L
GENERAL DESCRIPTION
The ADSP-21065L is a powerful member of the SHARC
family of 32-bit processors optimized for cost sensitive applications. The SHARC—Super Harvard Architecture—offers the
highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSP in the
industry that offer both fixed and floating-point capabilities,
without compromising precision or performance.
The ADSP-21065L is fabricated in a high speed, low power
CMOS process, 0.35 mm technology. With its on-chip instruction cache, the processor can execute every instruction in a
single cycle. Table I lists the performance benchmarks for the
ADSP-21065L.
The ADSP-21065L SHARC combines a floating-point DSP
core with integrated, on-chip system features, including a
544 Kbit SRAM memory, host processor interface, DMA controller, SDRAM controller, and enhanced serial ports.
Figure 1 shows a block diagram of the ADSP-21065L, illustrating the following architectural features:
Computation Units (ALU, Multiplier, and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Timers with Event Capture Modes
On-Chip, dual-ported SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and SDRAM Interface
DMA Controller
Enhanced Serial Ports
JTAG Test Access Port
Table I. Performance Benchmarks
Benchmark Timing Cycles
Cycle Time 15.00 ns 1
1024-Pt. Complex FFT
(Radix 4, with Digit Reverse) 0.274 ns 18221
Matrix Multiply (Pipelined)
[3 ¥ 3] ¥ [3 ¥ 1] 135 ns 9
[4 ¥ 4] ¥ [4 ¥ 1] 240 ns 16
FIR Filter (per Tap) 15 ns 1
IIR Filter (per Biquad) 60 ns 4
Divide Y/X 90 ns 6
Inverse Square Root (1/÷x) 135 ns 9
DMA Transfers 264 Mbytes/sec.
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21065L is code and function compatible with the
ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L
includes the following architectural features of the SHARC
family core.
ADSP-21065L
CLOCK
RESET
01
CLKIN
RESET
ID
1-0
SPORT0
TX0_A
TX0_B
RX0_A
RX0_B
SPORT1
TX1_A
TX1_B
RX1_A
RX1_B
CONTROL
#1
ADDR
DATA
MS
SBTS
REDY
SDWE
SDCLK
SDCKE
SDA10
23-0
31-0
RD
WR
ACK
BMS
SW
CS
HBR
HBG
RAS
CAS
DQM
CPA
BR
BR
ADDRESS
CONTROL
3-0
1-0
2
1
DATA
CS
ADDR
DATA
HOST
PROCESSOR
(OPTIONAL)
CS
ADDR
DATA
ADDR
DATA
CS
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
BOOT
EPROM
(OPTIONAL)
SDRAM
Figure 2. ADSP-21065L Single-Processor System
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all
perform single-cycle instructions. The three units are arranged
in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier
operations. These computation units support IEEE 32-bit
single-precision floating-point, extended precision 40-bit floatingpoint, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21065L features an enhanced Super Harvard Architecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see Figure 1). With its separate program and data memory
buses, and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction Cache
The ADSP-21065L includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21065L’s two data address generators (DAGs)
implement circular data buffers in hardware. Circular buffers
allow efficient programming of delay lines and other data
REV. C
–3–
ADSP-21065L
structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The
ADSP-21065L’s two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register
sets, 16 secondary). The DAGs automatically handle address
pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can
start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP21065L can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21065L FEATURES
The ADSP-21065L is designed to achieve the highest system
throughput to enable maximum system performance. It can be
clocked by either a crystal or a TTL-compatible clock signal.
The ADSP-21065L uses an input clock with a frequency equal
to half the instruction rate—a 33 MHz input clock yields a
15 ns processor cycle (which is equivalent to 66 MHz). Interfaces on the ADSP-21065L operate as shown below. Hereafter
in this document, 1x = input clock frequency, and 2x = processor’s
instruction rate.
The following clock operation ratings are based on 1x = 33 MHz
(instruction rate/core = 66 MHz):
SDRAM 66 MHz
External SRAM 33 MHz
Serial Ports 33 MHz
Multiprocessing 33 MHz
Host (Asynchronous) 33 MHz
Augmenting the ADSP-21000 family core, the ADSP-21065L
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21065L contains 544 Kbits of on-chip SRAM,
organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has
256 Kbits. Bank 0 is configured with 9 columns of 2K ¥ 16 bits,
and Bank 1 is configured with 8 columns of 2K ¥ 16 bits. Each
memory block is dual-ported for single-cycle, independent accesses
by the core processor and I/O processor or DMA controller.
The dual-ported memory and separate on-chip buses allow two
data transfers from the core and one from I/O, all in a single
cycle (see Figure 4 for the ADSP-21065L Memory Map).
On the ADSP-21065L, the memory can be configured as a
maximum of 16K words of 32-bit data, 34K words for 16-bit
data, 10K words of 48-bit instructions (and 40-bit data) or
combinations of different word sizes up to 544 Kbits. All the
memory can be accessed as 16-bit, 32-bit or 48-bit.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM and PM busses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of
the data operands is transferred to or from off-chip, via the
ADSP-21065L’s external port.
Off-Chip Memory and Peripherals Interface
The ADSP-21065L’s external port provides the processor’s
interface to off-chip memory and peripherals. The 64M words,
off-chip address space is included in the ADSP-21065L’s
unified address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 24-bit
address bus, four memory selects, and a single 32-bit data bus.
The on-chip Super Harvard Architecture provides three bus
performance, while the off-chip unified address space gives
flexibility to the designer.
SDRAM Interface
The SDRAM interface enables the ADSP-21065L to transfer
data to and from synchronous DRAM (SDRAM) at 2x clock
frequency. The synchronous approach coupled with 2x clock
frequency supports data transfer at a high throughput—up to
220 Mbytes/sec.
The SDRAM interface provides a glueless interface with standard SDRAMs—16 Mb, 64 Mb, and 128 Mb—and includes
options to support additional buffers between the ADSP-21065L
and SDRAM. The SDRAM interface is extremely flexible and
provides capability for connecting SDRAMs to any one of the
ADSP-21065L’s four external memory banks.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21065L supports pipelining of the address and
control signals to enable such buffering between itself and
multiple SDRAM devices.
Host Processor Interface
The ADSP-21065L’s host interface provides easy connection to
standard microprocessor buses—8-, 16-, and 32-bit—requiring
little additional hardware. Supporting asynchronous transfers at
speeds up to 1x clock frequency, the host interface is accessed
through the ADSP-21065L’s external port. Two channels of
DMA are available for the host interface; code and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21065L’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
IOP registers of the ADSP-21065L and can access the DMA
channel setup and mailbox registers. Vector interrupt support
enables efficient execution of host commands.
DMA Controller
The ADSP-21065L’s on-chip DMA controller allows zerooverhead, nonintrusive data transfers without processor intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21065L’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21065L’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-, or
48-bit internal words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-21065L—
eight via the serial ports, and two via the processor’s external
port (for either host processor, other ADSP-21065L, memory or
–4–
REV. C
ADSP-21065L
I/O transfers). Programs can be downloaded to the ADSP-21065L
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR
generation on completion of DMA transfers and DMA chaining
for automatically linked DMA transfers.
Serial Ports
The ADSP-21065L features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
1x clock frequency, providing each with a maximum data rate of
33 Mbit/s. Each serial port has a primary and a secondary set of
transmit and receive channels. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports supports
three operation modes: DSP serial port mode, I
interface commonly used by audio codecs), and TDM (Time
Division Multiplex) multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with selectable word lengths of 3 bits to
32 bits. They offer selectable synchronization and transmit
modes and optional m-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
The serial ports also include keyword and keymask features to
enhance interprocessor communication.
Programmable Timers and General-Purpose I/O Ports
The ADSP-21065L has two independent timer blocks, each of
which performs two functions—Pulsewidth Generation and
Pulse Count and Capture.
In Pulsewidth Generation mode, the ADSP-21065L can generate a modulated waveform with an arbitrary pulsewidth within
a maximum period of 71.5 secs.
In Pulse Counter mode, the ADSP-21065L can measure either
the high or low pulsewidth and the period of an input waveform.
The ADSP-21065L also contains twelve programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program Booting
The internal memory of the ADSP-21065L can be booted at
system power-up from an 8-bit EPROM, a host processor, or
external memory. Selection of the boot source is controlled by
the BMS (Boot Memory Select) and BSEL (EPROM Boot)
pins. Either 8-, 16-, or 32-bit host processors can be used for
booting. For details, see the descriptions of the BMS and BSEL
pins in the Pin Descriptions section of this data sheet.
Multiprocessing
The ADSP-21065L offers powerful features tailored to multiprocessing DSP systems. The unified address space allows
direct interprocessor accesses of both ADSP-21065L’s IOP
registers. Distributed bus arbitration logic is included on-chip
for simple, glueless connection of systems containing a maximum
of two ADSP-21065Ls and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus lock allows
indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands.
Maximum throughput for interprocessor data transfer is
132 Mbytes/sec over the external port.
1-2,
DMAG
). Other DMA features include interrupt
1-2
2
S mode (an
DEVELOPMENT TOOLS
The ADSP-21065L is supported with a complete set of software
and hardware development tools, including the EZ-ICE
Circuit Emulator and development software.
The same EZ-ICE hardware that you use for the ADSP-21060/
ADSP-21062 also fully emulates the ADSP-21065L.
Both the SHARC Development Tools family and the VisualDSP
integrated project management and debugging environment
support the ADSP-21065L. The VisualDSP project management
environment enables you to develop and debug an application
from within a single integrated program.
The SHARC Development Tools include an easy to use Assembler that is based on an algebraic syntax; an Assembly library/
librarian; a linker; a loader; a cycle-accurate, instruction-level
simulator; a C compiler; and a C run-time library that includes
DSP and mathematical functions.
Debugging both C and Assembly programs with the Visual DSP
debugger, you can:
•
View Mixed C and Assembly Code
•
Insert Break Points
•
Set Watch Points
•
Trace Bus Activity
•
Profile Program Execution
•
Fill and Dump Memory
•
Create Custom Debugger Windows
The Visual IDE enables you to define and manage multiuser
projects. Its dialog boxes and property pages enable you to
configure and manage all of the SHARC Development Tools.
This capability enables you to:
•
Control how the development tools process inputs and generate outputs.
•
Maintain a one-to-one correspondence with the tool’s command line switches.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21065L processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hardware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
Additional Information
For detailed information on the ADSP-21065L instruction set
and architecture, see the ADSP-21065L SHARC User’s Manual,
Third Edition, and the ADSP-21065L SHARC Technical Reference.
EZ-ICE and VisualDSP are registered trademarks of Analog Devices, Inc.
SHARCPAC is a trademark of Analog Devices, Inc.
®
In-
®
REV. C
–5–
ADSP-21065L
ADSP-21065L
#2
CLKIN
RESET
ADDR
DATA
23-0
31-0
10
CLOCK
RESET
01
ID
1-0
CONTROL
SPORT0
SPORT1
ADSP-21065L
#1
CLKIN
RESET
ID
SPORT0
SPORT1
CONTROL
ADDR
1-0
DATA
SDCLK
CPA
BR
BR
23-0
31-0
RD
WR
ACK
MS
BMS
SBTS
SW
CS
HBR
HBG
REDY
RAS
CAS
DQM
SDWE
SDCKE
SDA10
CPA
BR
BR
2
1
CS
ADDR
DATA
ADDRESS
CONTROL
3-0
1-0
2
1
DATA
ADDR
DATA
CS
(OPTIONAL)
HOST
PROCESSOR
(OPTIONAL)
CS
ADDR
DATA
(OPTIONAL)
RAS
CAS
DQM
WE
CLK
CKE
A10
BOOT
EPROM
SDRAM
Figure 3. Multiprocessing System
–6–
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ADSP-21065L
PIN DESCRIPTIONS
ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN
(or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR
internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left floating. These pins have a logic-level hold circuit that prevents the input from floating internally.
I = Input S = Synchronous P = Power Supply (O/D) = Open Drain
O = Output A = Asynchronous G = Ground (A/D) = Active Drive
T = Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
Pin Type Function
ADDR
23-0
I/O/T External Bus Address. The ADSP-21065L outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/
writes of the IOP registers of the other ADSP-21065L. The ADSP-21065L inputs addresses
when a host processor or multiprocessing bus master is reading or writing its IOP registers.
DATA
31-0
I/O/T External Bus Data. The ADSP-21065L inputs and outputs data and instructions on these
pins. The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixedpoint data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. Pull-up
resistors on unused DATA pins are not necessary.
MS
3-0
I/O/T Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of
external memory. Internal ADDR
25-24
memory address lines that change at the same time as the other address lines. When no external
memory access is occurring the MS
3-0
tional memory access instruction is executed, whether or not the condition is true. Additionally,
an MS
line which is mapped to SDRAM may be asserted even when no SDRAM access is
3-0
active. In a multiprocessor system, the MS
RD I/O/T Memory Read Strobe. This pin is asserted when the ADSP-21065L reads from external memory
devices or from the IOP register of another ADSP-21065L. External devices (including another
ADSP-21065L) must assert RD to read from the ADSP-21065L’s IOP registers. In a multiprocessor system, RD is output by the bus master and is input by another ADSP-21065L.
WR I/O/T Memory Write Strobe. This pin is asserted when the ADSP-21065L writes to external memory
devices or to the IOP register of another ADSP-21065L. External devices must assert WR to
write to the ADSP-21065L’s IOP registers. In a multiprocessor system, WR is output by the bus
master and is input by the other ADSP-21065L.
SW I/O/T Synchronous Write Select. This signal interfaces the ADSP-21065L to synchronous memory
devices (including another ADSP-21065L). The ADSP-21065L asserts SW to provide an early
indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in
a conditional write instruction). In a multiprocessor system, SW is output by the bus master and
is input by the other ADSP-21065L to determine if the multiprocessor access is a read or write.
SW is asserted at the same time as the address output.
ACK I/O/S Memory Acknowledge. External devices can deassert ACK to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold
off completion of an external memory access. The ADSP-21065L deasserts ACK as an output
to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a
slave ADSP-21065L deasserts the bus master’s ACK input to add wait state(s) to an access of
its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at
the level to which it was last driven.
SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the external bus address,
data, selects, and strobes—but not SDRAM control pins—in a high impedance state for the
following cycle. If the ADSP-21065L attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not finish until SBTS is deasserted.
SBTS should only be used to recover from host processor/ADSP-21065L deadlock.
IRQ
2-0
FLAG
11-0
I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
I/O/A Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can
be tested as a condition. As an output, it can be used to signal external peripherals.
DATA
23-0,
are decoded into MS
, FLAG
31-0
, SW, and inputs that have
11-0
. The MS
3-0
lines are decoded
3-0
lines are inactive; they are active, however, when a condi-
lines are output by the bus master.
3-0
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–7–
ADSP-21065L
Pin Type Function
HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the ADSP-
21065L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L
that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP21065L places the address, data, select, and strobe lines in a high impedance state. It does,
however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L
bus requests (BR
HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may
take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released.
In a multiprocessor system, HBG is output by the ADSP-21065L bus master.
CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L.
REDY (O/D) O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait states to an asyn-
chronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by
default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D).
REDY will only be output if the CS and HBR inputs are asserted.
) in a multiprocessor system.
2-1
DMAR
DMAR
DMAG
DMAG
BR
2-1
1
2
1
2
I/A DMA Request 1 (DMA Channel 9).
I/A DMA Request 2 (DMA Channel 8).
O/T DMA Grant 1 (DMA Channel 9).
O/T DMA Grant 2 (DMA Channel 8).
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065Ls to arbitrate for bus
mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID
2-0
inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD.
ID
1-0
I Multiprocessing ID. Determines which multiprocessor bus request (BR1–BR2) is used by
ADSP-21065L. ID = 01 corresponds to BR
, ID = 10 corresponds to BR2. ID = 00 in single-
1
processor systems. These lines are a system configuration selection which should be hard-wired
or changed only at reset.
CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21065L
bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an
open drain output that is connected to both ADSP-21065Ls in the system. The CPA pin has an
internal 5 kW pull-up resistor. If core access priority is not required in a system, leave the CPA
pin unconnected.
DTxX O Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kW internal pull-
up resistor.
DRxX I Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kW internal pull-up
resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kW internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kW internal pull-up resistor.
TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
BSEL I EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured for booting from
an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See
BMS for details. This signal is a system configuration selection which should be hardwired.
–8–
REV. C
ADSP-21065L
Pin Type Function
BMS I/O/T* Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1).
In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that
no booting will occur and that the ADSP-21065L will begin executing instructions from external memory. See following table. This input is a system configuration selection which should be
hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
BSEL BMS Booting Mode
1Output EPROM (connect BMS to EPROM chip select).
01 (Input) Host processor (HBW [SYSCON] bit selects host bus width).
00 (Input) No booting. Processor executes from external memory.
CLKIN I Clock In. Used in conjunction with XTAL, configures the ADSP-21065L to use either its
internal clock generator or an external clock source. The external crystal should be rated at 1x
frequency.
Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. The ADSP-21065L’s internal clock generator multiplies the 1x clock to generate 2x clock
for its core and SDRAM. It drives 2x clock out on the SDCLKx pins for the SDRAM interface
to use. See also SDCLKx.
Connecting the 1x external clock to CLKIN while leaving XTAL unconnected configures the
ADSP-21065L to use the external clock source. The instruction cycle rate is equal to 2x CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
RESET I/A Processor Reset. Resets the ADSP-21065L to a known state and begins execution at the
program memory location specified by the hardware reset vector address. This input must be
asserted at power-up.
TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kW internal
pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kW
internal pull-up resistor.
TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the ADSP-21065L. TRST has a 20 kW internal
pull-up resistor.
EMU (O/D) O Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target board connector
only.
BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21065L is cur-
rent bus master of the shared external bus. The ADSP-21065L drives BMSTR high only while
it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high.
CAS I/O/T SDRAM Column Access Strobe. Provides the column address. In conjunction with RAS,
MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
RAS I/O/T SDRAM Row Access Strobe. Provides the row address. In conjunction with CAS, MSx,
SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform.
SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes
SDA10, defines the operation for the SDRAM to perform.
DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write
operations.
SDCLK
SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet
1-0
I/O/S/T SDRAM 2x Clock Output. In systems with multiple SDRAM devices connected in parallel,
supports the corresponding increased clock load requirements, eliminating need of off-chip
clock buffers. Either SDCLK
supplied with your SDRAM device.
or both SDCLKx pins can be three-stated.
1
REV. C
–9–
ADSP-21065L
Pin Type Function
SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access.
XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the ADSP-21065L’s
internal clock generator or to disable it to use an external clock source. See CLKIN.
PWM_EVENT
1-0
VDD P Power Supply; nominally +3.3 V dc. (33 pins)
GND G Power Supply Return. (37 pins)
NC Do Not Connect. Reserved pins that must be left open and unconnected. (7 pins)
I/O/A PWM Output/Event Capture. In PWMOUT mode, is an output pin and functions as a timer
counter. In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture.
CLOCK SIGNALS
The ADSP-21065L can use an external clock or a crystal. See
CLKIN pin description. You can configure the ADSP-21065L
to use its internal clock generator by connecting the necessary
components to CLKIN and XTAL. You can use either a crystal
operating in the fundamental mode or a crystal operating at an
overtone. Figure 4 shows the component connections used for a
crystal operating in fundamental mode, and Figure 5 shows
the component connections used for a crystal operating at an
overtone.
CLKIN
X1
C1
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-33-30.000M (THROUGH-HOLE PACKAGE)
C1 = 33pF
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.
XTAL
C2
Figure 4. 30 MHz Operation (Fundamental Mode Crystal)
CLKIN XTAL
R
X1
C1 C2
SUGGESTED COMPONENTS FOR 30MHz OPERATION:
ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK ECT-30.000M (THROUGH-HOLE PACKAGE)
C1 = 18pF
C2 = 27pF
C3 = 75pF
L
= 3300nH
1
R
= SEE NOTE.
S
NOTE: C1, C2, C3, R
FOR X1. CONTACT MANUFACTURER FOR DETAILS.
AND L1 ARE SPECIFIC TO CRYSTAL SPECIFIED
S
S
C3
L1
Figure 5. 30 MHz Operation (3rd Overtone Crystal)
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST,
TDI, TDO, EMU and GND signals be made accessible on the
target system via a 14-pin connector (a 2 row x 7 pin strip header)
such as that shown in Figure 6. The EZ-ICE probe plugs directly
onto this connector for chip-on-board emulation. You must add
this connector to your target board design if you, intend to use
the ADSP-2106x EZ-ICE.
The total trace length between the EZ-ICE connector and the
furthest device sharing the EZ-ICE JTAG pins should be limited to 15 inches maximum for guaranteed operation. This
restriction on length must include EZ-ICE JTAG signals, which
are routed to one or more 2106x devices or to a combination of
2106xs and other JTAG devices on the chain.
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location—you must remove Pin 3 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 ¥ 0.1 inches. Pin strip headers are available
from vendors such as 3M, McKenzie and Samtec.
12
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
34
5
78
910
9
11 12
13 14
TOP VIEW
EMU
CLKIN (OPTIONAL)
6
TMS
TCK
TRST
TDI
TDO
Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
(JTAG Header)
–10–
REV. C
ADSP-21065L
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If you are not
going to use the test access port for board testing, tie BTRST
to GND and tie or pull-up BTCK to V
be asserted after power-up (through BTRST on the connector)
or held low for proper operation of the ADSP-2106x. None of
the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
Signal Termination
TMS Driven through 22 W resistor (16 mA driver)
TCK Driven at 10 MHz through 22 W resistor
(16 mA driver)
TRST* Driven through 22 W resistor (16 mA driver)
(pulled up by on-chip 20 kW resistor)
TDI Driven by 22 W resistor (16 mA driver)
TDO One TTL load, Split Termination (160/220)
CLKIN One TTL load, Split Termination (160/220).
(Caution: Do not connect to CLKIN if
internal XTAL oscillator is used.)
EMU Active Low 4.7 kW pull-up resistor, one TTL
load (open-drain output from ADSP-2106xs)
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
The TRST pin must
DD.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping, and single-stepping two
ADSP-21065Ls in a synchronous manner. If you do not need
these operations to occur synchronously on the two processors,
simply tie Pin 4 of the EZ-ICE header to ground.
For systems which use the internal clock generator and an external
discrete crystal, do not directly connect the CLKIN pin to the
JTAG probe. This will load the oscillator circuit and possibly
cause it to fail to oscillate. Instead the JTAG probe’s CLKIN
can be driven by the XTAL pin through a high impedance buffer.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between multiple ADSP-2106x
processors and the CLKIN pin on the EZ-ICE header must be
minimal. If the skew is too large, synchronous operations may
be off by one cycle between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and EMU should be
treated as critical signals in terms of skew, and should be laid
out as short as possible on your board.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User’s Guide and Reference.
REV. C
–11–
ADSP-21065L–SPECIFICATIONS
WARNING!
ESD SENSITIVE DEVICE
RECOMMENDED OPERATING CONDITIONS
Test C Grade K Grade
Parameter Conditions Min Max Min Max Unit
V
DD
T
CASE
V
IH
V
IL1
V
IL2
NOTE
See Environmental Conditions for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min Max Unit
V
OH
V
OL
I
IH
I
IL
I
ILP
I
OZH
I
OZL
I
OZLS
I
OZLA
I
OZLAR
I
OZLC
C
IN
NOTES
1
Applies to input and bidirectional pins: DATA
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS , SDWE, SDCKE.
2
Applies to input pin CLKIN.
3
Applies to output and bidirectional pins: DATA
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0, PWM_EVENT1,
RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE , SDA10.
4
See Output Drive Currents for typical drive current capabilities.
5
Applies to input pins: ACK, SBTS, IRQ
during reset in a multiprocessor system, when ID
6
Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.
7
Applies to three-statable pins: DATA
SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (Note that ACK is pulled up internally with 2 kW during reset in a multiprocessor system, when ID
01 and another ADSP-21065L is not requesting bus mastership).
8
Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.
9
Applies to CPA pin.
10
Applies to ACK pin when pulled up.
11
Applies to ACK pin when keeper latch enabled.
12
Guaranteed but not tested.
13
Applies to all signal pins.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130∞C
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21065L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Supply Voltage 3.13 3.60 3.13 3.60 V
Case Operating Temperature –40 +100 0 +85 ∞C
High Level Input Voltage @ VDD = max 2.0 VDD + 0.5 2.0 VDD + 0.5 V
Low Level Input Voltage
Low Level Input Voltage
1
2
@ VDD = min –0.5 0.8 –0.5 0.8 V
@ VDD = min –0.5 0.7 –0.5 0.7 V
C and K Grades
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Input Capacitance
12, 13
3
3
5
5
6
7, 8, 9, 10
7
8
11
10
9
31-0
, HBR, CS, DMAR1, DMAR2, ID
2-0
, ADDR
31-0
@ VDD = min, IOH = –2.0 mA
@ VDD = min, IOL = 4.0 mA
@ VDD = max, VIN = VDD max 10 mA
@ VDD = max, VIN = 0 V 10 mA
@ VDD = max, VIN = 0 V 150 mA
@ VDD = max, VIN = VDD max 10 mA
@ VDD = max, VIN = 0 V 8 mA
@ VDD = max, VIN = 0 V 150 mA
@ VDD = max, VIN = 1.5 V 350 mA
@ VDD = max, VIN = 0 V 4 mA
@ VDD = max, VIN = 0 V 1.5 mA
fIN = 1 MHz, T
, ADDR
, ADDR
31-0
= 01 and another ADSP-21065L is not requesting bus mastership.)
1-0
, MS
23-0
, BSEL, RD, WR, SW, ACK, SBTS, IRQ
23-0
, MS
23-0
, RD, WR, SW, ACK, FLAG
3-0
, RD, WR, SW, ACK, FLAG
3-0
1-0
= 25∞C, VIN = 2.5 V 8 pF
CASE
, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 kW
11-0
4
4
, FLAG
2-0
, HBG, REDY, DMAG1, DMAG2, BR
11-0
, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS, DQM,
11-0
2.4 V
0.4 V
, HBG, CS, DMAR1, DMAR2, BR
2-1
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . 280∞C
+ 0.5 V
DD
+ 0.5 V
DD
*Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
–12–
, CPA, TCLK0,
, ID
2-1
REV. C
,
2-0
=
1-0
ADSP-21065L
POWER DISSIPATION ADSP-21065L
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Table II. Internal Current Measurements
Peak Activity High Activity
Operation (I
DDINPEAK
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK ¥ I
DDINPEAK
+ %HIGH ¥ I
DDINHIGH
(See note 4 below Table III.)
OR %PEAK ¥ I
DDINPEAK
+ %HIGH ¥ I
(See note 5 below Table III.)
)(I
+ %LOW ¥ I
DDINHIGH
+ %LOW ¥ I
DDINLOW
DDINHIGH
+ %IDLE ¥ I
DDINLOW
+ %IDLE16 ¥ I
) Low Activity (I
= POWER CONSUMPTION
DDIDLE
DDIDLE16
Table III. Internal Current Measurement Scenarios
DDINLOW
= POWER CONSUMPTION
)
Parameter Test Conditions Max Unit
I
DDINPEAK
I
DDINHIGH
I
DDINLOW
I
DDIDLE
I
DDIDLE16
NOTES
1
The test program used to measure I
power measurements made using typical applications are less than specified.
2
I
is a composite average based on a range of high activity code.
DDINHIGH
3
I
is a composite average based on a range of low activity code.
DDINLOW
4
IDLE denotes ADSP-21065L state during execution of IDLE instruction.
5
IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (IDLE)
Supply Current (IDLE16)
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal
DDINPEAK
1
2
3
4
5
tCK = 33 ns, VDD = max 470 mA
= 30 ns, VDD = max 510 mA
t
CK
tCK = 33 ns, VDD = max 275 mA
t
= 30 ns, VDD = max 300 mA
CK
tCK = 33 ns, VDD = max 240 mA
t
= 30 ns, VDD = max 260 mA
CK
tCK = 33 ns, VDD = max 150 mA
= 30 ns, VDD = max 155 mA
t
CK
VDD = max 50 mA
TIMING SPECIFICATIONS
General Notes
Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (t
max range of the t
specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
CK
= 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
CK
period of 33.3 ns:
DT = (t
– 33.3)/32
CK
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
REV. C
–13–
ADSP-21065L
Switching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
66 MHz 60 MHz
Parameter Min Max Min Max Unit
Clock Input
Timing Requirements:
t
CK
t
CKL
t
CKH
t
CKRF
CLKIN Period 30.00 100 33.33 100 ns
CLKIN Width Low 7.0 7.0 ns
CLKIN Width High 5.0 5.0 ns
CLKIN Rise/Fall (0.4 V–2.0 V) 3.0 3.0 ns
t
CK
CLKIN
t
CKH
t
CKL
Figure 7. Clock Input
Parameter Min Max Unit
Reset
Timing Requirements:
t
WRST
t
SRST
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
RESET Pulsewidth Low
RESET Setup Before CLKIN High
CLKIN
RESET
1
2
t
WRST
2 t
CK
23.5 + 24 DT t
t
SRST
CK
ns
ns
Figure 8. Reset
Parameter Min Max Unit
Interrupts
Timing Requirements:
t
SIR
t
HIR
t
IPW
NOTES
1
Only required for IRQx recognition in the following cycle.
2
Applies only if t
IRQ2-0 Setup Before CLKIN High or Low
IRQ2-0 Hold Before CLKIN High or Low
IRQ2-0 Pulsewidth
and t
SIR
requirements are not met.
HIR
2
1
1
11.0 + 12 DT ns
0.0 + 12 DT ns
2.0 + tCK/2 ns
–14–
REV. C
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