ANALOG DEVICES ADSP-21065L Service Manual
ADSP-21065L SHARC® DSP
Technical Reference
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
Revision 2.0, July 2003
Part Number
82-001903-01
a
Copyright Information
©2003 Analog Devices, Inc., ALL RIGHTS RESERVED. This document
may not be reproduced in any form without prior, express written consent
from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by
implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices logo, the SHARC logo, EZ-ICE, and SHARC are
registered trademarks of Analog Devices, Inc.
VisualDSP++ is a trademark of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
CONTENTS
PREFACE
For Additional Information About Analog Products ...................... -xiii
For Technical or Customer Support .............................................. -xiv
What’s This Book About and Who’s It For? ................................... -xiv
How to Use This Manual ............................................................. -xvi
Related Documents .................................................................... -xviii
Conventions of Notation .............................................................. -xix
INSTRUCTION SET REFERENCE
Instruction Summary ................................................................... A-2
Compute and Move/Modify Summary .................................... A-4
Program Flow Control Summary ............................................ A-6
Immediate Move Summary ..................................................... A-8
Miscellaneous Instructions Summary ...................................... A-9
Reference Notation Summary ............................................... A-11
Register Types Summary ....................................................... A-15
Memory Addressing Summary .............................................. A-18
Opcode Notation ....................................................................... A-19
Universal Register Codes ...................................................... A-24
ADSP-21065L SHARC DSP Technical Reference iii
CONTENTS
Group I Instructions (Compute & Move) .................................... A-28
Compute/dregÙDM/dregÙPM (Type 1) ........................... A-30
Compute (Type 2) ................................................................ A-32
Compute/uregÙDM|PM, register modify (Type 3) .............. A-33
Compute/dreg
Compute/uregÙureg (Type 5) ............................................. A-37
Immediate Shift/dreg
Compute/modify (Type 7) .................................................... A-42
Group II Instructions (Program Flow Control) ............................ A-44
Direct Jump|Call (Type 8) ..................................................... A-45
Indirect Jump|Call / Compute (Type 9) ................................. A-48
Indirect Jump or Compute/dregÙDM (Type 10) ................. A-52
Return From Subroutine|Interrupt/Compute (Type 11) ......... A-55
Do Until Counter Expired (Type 12) ..................................... A-58
Do Until (Type 13) ............................................................... A-60
Group III Instructions (Immediate Move) ................................... A-62
ÙDM|PM (direct addressing) (Type 14) ....................... A-63
Ureg
Ureg
ÙDM|PM (indirect addressing) (Type 15) .................... A-65
ÙDM|PM, immediate modify (Type 4) ......... A-35
ÙDM|PM (Type 6) ............................. A-39
Immediate data
Immediate dataÖureg (Type 17) ........................................... A-69
Group IV Instructions (Miscellaneous) ........................................ A-70
System Register Bit Manipulation (Type 18) .......................... A-71
Register Modify/bit-reverse (Type 19) .................................... A-73
iv ADSP-21065L SHARC DSP Technical Reference
ÖDM|PM (Type 16) .................................... A-67
CONTENTS
Push|Pop Stacks/Flush Cache (Type 20) ................................ A-75
Nop (Type 21) ..................................................................... A-77
Idle (Type 22) ...................................................................... A-78
Idle16 (Type 23) ................................................................... A-79
Cjump/Rframe (Type 24) ..................................................... A-81
COMPUTE OPERATION REFERENCE
Single-Function Operations .......................................................... B-2
ALU Operations ..................................................................... B-2
Rn = Rx + Ry ......................................................................... B-6
Rn = Rx – Ry ......................................................................... B-7
Rn = Rx + Ry + CI ................................................................. B-8
Rn = Rx – Ry + CI – 1 ............................................................ B-9
Rn = (Rx + Ry)/2 .................................................................. B-10
COMP(Rx, Ry) .................................................................... B-11
Rn = Rx + CI ....................................................................... B-12
Rn = Rx + CI – 1 .................................................................. B-13
Rn = Rx + 1 ......................................................................... B-14
Rn = Rx – 1 ......................................................................... B-15
Rn = –Rx ............................................................................. B-16
Rn = ABS Rx ........................................................................ B-17
Rn = PASS Rx ...................................................................... B-18
Rn = Rx AND Ry ................................................................. B-19
Rn = Rx OR Ry .................................................................... B-20
Rn = Rx XOR Ry ................................................................. B-21
ADSP-21065L SHARC DSP Technical Reference v
CONTENTS
Rn = NOT Rx ...................................................................... B-22
Rn = MIN(Rx, Ry) ................................................................ B-23
Rn = MAX(Rx, Ry) ............................................................... B-24
Rn = CLIP Rx BY Ry ............................................................ B-25
Fn = Fx + Fy ......................................................................... B-26
Fn = Fx – Fy ......................................................................... B-27
Fn = ABS (Fx + Fy) ............................................................... B-28
Fn = ABS (Fx – Fy) ............................................................... B-29
Fn = (Fx + Fy)/2 ................................................................... B-30
COMP(Fx, Fy) ..................................................................... B-31
Fn = –Fx ............................................................................... B-32
Fn = ABS Fx ......................................................................... B-33
Fn = PASS Fx ........................................................................ B-34
Fn = RND Fx ....................................................................... B-35
Fn = SCALB Fx BY Ry .......................................................... B-36
Rn = MANT Fx .................................................................... B-37
Rn = LOGB Fx ..................................................................... B-38
Rn = FIX Fx
Rn = TRUNC Fx
Rn = FIX Fx BY Ry
Rn = TRUNC Fx BY Ry ..................................................... B-39
Fn = FLOAT Rx BY Ry
Fn = FLOAT Rx ................................................................. B-41
Fn = RECIPS Fx ................................................................... B-42
Fn = RSQRTS Fx .................................................................. B-44
vi ADSP-21065L SHARC DSP Technical Reference
CONTENTS
Fn = Fx COPYSIGN Fy ....................................................... B-46
Fn = MIN(Fx, Fy) ................................................................ B-47
Fn = MAX(Fx, Fy)................................................................ B-48
Fn = CLIP Fx BY Fy ............................................................. B-49
Multiplier Operations ................................................................ B-50
Rn = Rx * Ry mod2
MRF = Rx * Ry mod2
MRB = Rx * Ry mod2 ....................................................... B-54
Rn = MRF + Rx * Ry mod2
Rn = MRB + Rx * Ry mod2
MRF = MRF + Rx * Ry mod2
MRB = MRB + Rx * Ry mod2 .......................................... B-55
Rn = MRF – Rx * Ry mod2
Rn = MRB – Rx * Ry mod2
MRF = MRF – Rx * Ry mod2
MRB = MRB – Rx * Ry mod2 .......................................... B-56
Rn = SAT MRF mod1
Rn = SAT MRB mod1
MRF = SAT MRF mod1
MRB = SAT MRB mod1 ................................................... B-57
Rn = RND MRF mod1
Rn = RND MRB mod1
MRF = RND MRF mod1
MRB = RND MRB mod1 .................................................. B-58
MRF = 0
MRB = 0 ....................................................................... B-59
MR = Rn/Rn = MR .............................................................. B-60
Fn = Fx * Fy ......................................................................... B-62
ADSP-21065L SHARC DSP Technical Reference vii
CONTENTS
Shifter Operations ...................................................................... B-63
Rn = LSHIFT Rx BY Ry
Rn = LSHIFT Rx BY <data8> ............................................. B-65
Rn = Rn OR LSHIFT Rx BY Ry
Rn = Rn OR LSHIFT Rx BY <data8> ................................. B-66
Rn = ASHIFT Rx BY Ry
Rn = ASHIFT Rx BY <data8> ............................................ B-67
Rn = Rn OR ASHIFT Rx BY Ry
Rn = Rn OR ASHIFT Rx BY <data8> ................................ B-68
Rn = ROT Rx BY Ry
Rn = ROT Rx BY <data8> .................................................. B-69
Rn = BCLR Rx BY Ry
Rn = BCLR Rx BY <data8> ................................................ B-70
Rn = BSET Rx BY Ry
Rn = BSET Rx BY <data8> ................................................. B-71
Rn = BTGL Rx BY Ry
Rn = BTGL Rx BY <data8> ................................................ B-72
BTST Rx BY Ry
BTST Rx BY <data8> ......................................................... B-73
Rn = FDEP Rx BY Ry
Rn = FDEP Rx BY <bit6>:<len6> ....................................... B-74
Rn = Rn OR FDEP Rx BY Ry
Rn = Rn OR FDEP Rx BY <bit6>:<len6> ........................... B-76
Rn = FDEP Rx BY Ry (SE)
Rn = FDEP Rx BY <bit6>:<len6> (SE) .............................. B-78
Rn = Rn OR FDEP Rx BY Ry (SE)
Rn = Rn OR FDEP Rx BY <bit6>:<len6> (SE) ................... B-80
viii ADSP-21065L SHARC DSP Technical Reference
CONTENTS
Rn = FEXT Rx BY Ry
Rn = FEXT Rx BY <bit6>:<len6> ...................................... B-82
Rn = FEXT Rx BY Ry (SE)
Rn = FEXT Rx BY <bit6>:<len6> (SE) ............................... B-84
Rn = EXP Rx ........................................................................ B-86
Rn = EXP Rx (EX) ............................................................... B-87
Rn = LEFTZ Rx ................................................................... B-88
Rn = LEFTO Rx .................................................................. B-89
Rn = FPACK Fx ................................................................... B-90
Fn = FUNPACK Rx ............................................................. B-92
Multifunction Computations ..................................................... B-94
Dual Add/Subtract (Fixed-Pt.) .............................................. B-96
Dual Add/Subtract (Floating-Pt.) .......................................... B-98
Parallel Multiplier and ALU (Fixed-Pt.) ................................ B-100
Parallel Multiplier & ALU (Floating-Point) .......................... B-101
Parallel Multiplier and Dual Add/Subtract ............................ B-104
ADSP-21065L SHARC DSP Technical Reference ix
CONTENTS
NUMERIC FORMATS
Single-Precision Floating-Point Format ......................................... C-2
Extended-Precision Floating-Point Format .................................... C-4
Short Word Floating-Point Format ................................................ C-5
Fixed-Point Formats ..................................................................... C-8
JTAG TEST ACCESS PORT
Test Access Port (TAP) ................................................................. D-2
Instruction Register ..................................................................... D-3
Boundary Register ....................................................................... D-6
Device Identification Register .................................................... D-28
Built-In Self-Test Instructions (BIST) ........................................ D-28
Private Instructions .................................................................... D-29
References ................................................................................. D-29
CONTROL AND STATUS REGISTERS
System Registers ........................................................................... E-2
Latencies—Effect and Read ..................................................... E-4
System Register Bit Manipulation Instruction .......................... E-5
Bit Test Flag ............................................................................ E-6
ASTAT
Arithmetic Status Register .................................................... E-8
IMASK and IRPTL
Interrupt Mask and Latch Registers .................................... E-12
MODE1 Register .................................................................. E-16
MODE2 Register .................................................................. E-21
x ADSP-21065L SHARC DSP Technical Reference
CONTENTS
Sticky Status Register (STKY) ................................................ E-27
IOP Registers .............................................................................. E-31
IOP Registers Summary ......................................................... E-31
IOP Register Access Restrictions ............................................ E-40
IOP Register Group Access Contention .................................. E-41
IOP Register Write Latencies ................................................. E-42
DMACx
External Port DMA Control Registers ................................. E-54
DMASTAT
DMA Channel Status Register ............................................ E-64
IOCTL
Programmable I/O and SDRAM Control Register ............... E-68
IOSTAT
Programmable I/O Status Register ....................................... E-75
RDIVx/TDIVx
SPORT Divisor Registers .................................................... E-78
SRCTLx
SPORT Receive Control Register ........................................ E-81
STCTLx
SPORT Transmit Control Register ...................................... E-90
SYSCON
System Configuration Register ............................................ E-99
SYSTAT
System Status Register ...................................................... E-106
WAIT
External Memory Wait State Control Register ................... E-111
ADSP-21065L SHARC DSP Technical Reference xi
CONTENTS
SYMBOL DEFINITIONS FILE
(def21065L.h) ....................................................................... E-116
INTERRUPT VECTOR ADDRESSES
INDEX
xii ADSP-21065L SHARC DSP Technical Reference
PREFACE
Listing 1-0.
Figure 1-0.
Table 1-0.
Congratulations on your purchase of Analog Devices ADSP-21065L
SHARC® DSP, the high-performance Digital Signal Processor of choice!
The ADSP-21065L is a 32-bit DSP with 544K bits of on-chip memory
that is designed to support a wide variety of applications—audio, automo-
tive, communications, industrial, and instrumentation.
For Additional Information About Analog Products
Analog Devices is online on the internet at http://www.analog.com. Our
Web pages provide information on the company and products, including
access to technical information and documentation, product overviews,
and product announcements. You may also obtain additional information
about Analog Devices and its products in any of the following ways:
• Visit our World Wide Web site at www.analog.com.
• FAX questions or requests for information to
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
ADSP-21065L SHARC DSP Technical Reference xiii
1(781)461-3010.
For Technical or Customer Support
• Access the division’s File Transfer Protocol (FTP) site at ftp
ftp.analog.com or ftp 137.71.23.21 or ftp://ftp.anlog.com.
This site is a mirror of the BBS.
For Technical or Customer Support
You can reach our Customer Support group in the following ways:
• Visit our World Wide Web site at www.analog.com.
• Call the Analog Devices automated Customer Support Hot Line at
1(800)ANALOG-D.
• E-mail questions to dsp.support@analog.com or
dsp.europe@analog.com (European customer support).
What’s This Book About and Who’s It For?
The ADSP-21065L documentation set contains two manuals, the
ADSP-21065L SHARC DSP User’s Manual and the ADSP-21065L
SHARC DSP Technical Reference. These manuals are reference guides for
hardware and software engineers who want to develop applications using
the ADSP-21065L. These manuals assume that the user has a working
knowledge of the ADSP-21065L’s Super Harvard Architecture.
The ADSP-21065L SHARC DSP User’s Manual describes the architecture
and operation of the ADSP-21065L’s individual components, intercomponent connections and access, off-chip connections and access, and the
processor’s hardware/software interface.
xiv ADSP-21065L SHARC DSP Technical Reference
Preface
The information in this book includes:
• Pin definitions and instructions for connecting the pins to external
devices and peripherals in single- and multiprocessor systems.
• Processor features and instructions for configuring the processor for
specific operation options.
• Internal and external data paths and instructions for moving data
between internal components and between the processor and external devices and peripherals.
• Timing, sequencing, and throughput of control signals and data
accesses.
The ADSP-21065L SHARC DSP Technical Reference provides detailed
technical information on programming the ADSP-21065L. This information includes:
• A description of each instruction in the processor’s instruction set,
supported numeric formats, and the default bit definitions for all of
the processor’s control and status registers.
• A description of the pins and the control and data registers of the
JTAG test access port.
• A list of all vector interrupts and their addresses.
To supplement the information in these manuals, users can attend scheduled workshops sponsored by Analog Devices, Inc. (ADI) and access other
ADI documentation related specifically to this product. For details, see
“Related Documents” on page xviii.
ADSP-21065L SHARC DSP Technical Reference xv
How to Use This Manual
How to Use This Manual
For information on… See…
ALU operation Chapter 2, Computation Units; Appendix B,
Compute Operation Reference
Address generation Chapter 4, Data Addressing; Chapter 5, Mem-
ory; Chapter 6, DMA
Booting Chapter 5, Memory; Chapter 7, System Design
Clock generation Chapter 9, Serial Ports; Chapter 11, Pro-
grammable Timers and I/O Ports; Chapter 12,
System Design
Computation units Chapter 2, Computation Units; Appendix B,
Compute Operation Reference; Appendix C,
Numeric Formats
Data delays,
latencies,
throughput
Data packing Chapter 6, DMA; Chapter 8, Host Interface;
DMA Chapter 6, DMA; Chapter 7, Multiprocessing;
External port Chapter 6, DMA; Chapter 7, Multiprocessing;
High-frequency design
issues
Host interface Chapter 8, Host Interface
Instruction cache Chapter 3, Program Sequencing; Chapter 5,
Chapter 10, SDRAM Interface; Chapter 12,
System Design
Chapter 9, Serial Ports
Chapter 8, Host Interface
Chapter 8, Host Interface
Chapter 12, System Design
Memory
xvi ADSP-21065L SHARC DSP Technical Reference
Preface
For information on… See…
Instruction set Appendix A, Instruction Set Reference;
Appendix B, Compute Operation Reference;
Appendix C, Numeric Formats
Internal buses Chapter 5, Memory; Chapter 6, DMA; Chapter
8, Host Interface
Interrupts Chapter 3, Program Sequencing; Chapter 5,
Memory; Appendix F, Interrupt Vector
Addresses
JTAG test port Chapter 12, System Design; Appendix D, JTAG
Test Access Port
Memory Chapter 5, Memory
Multiplier operation Chapter2, Computation Units; Appendix B,
Compute Operation Reference
Multiprocessing Chapter 7, Multiprocessing
Pin definitions Chapter 12, System Design
Processor
architecture
Processor
configuration
Program flow Chapter 3, Program Sequencing
Programmable I/O
ports
Programmable timers Chapter 11, Programmable Timers and I/O
Programming
considerations
Chapter 1, Introduction
Appendix E, Control and Status Registers
Chapter 11, Programmable Timers and I/O
Ports
Ports
Chapter 13, Programming Considerations
ADSP-21065L SHARC DSP Technical Reference xvii
Related Documents
For information on… See…
Reset Chapter 7, Multiprocessing; Chapter 9,
Serial Ports; Chapter 12, System Design
SDRAM interface Chapter 10 SDRAM Interface
Serial ports Chapter 9, Serial Ports
Shifter operation Chapter 2, Computation Units; Appendix B,
Compute Operation Reference
System Design Chapter 12, System Design
Wait states Chapter 5, Memory; Chapter 12, System
Design; Appendix E, Control and Status Registers
Indexes Both manuals are cross-indexed. Pages with
an alphabetic prefix (as C-12) reference
information in ADSP-21065L SHARC DSP Techni-
cal Reference. Pages with a numeric prefix
(as 5-41) reference information in
ADSP-21065L SHARC DSP User’s Manual.
Related Documents
For information on related products, see the following documents available from Analog Devices, Inc.:
• ADSP-21065L SHARC DSP, 198 MFLOPS, 3.3v Data Sheet
(Rev. C, 6/03)
• VisualDSP++ Quick Installation Reference Card
• VisualDSP++ 3.0 User’s Guide for SHARC DSPs
• VisualDSP++ 3.0 Getting Started Guide for SHARC DSPs
xviii ADSP-21065L SHARC DSP Technical Reference
Preface
• VisualDSP++ 3.0 C/C++ Compiler and Library Manual for SHARC
DSPs
• VisualDSP++ 3.0 Linker and Utilities Manual for SHARC DSPs
• VisualDSP++ 3.0 Assembler and Preprocessor Manual for SHARC
DSPs
• VisualDSP++ 3.0 Kernel (VDK) User’s Guide
• VisualDSP++ 3.0 Component Software Engineering User’s Guide
Conventions of Notation
The following conventions apply to all chapters within this manual. Additional conventions that apply to specific chapters only are documented at
the beginning of the chapter in which they appear.
This notation… Denotes…
Letter Gothic
font
Italics Special terminology; titles of books.
*
,
Code, software or command line options or keywords; input you must enter from the keyboard.
A hint or tip.
A warning or caution.
ADSP-21065L SHARC DSP Technical Reference xix
Conventions of Notation
xx ADSP-21065L SHARC DSP Technical Reference
A INSTRUCTION SET
REFERENCE
Figure A-0.
Table A-0.
Listing A-0.
Appendix A and B describe the processor’s instruction set. This appendix
explains each instruction type, including the assembly language syntax and
opcodes, which result from instruction assembly.
Many instructions’ opcodes contain a COMPUTE field that specifies a compute operation using the ALU, Multiplier, or Shifter. Because a large
number of options are available for computations, their descriptions
appear in Appendix B.
Because data moves between the MR registers and the Register File are
considered Multiplier operations, their descriptions appear in Appendix B.
ADSP-21065L SHARC DSP Technical Reference A-1
Instruction Summary
Instruction Summary
Each instruction is specified in this appendix. The reference page for an
instruction shows the syntax of the instruction, describes its function,
gives one or two assembly-language examples, and identifies fields of its
opcode. The instruction types are organized into four groups:
• “Group I Instructions (Compute & Move)” on page A-28
These instruction specify a compute operation in parallel with one
or two data moves or an index register modify.
• “Group II Instructions (Program Flow Control)” on page A-44
These instructions specify various types of branches, calls, returns,
and loops. Some may also specify a compute operation or a data
move.
• “Group III Instructions (Immediate Move)” on page A-62
These instructions use immediate instruction fields as operators for
addressing.
• “Group IV Instructions (Miscellaneous)” on page A-70
These instructions include bit modify, bit test, no operation, and
idle.
The instructions are referred to by type, ranging from 1 to 23. These types
correspond to the opcodes that the processor recognizes, but are for reference only and have no bearing on programming.
Some instructions have more than one syntactical form; for example,
instruction “Compute/dregÙDM|PM, immediate modify (Type 4)” on
page A-35 has four distinct forms.
A-2 ADSP-21065L SHARC DSP Technical Reference
Instruction Set Reference
Many instructions can be conditional. These instructions are prefaced by
IF COND; for example:
If COND compute, |DM(Ia,Mb)| = ureg;
In a conditional instruction, the execution of the entire instruction is
based on the specified condition.
ADSP-21065L SHARC DSP Technical Reference A-3
Instruction Summary
Compute and Move/Modify Summary
Compute and move/modify instructions are classed as Group I instructions, and they provide math, conditional, memory or register access
services. For a complete description of these instructions, see the noted
pages.
*
For all compute and move/modify instructions, IF
COND is optional.
“Compute/dregÙDM/dregÙPM (Type 1)” page A-30
compute , DM(Ia, Mb) = dreg1 , PM(Ic, Md) = dreg2 ;
, dreg1 = DM(Ia, Mb) , dreg2 = PM(Ic, Md)
“Compute (Type 2)” on page A-32
IF COND compute ;
“Compute/uregÙDM|PM, register modify (Type 3)” on page A-33
IF COND compute , DM(Ia, Mb) = ureg ;
, PM(Ic, Md)
, DM(Mb, Ia) = ureg ;
, PM(Md, Ic)
, ureg = DM(Ia, Mb) ;
PM(Ic, Md) ;
, ureg = DM(Mb, Ia) ;
PM(Md, Ic) ;
A-4 ADSP-21065L SHARC DSP Technical Reference
Instruction Set Reference
“Compute/dregÙDM|PM, immediate modify (Type 4)” on page A-35
IF COND compute , DM(Ia, <data6>) = dreg ;
, PM(Ic, <data6>)
, DM(<data6>, Ia) = dreg ;
, PM(<data6>, Ic)
, dreg = DM(Ia, <data6>) ;
PM(Ic, <data6>) ;
, dreg = DM(<data6>, Ia) ;
PM(<data6>, Ic) ;
“Compute/uregÙureg (Type 5)” on page A-37
IF COND compute, ureg1 = ureg2 ;
“Immediate Shift/dregÙDM|PM (Type 6)” on page A-39
IF COND shiftimm , DM(Ia, Mb) = dreg ;
, PM(Ic, Md)
, dreg = DM(Ia, Mb) ;
PM(Ic, Md) ;
“Compute/modify (Type 7)” on page A-42
IF COND compute , MODIFY (Ia, Mb) ;
(Ic, Md) ;
ADSP-21065L SHARC DSP Technical Reference A-5
Instruction Summary
Program Flow Control Summary
Program flow control instructions are classed as Group II instructions,
and they provide control of program execution flow. For a complete
description of these instructions, see the noted pages.
*
instructions, IF COND is optional.
“Direct Jump|Call (Type 8)” on page A-45
For all program flow control instructions, except type 10
IF COND
JUMP
IF COND
CALL
<addr24> (DB) ;
(PC, <reladdr24>) (LA)
(CI)
(DB, LA)
(DB, CI)
<addr24> (DB) ;
(PC, <reladdr24>)
“Indirect Jump|Call / Compute (Type 9)” on page A-48
IF COND
JUMP
(Md, Ic) (DB) , compute ;
(PC, <reladdr6>) (LA) , ELSE compute
(CI)
(DB, LA)
(DB, CI)
IF COND
CALL
(Md, Ic) (DB) , compute ;
(PC, <reladdr6>) , ELSE compute
“Indirect Jump or Compute/dregÙDM (Type 10)” on page A-52
IF COND
Jump
(Md, Ic) , Else compute, DM(Ia, Mb) = dreg ;
(PC, <reladdr6> compute, dreg = DM(Ia, Mb) ;
A-6 ADSP-21065L SHARC DSP Technical Reference
Instruction Set Reference
“Return From Subroutine|Interrupt/Compute (Type 11)” on page A-55
IF COND RTS (DB) , compute ;
(LR) , ELSE compute
(DB, LR)
IF COND RTI (DB) , compute ;
, ELSE compute
“Do Until Counter Expired (Type 12)” on page A-58
LCNTR = <data16> , DO <addr24> UNTIL LCE ;
ureg (<PC, reladdr24>)
“Do Until (Type 13)” on page A-60
DO <addr24> UNTIL termination ;
(PC, <reladdr24>)
ADSP-21065L SHARC DSP Technical Reference A-7
Instruction Summary
Immediate Move Summary
Immediate move instructions are classed as Group III instructions, and
they provide memory and register access services. For a complete description of these instructions, see the noted pages.
“UregÙDM|PM (direct addressing) (Type 14)” on page A-63
DM(<addr32>)
PM(<addr24>)
ureg = DM(<addr32>) ;
= ureg ;
PM(<addr24>)
“UregÙDM|PM (indirect addressing) (Type 15)” on page A-65
DM(<data32>, Ia)
PM(<data24>, Ic)
ureg = DM(<data32>, Ia) ;
= ureg ;
PM(<data24>, Ic) ;
“Immediate dataÖDM|PM (Type 16)” on page A-67
DM(Ia, Mb)
PM(Ic, Md)
= <data32> ;
“Immediate dataÖureg (Type 17)” on page A-69
ureg = <data32> ;
A-8 ADSP-21065L SHARC DSP Technical Reference
Instruction Set Reference
Miscellaneous Instructions Summary
Miscellaneous instructions are classed as Group IV instructions, and they
provide system register, bit manipulation, and low power services. For a
complete description of these instructions, see the noted pages.
“System Register Bit Manipulation (Type 18)” on page A-71
BIT SET sreg <data32> ;
CLR
TGL
TST
XOR
“Register Modify/bit-reverse (Type 19)” on page A-73
MODIFY (Ia, <data32>) ;
(Ic, <data24>)
BITREV (Ia, <data32>) ;
(Ic, <data24>)
“Push|Pop Stacks/Flush Cache (Type 20)” on page A-75
PUSH LOOP , PUSH STS , PUSH PCSTK , FLUSH CACHE ;
POP POP POP
“Nop (Type 21)” on page A-77
NOP ;
“Idle (Type 22)” on page A-78
IDLE ;
ADSP-21065L SHARC DSP Technical Reference A-9
Instruction Summary
“Idle16 (Type 23)” on page A-79
IDLE16 ;
“Cjump/Rframe (Type 24)” on page A-81
CJUMP function (DB) ;
(PC, <reladdr24>)
RFRAME ;
A-10 ADSP-21065L SHARC DSP Technical Reference
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