Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)
1 Megabit Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable as 32K Words Data Memory (32-Bit), 16K
Words Program Memory (48-Bit) or Combinations of
Both Up to 1 Mbit
Off-Chip Memory Interfacing
4-Gigawords Addressable (32-Bit Address)
Programmable Wait State Generation, Page-Mode DRAM
Support
CORE PROCESSOR
INSTRUCTION
DAG1
8 x 4 x 32
BUS
CONNECT
(PX)
MULTIPLIER
DAG2
8 x 4 x 24
PM ADDRESS BUS
DM ADDRESS BUS
DATA
REGISTER
FILE
16 x 40-BIT
TIMER
PM DATA BUS
DM DATA BUS
CACHE
32 x 48-BIT
PROGRAM
SEQUENCER
BARREL
SHIFTER
ADDRDATAADDR
24
32
48
40/32
ALU
Figure 1. ADSP-21061/ADSP-21061L Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
EZ-ICE is a registered trademark of Analog Devices, Inc.
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up To Six ADSP-21061s Plus Host
300 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports
Independent Transmit and Receive Functions
3- to 32-Bit Data Word Width
-Law/A-Law Hardware Companding
TDM Multichannel Mode
Multichannel Signaling Protocol
ADSP-21061L EZ-ICE Emulator (Jumpers in Place) . . . 12
Figure 34. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (V
–2–
= 3.3 V) . . . . . . . 41
DD
REV. B
®
S
ADSP-21061/ADSP-21061L
GENERAL NOTE
This data sheet represents production released specifications
for the ADSP-21061 5 V and ADSP-21061L 3.3 V processors. ADSP-21061 is used throughout this data sheet to refer to
both devices unless expressly noted.
GENERAL DESCRIPTION
The ADSP-21061 is a member of the powerful SHARC family
of floating point processors. The SHARC—Super Harvard
Architecture Computer—are signal processing microcomputers
that offer new capabilities and levels of integration and performance. The ADSP-21061 is a 32-bit processor optimized for
high performance DSP applications. The ADSP-21061 combines the ADSP-21000 DSP core with a dual-ported on-chip
SRAM and an I/O processor with a dedicated I/O bus to form a
complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time operating at up
to 50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table I shows performance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC
ing-point DSP core with integrated, on-chip system features,
including a 1 Mbit SRAM memory, host processor interface,
DMA controller, serial ports and parallel bus connectivity for
glueless DSP multiprocessing.
combines a high-performance float-
Figure 1 shows a block diagram of the ADSP-21061/ADSP21061L, illustrating the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
1 Mbit On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port & Multiprocessor Interface
DMA Controller
Serial Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multiprocessing system is shown in Figure 3.
Table I. ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 is code and
function compatible with the ADSP-21060/ADSP-21062 and
the ADSP-21020.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all perform single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit singleprecision floating-point, extended precision 40-bit floatingpoint and 32-bit fixed-point data formats.
ADSP-21061/
ADSP-21061L
DATA
CS
ADDR
DATA
ADDR
DATA
OE
PERIPHERALS
WE
(OPTIONAL)
ACK
CS
DMA DEVICE
(OPTIONAL)
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
MEMORY
AND
1x CLOCK
TO GND
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
CLKIN
EBOOT
LBOOT
3
IRQ
2-0
4
FLAG
3-0
TIMEXP
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
RPBA
ID
2-0
RESET
ADDR
DATA
MS
PAGE
SBTS
ADRCLK
DMAR
DMAG
REDY
BR
JTAG
BMS
31-0
47-0
RD
WR
ACK
SW
CS
HBR
HBG
CPA
7
ADDRESS
CONTROL
3-0
1-2
1-2
1-6
Figure 2. ADSP-21061/ADSP-21061L System
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the ADSP21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction Cache
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The ADSP-21061 two
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers (16 primary register sets, 16 secondary). The
DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance and simplifying implementation. Circular buffers can start and end at any memory
location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP21061 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21061 FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21061
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21061 contains 1 megabit of on-chip SRAM, organized as two banks of 0.5 Mbits each. Each bank has eight 16bit columns with 4K 16-bit words per column. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 Memory Map).
On the ADSP-21061, the memory can be configured as a maximum of 32K words of 32-bit data, 64K words for 16-bit data,
16K words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 1 megabit. All the memory
can be accessed as 16-bit, 32-bit or 48-bit.
A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on chip.
Conversion between the 32-bit floating-point and 16-bit floatingpoint formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores instructions and data, using the PM bus for transfers. Using the
DM and PM buses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP21061’s external port.
–4–
REV. B
ADSP-21061/ADSP-21061L
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s interface to off-chip memory and peripherals. The 4-gigaword offchip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 32-bit address
bus and a single 48-bit (or 32-bit) data bus. The on-chip
Super Harvard Architecture provides three-bus performance,
while the off-chip unified address space gives flexibility to the
designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to DRAM and peripherals with variable access, hold and disable time requirements.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s external port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG) and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the
DMA channel setup and mailbox registers. Vector interrupt
support is provided for efficient execution of host commands.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zerooverhead, nonintrusive data transfers without processor intervention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32or 48-bit words is performed during DMA transfers.
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR
, DMAG
1-2
). Other DMA features include interrupt
1-2
generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maximum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from three
bits to 32 bits. They offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding.
Serial port clocks and frame syncs can be internally or externally
generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
Multiprocessing
The ADSP-21061 offers powerful features tailored to multiprocessing DSP systems. The unified address space allows direct
interprocessor accesses of each ADSP-21061’s internal memory.
Distributed bus arbitration logic is included on-chip for simple,
glueless connection of systems containing up to six ADSP-21061s
and a host processor. Master processor changeover incurs only
one cycle of overhead. Bus arbitration is selectable as either
fixed or rotating priority. Bus lock allows indivisible read-modifywrite sequences for semaphores. A vector interrupt is provided
for interprocessor commands. Maximum throughput for interprocessor data transfer is 500 Mbytes/sec over the external port.
Broadcast writes allow simultaneous transmission of data to
all ADSP-21061s and can be used to implement reflective
semaphores.
Program Booting
The internal memory of the ADSP-21061 can be booted at
system power-up from either an 8-bit EPROM or a host processor. Selection of the boot source is controlled by the BMS (Boot
Memory Select), EBOOT (EPROM Boot), and LBOOT (Host
Boot) pins. 32-bit and 16-bit host processors can be used for
booting. See the BMS pin in the Pin Function Descriptions
section of this data sheet.
REV. B
–5–
ADSP-21061/ADSP-21061L
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
011
010
ADSP-2106x #3
CLKIN
RESET
RPBA
3
ID
2-0
CONTROL
ADSP-2106x #2
CLKIN
RESET
RPBA
3
ID
2-0
CONTROL
ADDR
DATA
BR
1-2
ADDR
DATA
BR1, BR
, BR
31-0
47-0
CPA
BR
31-0
47-0
CPA
BR
CONTROL
5
4-6
3
5
3-6
2
DATA
ADDRESS
1x
CLOCK
ADSP-2106x #1
001
CLKIN
RESETRESET
RPBA
3
ID
2-0
CONTROL
ADDR
DATA
ACK
MS
BMS
PAGE
SBTS
ADRCLK
HBR
HBG
REDY
CPA
BR
BR
31-0
47-0
RD
WR
SW
CS
3-0
5
2-6
1
Figure 3. Multiprocessing System
CONTROL
ADDRESS
DATA
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
ADDR
DATA
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
–6–
REV. B
ADSP-21061/ADSP-21061L
INTERNAL
MEMORY
SPACE
MULTIPROCESSOR
MEMORY SPACE
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
IOP REGISTERS
NORMAL WORD ADDRESSING
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=001
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=010
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=011
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=100
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
EXTERNAL
MEMORY
SPACE
BANK 0
DRAM
(OPTIONAL)
BANK 1
BANK 2
BANK 3
NONBANKED
0x0040 0000
MS
0
MS
1
MS
2
MS
3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
0xFFFF FFFF
Figure 4. ADSP-21061/ADSP-21061L Memory Map
REV. B
–7–
ADSP-21061/ADSP-21061L
Porting Code from ADSP-21060 or ADSP-21062 to the
ADSP-21061
The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the Link Port pins of the ADSP-21060/
ADSP-21062 are no-connects.
The ADSP-21061 is object code compatible with the ADSP21060/ADSP-21062 except for the following functional
changes:
The ADSP-21061 memory is organized into two blocks
with eight columns that are 4K deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per block.
Link port functions are not available.
Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.
2-D DMA capability of the SPORT is not available.
The modify registers in SPORT DMA are not programmable.
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the ADSP21061—these addresses will alias into the actual Block 1 of each
processor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8K of instructions
or up to 16K of data in each bank of the ADSP-21062, or any
combinations of instructions or data that does not exceed the
memory bank.
DEVELOPMENT TOOLS
The ADSP-21061 is supported with a complete set of software
and hardware development tools, including an EZ-ICE
Circuit Emulator, EZ-Kit Lite, and development software. The
SHARC
EZ-Kit Lite (ADDS-2106x-EZ-Lite) is a complete low
In-
cost package for DSP evaluation and prototyping. The EZ-Kit
Lite contains an evaluation board with an ADSP-21061 (5 V)
processor and provides a serial connection to your PC. The EZKit Lite also includes an optimizing compiler, assembler, instruction level simulator, run-time libraries, diagnostic utilities
and a complete set of example programs.
The same EZ-ICE hardware can be used for the ADSP-21060/
ADSP-21062, to fully emulate the ADSP-21061, with the exception of displaying and modifying the two new SPORTS
registers. The emulator will not display these two registers,
but your code can use them.
Analog Devices ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
Assembly Library/Librarian, Linker, instruction-level Simulator,
an ANSI C optimizing Compiler, the CBUG™ C Source—
Level Debugger and a C Runtime Library including DSP and
mathematical functions. The Optimizing Compiler includes
Numerical C extensions based on the work of the ANSI Numerical C Extensions Group. Numerical C provides extensions
to the C language for array selections, vector math operations,
complex data types, circular pointers and variably dimensioned
arrays. The ADSP-21000 Family Development Software is
available for both the PC and Sun platforms.
The EZ-ICE
port of the ADSP-21061 processor to monitor and control the
target board processor during emulation. The EZ-ICE
Emulator uses the IEEE 1149.1 JTAG test access
provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG interface—the emulator does not affect target system loading or
timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware and Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC
ware tools include SHARC
SHARC
VME boards, and daughter and modules with multiple
PC plug-in cards multiprocessor
processor family. Hard-
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer to
the ADSP-2106x SHARC User’s Manual, Second Edition.
CBUG and SHARCPAC are trademarks of Analog Devices, Inc.
–8–
REV. B
ADSP-21061/ADSP-21061L
PIN DESCRIPTIONS
ADSP-21061 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to IVDD or IGND,
except for ADDR
, DATA
31-0
, FLAG
47-0
, SW and inputs that
3-0
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
PIN FUNCTION DESCRIPTIONS
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left
floating. These pins have a logic-level hold circuit that prevents
the input from floating internally.
I = InputS = SynchronousP = Power Supply
(O/D) = Open DrainO = OutputA = Asynchronous
G = Ground(A/D) = Active Drive
T = Three-State (when SBTS is asserted, or when the
ADSP-2106x is a bus slave)
PinTypeFunction
ADDR
31-0
I/O/TExternal Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a
host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
DATA
47-0
I/O/TExternal Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins.
The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point
data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of
the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on unused DATA pins are not necessary.
MS
3-0
O/TMemory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The MS
the other address lines. When no external memory access is occurring the MS
lines are decoded memory address lines that change at the same time as
3-0
lines are inactive;
3-0
they are active, however, when a conditional memory access instruction is executed, whether or not the
condition is true. MS
(Bank 0). In a multiprocessor system the MS
can be used with the PAGE signal to implement a bank of DRAM memory
0
lines are output by the bus master.
3-0
RDI/O/TMemory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external
memory devices or from the internal memory of other ADSP-21061s. External devices (including
other ADSP-21061s) must assert RD to read from the ADSP-21061’s internal memory. In a multiprocessor system RD is output by the bus master and is input by all other ADSP-21061s.
WRI/O/TMemory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory
devices or to the internal memory of other ADSP-21061s. External devices must assert WR to write to
the ADSP-21061’s internal memory. In a multiprocessor system WR is output by the bus master and is
input by all other ADSP-21061s.
PAGEO/TDRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE
signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the
bus master.
ADRCLKO/TAddress Clock for synchronous external memories. Addresses on ADDR
are valid before the
31-0
rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.
SWI/O/TSynchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory
devices (including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g. in a conditional
write instruction). In a multiprocessor system, SW is output by the bus master and is input by all other
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the
same time as the address output. A host processor using synchronous writes must assert this pin when
writing to the ADSP-21061(s).
ACKI/O/SMemory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off
completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add
wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave
ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal
memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it
was last driven to.
REV. B
–9–
ADSP-21061/ADSP-21061L
PinTypeFunction
SBTSI/SSuspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address,
data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061
attempts to access external memory while SBTS is asserted, the processor will halt and the memory
access will not be completed until SBTS is deasserted. SBTS should only be used to recover from
PAGE faults or host processor/ADSP-21061 deadlock.
IRQ
2-0
FLAG
3-0
TIMEXPOTimer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
HBRI/AHost Bus Request. Must be asserted by a host processor to request control of the ADSP-21061’s
HBGI/OHost Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take
CSI/AChip Select. Asserted by host processor to select the ADSP-21061.
REDY (O/D)OHost Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-
RPBAI/SRotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
CPA (O/D)I/OCore Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave
DTxOData Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRxIData Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKxI/OTransmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKxI/OReceive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
I/AInterrupt Request Lines. May be either edge-triggered or level-sensitive.
I/O/AFlag Pins. Each is configured via control bits as either an input or an output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
zero.
external bus. When HBR is asserted in a multiprocessing system, the ADSP-21061 that is bus master
will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address,
data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21061 bus
requests (BR
) in a multiprocessing system.
6-1
control of the external bus. HBG is asserted (held low) by the ADSP-21061 until HBR is released. In a
multiprocessing system, HBG is output by the ADSP-21061 bus master and is monitored by all others.
nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the CS and HBR inputs are asserted.
I/O/SMultiprocessing Bus Requests. Used by multiprocessing ADSP-21061s to arbitrate for bus master-
ship. An ADSP-21061 only drives its own BRx line (corresponding to the value of its ID
inputs) and
2-0
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BRx pins
should be tied high; the processor’s own BRx line must not be tied high or low because it is an output.
IMultiprocessing ID. Determines which multiprocessing bus request (BR1–BR6) is used by ADSP-
21061. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed at
reset.
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection which must be set to the same value on every ADSP-21061. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.
to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain
output that is connected to all ADSP-2106Ls in the system. The CPA pin has an internal 5 kΩ pull-up
resistor. If core access priority is not required in a system, the CPA pin should be left unconnected.
–10–
REV. B
ADSP-21061/ADSP-21061L
PinTypeFunction
TFSxI/OTransmit Frame Sync (Serial Ports 0, 1).
RFSxI/OReceive Frame Sync (Serial Ports 0, 1).
EBOOTIEPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table
below. This signal is a system configuration selection which should be hardwired.
LBOOTILink Boot—Must be tied to GND.BMSI/O/T*Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-
cates that no booting will occur and that ADSP-21061 will begin executing instructions from external
memory. See table below. This input is a system configuration selection which should be hardwired.
*Three-statable only in EPROM boot mode (when BMS is an output).
EBOOTLBOOTBMSBooting Mode
10OutputEPROM (Connect BMS to EPROM chip select.)
001 (Input)Host Processor
000 (Input)No Booting. Processor executes from external memory.
CLKINIClock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the specified frequency.
RESETI/AProcessor Reset. Resets the ADSP-21061 to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCKITest Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMSI/STest Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up
resistor.
TDII/STest Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal
pull-up resistor.
TDOOTest Data Output (JTAG). Serial scan output of the boundary scan path.TRSTI/ATest Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.
EMUOEmulation Status. Must be connected to the ADSP-21061 EZ-ICE
ICSAOReserved, leave unconnected.
VDDPPower Supply; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.
GNDGPower Supply Return.
NCDo Not Connect. Reserved pins which must be left open and unconnected.
target board connector only.
REV. B
–11–
ADSP-21061/ADSP-21061L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pins should be limited to 15
inches maximum for guaranteed operation. This length restriction must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP2106x devices and other JTAG devices on the chain.
12
GND
BTDI
GND
34
5
78
910
9
1112
1314
TOP VIEW
KEY (NO PIN)
BTMS
BTCK
BTRST
Figure 5. Target Board Connector For ADSP-21061/ADSP21061L EZ-ICE
Emulator (Jumpers in Place)
EMU
CLKIN (OPTIONAL)
6
TMS
TCK
TRST
TDI
TDO
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie BTRST to GND
and tie or pull BTCK up to VDD. The TRST pin must be
asserted after power-up (through BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
SignalTermination
TMSDriven through 22 Ω Resistor (16 mA Driver)
TCKDriven at 10 MHz through 22 Ω Resistor (16 mA
Driver)
TRST* Active Low Driven through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
TDIDriven by 22 Ω Resistor (16 mA Driver)
TDOOne TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMUActive Low 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
OTHER
JTAG
CONTROLLER
EZ-ICE
JTAG
CONNECTOR
EMU
TRST
TDO
CLKIN
TDI
TCK
TMS
ADSP-2106x
TDI
TCK
OPTIONAL
#1
TMS
TDO
EMU
TRST
JTAG
DEVICE
(OPTIONAL)
TDI
TCK
TMS
TDO
TRST
ADSP-2106x
#n
TDI
TCK
TMS
TDO
EMU
TRST
Figure 6. JTAG Scan Path Connections for Multiple ADSP-21061/ADSP-21061L Systems
–12–
REV. B
ADSP-21061/ADSP-21061L
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform operations such as starting, stopping and single-stepping multiple
ADSP-2106x in a synchronous manner. If you do not need these
operations to occur synchronously on the multiple processors,
simply tie Pin 4 of the EZ-ICE
header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP21061x processors and the CLKIN pin on the EZ-ICE
header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For synchronous multiprocessor operation TCK, TMS, CLKIN and
EMU should be treated as critical signals in terms of skew, and
TDITDOTDITDO
5k⍀
*
TDITDO
should be laid out as short as possible on your board. If TCK,
TMS and CLKIN are driving a large number of ADSP-2106x
(more than eight) in your system, then treat them as a clock tree
using multiple drivers to minimize skew. (See Figure 7, JTAG
Clock Tree, and Clock Distribution in the High Frequency
Design Considerations section of the ADSP-2106x User’sManual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termination on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP-21000 Family JTAG EZ-ICE User’s Guide and Reference.
TDITDO
TDITDO
TDITDO
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
5k⍀
*
*
OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
EMU
Figure 7. JTAG Clocktree for Multiple ADSP-21061/ADSP-21061L Systems
SYSTEM
CLKIN
REV. B
–13–
ADSP-21061/ADSP-21061L
ADSP-21061–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
K Grade
ParameterTest ConditionsMinMaxUnit
V
DD
T
CASE
V
IH1
V
IH2
V
IL
NOTES
1
Applies to input and bidirectional pins: DATA
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT
2
Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
ParameterTest ConditionsMinMaxUnit
V
OH
V
OL
I
IH
I
IL
I
ILP
I
OZH
I
OZL
I
OZHP
I
OZLC
I
OZLA
I
OZLAR
I
OZLS
C
IN
Supply Voltage4.755.25V
Case Operating Temperature0+85°C
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Input Capacitance
Applies to output and bidirectional pins: DATA
DMAG2, BR
12
See Output Drive Currents section for typical drive current capabilities.
13
Applies to input pins: ACK SBTS, IRQ
internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)
14
Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.
15
Applies to three-statable pins: DATA
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
not requesting bus mastership.)
16
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
17
Applies to CPA pin.
18
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
ADSP-21061x is not requesting bus mastership).
19
Applies to three-statable pins with internal pull-downs: LxDAT
, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up
2-0
, REDY, HBG, DMAG1, DMAG2, BMS, BR
3-0
= 001 and another ADSP-2106x is
2-0
= 001 and another
2-0
6–1
,
–14–
REV. B
ADSP-21061/ADSP-21061L
POWER DISSIPATION ADSP-21061 (5 V)
These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
OperationPeak Activity (I
DDINPEAK
)High Activity (I
DDINHIGH
)Low Activity (I
DDINLOW
)
Instruction TypeMultifunctionMultifunctionSingle Function