ANALOG DEVICES ADSP-21061, ADSP-21061L Service Manual

a

SHARC

Commercial Grade

®

Family DSP Microcomputer

ADSP-21061/ADSP-21061L

SUMMARY

High performance signal processor for communications,

graphics, and imaging applications

Super Harvard Architecture

Four independent buses for dual data fetch, instruction

fetch, and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip

Integrated multiprocessing features

KEY FEATURES—PROCESSOR CORE

50 MIPS, 20 ns instruction rate, single-cycle instruction

execution

120 MFLOPS peak, 80 MFLOPS sustained performance

CORE PROCESSOR

INSTRUCTION

DAG1

8  4  32

DAG2

8  4  24

PM ADDRESS BUS

DM ADDRESS BUS

TIMER

CACHE

32  48-BIT

PROGRAM

SEQUENCER

24

32

Dual data address generators with modulo and bit-reverse

addressing

Efficient program sequencing with zero-overhead looping:

single-cycle loop setup

IEEE JTAG Standard 1149.1 test access port and on-chip

emulation

32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data
format

240-lead MQFP package, thermally enhanced MQFP, 225-ball

plastic ball grid array (PBGA)

Lead (Pb) free packages. For more information, see Ordering

Guide on Page 53.

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

ADDR DATA ADDR

ADDR DATA

DATA

DATA ADDR

IOD

48

BLOCK 0

IOA

17

BLOCK 1

JTAG

TEST AND

EMULATION

EXTERNAL

PORT

ADDR BUS

MUX

7

32

DATA

REGISTER

FILE

16  40-BIT

PM DATA BUS

BUS

CONNECT

(PX)

MULT

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DM DATA BUS

BARREL

SHIFTER

48

40/32

ALU

S

REGISTERS

(MEMORY
MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

Figure 1. Functional Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

IOP

CONTROLLER

SERIAL PORTS

I/O PROCESSOR

DMA

(2)

MULTIPROCESSOR

INTERFACE

DATA BU S

MUX

HOST PORT

4

6

6

48

ADSP-21061/ADSP-21061L

Parallel Computations

Single-cycle multiply and ALU operations in parallel with

dual memory read/write and instruction fetch

Multiply with add and subtract for accelerated FFT butterfly

computation

1M bit On-Chip SRAM

Dual-ported for independent access by core processor and

DMA

Off-Chip Memory Interfacing

4 gigawords addressable
Programmable wait state generation, page-mode DRAM

support

DMA Controller

6 DMA channels for transfers between ADSP-21061 internal

memory and external memory, external peripherals, host
processor, or serial ports

Background DMA transfers at up to 40 MHz, in parallel with

full-speed processor execution

Host Processor Interface to 16- and 32-Bit Microprocessors

Host can directly read/write ADSP-21061 internal memory

Multiprocessing

Glueless connection for scalable DSP multiprocessing

architecture

Distributed on-chip bus arbitration for parallel bus connect

of up to six ADSP-21061s plus host

240 MBps transfer rate over parallel bus

Serial Ports

Two 40 Mbps synchronous serial ports with companding

hardware

Independent transmit and receive functions

Rev. C | Page 2 of 56 | July 2007

CONTENTS

ADSP-21061/ADSP-21061L

General Description ................................................. 4

SHARC Family Core Architecture ............................ 4

Memory and I/O Interface Features ........................... 5

Porting Code From the ADSP-21060 or ADSP-21062 .... 8

Development Tools ............................................... 8

Evaluation Kit ...................................................... 9

Designing an Emulator-Compatible DSP

Board (Target) .................................................. 9

Additional Information .......................................... 9

Pin Function Descriptions ........................................ 10

Target Board Connector For EZ-ICE Probe ................ 13

ADSP-21061 Specifications ....................................... 15

Operating Conditions (5 V) .................................... 15

Electrical Characteristics (5 V) ................................ 15

Internal Power Dissipation (5 V) ............................. 16

External Power Dissipation (5 V) ............................. 17

ADSP-21061L Specifications ..................................... 18

Operating Conditions (3.3 V) ................................. 18

Electrical Characteristics (3.3 V) .............................. 18

Internal Power Dissipation (3.3 V) ........................... 19

External Power Dissipation (3.3 V) .......................... 20

Absolute Maximum Ratings ................................... 21

ESD Sensitivity .................................................... 21

Package Marking Information ................................ 21

Timing Specifications ........................................... 21

Test Conditions ................................................... 44

Environmental Conditions ..................................... 47

225-Ball PBGA Pin Configurations ............................. 48

240-Lead MQFP Pin Configurations ............................ 50

Outline Dimensions ................................................ 51

Surface-Mount Design .......................................... 53

Ordering Guide ...................................................... 53

REVISION HISTORY

7/07—Rev B to Rev C

Added

Porting Code From the ADSP-21060 or ADSP-21062 ....... 8

Added several new lead (Pb) free models. See

Ordering Guide ......................................................53

GENERAL NOTE

This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.

Rev. C | Page 3 of 56 | July 2007

ADSP-21061/ADSP-21061L

GENERAL DESCRIPTION

The ADSP-21061 SHARC—Super Harvard Architecture Com­puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual­ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 1 shows perfor­mance benchmarks for the ADSP-21061/ADSP-21061L.

The ADSP-21061 SHARC represents a new standard of integra­tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea­tures including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus con­nectivity for glueless DSP multiprocessing.

Table 1. Benchmarks (at 50 MHz)

Benchmark Algorithm Speed Cycles

1024 Point Complex FFT (Radix 4,

.37 ms 18,221

with reversal)
FIR Filter (per tap) 20 ns 1
IIR Filter (per biquad) 80 ns 4
Divide (y/x) 120 ns 6
Inverse Square Root 180 ns 9
DMA Transfer Rate 300M Bps

The ADSP-21061 continues SHARC’s industry-leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.

The block diagram on Page 1, illustrates the following architec­tural features:

• Computation units (ALU, multiplier, and shifter) with a
shared data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

•Interval timer

•On-chip SRAM

• External port for interfacing to off-chip memory and
peripherals

• Host port and multiprocessor interface

• DMA controller

•Serial ports

• JTAG test access port

ADSP-21061

1 ⫻ CLOCK

TO GND

SERIAL
DEVICE

(OPTIONAL)

SERIAL
DEVICE

(OPTIONAL)

3
4

CLKIN
EBOOT
LBOOT

IRQ

2–0

FLAG

3–0

TIMEXP

TCLK0
RCLK0
TFS0
RSF0
DT0
DR0

TCLK1
RCLK1
TFS1
RSF1
DT1
DR1

RPBA
ID

2–0

RESET JTAG

BMS

ADDR

DATA

ACK

MS

PAGE

SBTS

ADRCLK
DMAR
DMAG

HBR
HBG

REDY
BR

31–0

47–0

RD

WR

3–0

SW

1–2

1–2

CS

1–6

CPA

7

L
O
R

T
N
O
C

CS

BOOT

EPROM

ADDR

(OPTIONAL)

DATA

ADDR

MEMORY-

DATA

MAPPED

OE

DEVICES

WE

(OPTIONAL)

ACK
CS

S
S

A

E

T

R
D
D
A

A
D

DATA

DMA DEVICE

(OPTIONAL)

PROCESSOR

INTERFACE
(OPTIONAL)

ADDR
DATA

HOST

Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration

SHARC FAMILY CORE ARCHITECTURE

The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier, and shifter all per­form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi­function instructions execute parallel ALU and multiplier oper­ations. These computation units support IEEE 32-bit single­precision floating-point, extended-precision 40-bit floating­point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for stor­ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.

Rev. C | Page 4 of 56 | July 2007

ADSP-21061/ADSP-21061L

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(Figure 1 on Page 1). With its separate program and data mem-
ory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.

Instruction Cache

The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-21061’s two data address generators (DAGs) imple­ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21061 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem­ory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21061 can conditionally execute a multiply, an add, a
subtract, and a branch, all in a single instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-21061 processors add the following architectural
features to the SHARC family core.

Dual-Ported On-Chip Memory

The ADSP-21061 contains one megabit of on-chip SRAM, orga­nized as two blocks of 0.5M bits each. Each bank has eight 16-bit
columns with 4k 16-bit words per column. Each memory block
is dual-ported for single-cycle, independent accesses by the core
processor and I/O processor or DMA controller. The dual­ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 memory map).

On the ADSP-21061, the memory can be configured as a maxi­mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k
words of 48-bit instructions (and 40-bit data) or combinations
of different word sizes up to 1 megabit. All the memory can be
accessed as 16-bit, 32-bit, or 48-bit.

A 16-bit floating-point storage format is supported, which effec­tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float­ing-point formats is done in a single instruction.

While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-21061’s external port.

Off-Chip Memory and Peripherals Interface

The ADSP-21061’s external port provides the processor’s inter­face to off-chip memory and peripherals. The 4-gigaword off­chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program mem­ory, data memory, and I/O—are multiplexed at the external port
to create an external system bus with a single 32-bit address bus
and a single 48-bit (or 32-bit) data bus. The on-chip Super Har­vard Architecture provides three-bus performance, while the
off-chip unified address space gives flexibility to the designer.

Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim­plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external mem­ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold, and disable time
requirements.

Host Processor Interface

The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit­tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter­nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.

The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.

), host bus grant (HBG), and

DMA Controller

The ADSP-21061’s on-chip DMA controller allows zero­overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.

Rev. C | Page 5 of 56 | July 2007

ADSP-21061/ADSP-21061L

CLKIN

RESET

RPBA

3

ID2–0

011

ADSP-2 1061 #6
ADSP-2 1061 #5
ADSP-2 1061 #4

ADSP-21061 #3

ADDR31–0

DATA47–0

CONTROL

L

S
S

O
R
T
N
O
C

A

E

T

R

A

D

D

D
A

RESET

CLOCK

010

001

BUS

PRIORITY

CLKIN

RESET

RPBA

3

ID2–0

CLKIN

RESET

RPBA

3

ID2–0

BR1–2, BR4–6

ADSP-21061 #2

ADDR31–0

DATA47–0

CONTROL

BR1, BR3–6

ADSP-21061 #1

ADDR31–0

DATA47–0

L
O

MS3–0

R
T
N

O
C

PAGE

SBTS

REDY

BR2–6

BR3

CPA

BR2

RDx

WRx

ACK

BMS

HBR
HBG

CPA

BR1

CS

5

5

L

S
S

O
R
T
N
O
C

5

A

E

T

R

A

D

D

D
A

ADDR

DATA

OE
WE

ACK

CS

CS

ADDR

DATA

ADDR

DATA

GLOBAL MEMORY
AND
PERIPHERAL (O PTIONAL)

BOOT EPROM (OPTIONAL)

HOSTPROCESSOR
INTERFACE (O PTIONAL)

Figure 3. Shared Memory Multiprocessing System

DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.

Rev. C | Page 6 of 56 | July 2007

DMA transfers between external memory and external periph­eral devices are another option. External bus packing to 16-, 32­, or 48-bit words is performed during DMA transfers.

ADSP-21061/ADSP-21061L

Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA request/grant lines
(DMAR

, DMAG

1–2

). Other DMA features include interrupt

1–2

generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.

Serial Ports

The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi­mum data rate of 40 Mbps. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.

ADDRESS

The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits
to 32 bits. They offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally gen­erated. The serial ports also include keyword and key mask
features to enhance interprocessor communication.

Multiprocessing

The ADSP-21061 offers powerful features tailored to multipro­cessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-21061’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-21061s and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vec­tor interrupt is provided for interprocessor commands. Maxi­mum throughput for interprocessor data transfer is 500 Mbps
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21061s and can be used to
implement reflective semaphores.

ADDRESS

INTERNAL
MEMORY
SPACE

MULTIPROCESSOR
MEMOR Y
SPACE

IOP REGISTERS

NORMAL WORD ADDRESSING

(32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS)

SHORT WORD ADDRESSING

(16-BIT DATA WORDS)

INTERNAL MEMORY SPACE

WITH ID = 001

INTERNAL MEMORY SPACE

WITH ID = 010

INTERNAL MEMORY SPACE

WITH ID = 011

INTERNAL MEMORY SPACE

WITH ID = 100

INTERNAL MEMORY SPACE

WITH ID = 101

INTERNAL MEMORY SPACE

WITH ID = 110

BROADCASTWRITE

TO ALL ADSP-21061s

0x0000 0000

0x0002 0000

0x0004 0000

0x0008 0000

0x0010 0000

0x0018 0000

0x0012 0000

0x0028 0000

0x0030 0000

0x0038 0000

0x003F FFFF

EXTERNAL
MEMORY
SPACE

BANK 0

SDRAM

(OPTIONAL)

BANK 1

BANK 2

BANK 3

NONBANKED

0x0040 0000

MS0

MS1

MS2

MS3

Figure 4. Memory Map

Rev. C | Page 7 of 56 | July 2007

0x0FFF FFFF

NOTE: BANK SIZES ARE SELECTED BY
MSIZE BITS OF THE SYSCON REGISTER

ADSP-21061/ADSP-21061L

Program Booting

The internal memory of the ADSP-21061 can be booted at sys­tem power-up from either an 8-bit EPROM, or a host processor.
Selection of the boot source is controlled by the BMS

(boot
memory select), EBOOT (EPROM boot), and LBOOT (host
boot) pins. 32-bit and 16-bit host processors can be used for
booting.

PORTING CODE FROM THE ADSP-21060 OR ADSP-21062

The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the link port pins of the ADSP-21060/
ADSP-21062 are no-connects.

The ADSP-21061 is object code compatible with the
ADSP-21060/ADSP-21062 processors except for the folowing
functional elements:

• The ADSP-21061 memory is organized into two blocks
with eight columns that are 4k deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per
block.

• Link port functions are not available.

• Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.

• 2-D DMA capability of the SPORT is not available.

• The modify registers in SPORT DMA are not
programmable.

On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the
ADSP- 21061—these addresses will alias into the actual Block 1
of each processor.

If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8k of instructions
or up to 16k of data in each bank of the ADSP-21062, or any
combination of instructions or data that does not exceed the
memory bank.

DEVELOPMENT TOOLS

The ADSP-21061 is supported by a complete set of
CROSSCORE
Devices emulators and VisualDSP++
ment. The same emulator hardware that supports other SHARC
processors also fully emulates the ADSP-21061.

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

®

†

software development tools, including Analog

®

‡

development environ-

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21061
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,
and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-21061
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits programmers
to:

• Control how the development tools process inputs and
generate outputs

• Maintain a one-to-one correspondence with the tools’
command line switches

The VisualDSP++ kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,

Rev. C | Page 8 of 56 | July 2007

ADSP-21061/ADSP-21061L

eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre­emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.

Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The
expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphi­cal and textual environments.

In addition to the software development tools available from
Analog Devices, third parties provide a wide range of tools sup­porting the SHARC processor family. Third-party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.

EVALUATION KIT

®

Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a
standalone unit, without being connected to the PC.

†

evaluation plat-

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any
custom-defined system. Connecting an Analog Devices JTAG
emulator to the EZ-KIT Lite board enables high speed, nonin­trusive emulation.

DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter­face—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea­tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys­tem timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer
to the ADSP-21061 SHARC User’s Manual, Revision 2.1.

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

Rev. C | Page 9 of 56 | July 2007

ADSP-21061/ADSP-21061L

PIN FUNCTION DESCRIPTIONS

ADSP-21061 pin definitions are listed below. All pins are identi­cal on the ADSP-21061 and ADSP-21061L. Inputs identified as
synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identi­fied as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST

).

Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31-0, DATA47-0, FLAG3-0, SW
internal pull-up or pull-down resistors (CPA

, and inputs that have

, ACK, DTx, DRx,
TCLKx, RCLKx, TMS, and TDI)—these pins can be left float­ing. These pins have a logic-level hold circuit that prevents the
input from floating internally.

Table 2. Pin Descriptions

Pin Type Function

ADDR

31–0

DATA

47–0

MS

3–0

RD

WR

PAG E O /T DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page boundary

ADRCLK O/T Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,
T = Three-State (when SBTS

I/O/T External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system the bus master outputs addresses for read/write of the internal memory or
IOP registers of other ADSP-21061s. The ADSP-21061 inputs addresses when a host processor or multipro­cessing bus master is reading or writing its internal memory or IOP registers.

I/O/T External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins. 32-bit single-

precision floating-point data and 32-bit fixed-point data is transferred over Bits 47 to 16 of the bus. 40-bit
extended-precision floating-point data is transferred over Bits 47 to 8 of the bus. 16-bit short word data is
transferred over Bits 31 to 16 of the bus. In PROM boot mode, 8-bit data is transferred over Bits 23 to 16. Pull­up resistors on unused DATA pins are not necessary.

O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external

memory. Memory bank size must be defined in the ADSP-21061’s system control register (SYSCON). The

lines are decoded memory address lines that change at the same time as the other address lines.

MS

3–0

When no external memory access is occurring the MS
conditional memory access instruction is executed, whether or not the condition is true. MS
with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a multiprocessing system the MS
lines are output by the bus master.

I/O/T Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external memory devices

or from the internal memory of other ADSP-21061s. External devices (including other ADSP-21061s) must
assert RD
bus master and is input by all other ADSP-21061s.

I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory devices

or to the internal memory of other ADSP-21061s. External devices must assert WR to write to the
ADSP-21061’s internal memory. In a multiprocessing system WR
all other ADSP-21061s.

has been crossed. DRAM page size must be defined in the ADSP-21061’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for
Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.

I/O/T Synchronous Write Select. This signal is used to interface the ADSP-21061 to synchronous memory devices

(including other ADSP-21061s). The ADSP-21061 asserts SW (low) to provide an early indication of an
impending write cycle, which can be aborted if WR
instruction). In a multiprocessing system, SW
ADSP-21061s to determine if the multiprocessor memory access is a read or write. SW is asserted at the same
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-21061(s).

is asserted, or when the ADSP-21061 is a bus slave)

to read from the ADSP-21061’s internal memory. In a multiprocessing system RD is output by the

is output by the bus master and is input by all other

lines are inactive; they are active however when a

3–0

is output by the bus master and is input by

is not later asserted (e.g., in a conditional write

can be used

0

3–0

Rev. C | Page 10 of 56 | July 2007

ADSP-21061/ADSP-21061L

Table 2. Pin Descriptions (Continued)

Pin Type Function

ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-21061 deasserts ACK as an output to add wait states to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-21061 deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.

SBTS

IRQ

2–0

FLAG

3–0

TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR

HBG

CS
REDY O (O/D) Host Bus Acknowledge. The ADSP-21061 deasserts REDY (low) to add wait states to an asynchronous access

DMAR

2–1

DMAG

2–1

BR

6–1

ID2–0

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

CPA

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-21061 is a bus slave)

I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,

selects, and strobes in a high impedance state for the following cycle. If the ADSP-21061 attempts to access
external memory while SBTS is asserted, the processor halts and the memory access is not complete until

is deasserted. SBTS should only be used to recover from host processor/ADSP-21061 deadlock, or used

SBTS
with a DRAM controller.

I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.
I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as

a condition. As an output, they can be used to signal external peripherals.

I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-21061’s

external bus. When HBR

is asserted in a multiprocessing system, the ADSP-21061 that is bus master will
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21061 places the address, data, select,
and strobe lines in a high impedance state. HBR

has priority over all ADSP-21061 bus requests BR

6–1

in a

multiprocessing system.

I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the

external bus. HBG is asser ted (held low) by the ADSP-21061 until HBR is released. In a multiprocessing system,

is output by the ADSP-21061 bus master and is monitored by all others.

HBG

I/A Chip Select. Asserted by host processor to select the ADSP-21061.

of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if

and HBR inputs are asserted.

the CS

I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 6).
O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 6).
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21061 processors to arbitrate for bus

mastership. An ADSP-21061 only drives its own BR
monitors all others. In a multiprocessor system with less than six ADSP-21061s, the unused BR

x line (corresponding to the value of its ID2-0 inputs) and

x pins should

be pulled high; the processor’s own BRx line must not be pulled high or low because it is an output.

O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-21061.

ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc., ID = 000 in single-processor systems. These
lines are a system configuration selection which should be hardwired or changed at reset only.

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration
selection which must be set to the same value on every ADSP-21061. If the value of RPBA is changed during
system operation, it must be changed in the same CLKIN cycle on every ADSP-21061.

I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-21061 bus slave to interrupt

background DMA transfers and gain access to the external bus. CPA
connected to all ADSP-21061s in the system. The CPA

pin has an internal 5 kΩ pull-up resistor. If core access

is an open-drain output that is

priority is not required in a system, the CPA pin should be left unconnected.

Rev. C | Page 11 of 56 | July 2007

ADSP-21061/ADSP-21061L

Table 2. Pin Descriptions (Continued)

Pin Type Function

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS
description below. This signal is a system configuration selection that should be hardwired.

LBOOT I Link Boot. Must be tied to GND.
BMS

CLKIN I Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN. CLKIN may

RESET

TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST

EMU

ICSA O Reserved. Leave unconnected.
VDD P Power Supply. Nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins)
GND G Power Supply Return. (30 pins)
NC Do Not Connect. Reserved pins which must be left open and unconnected.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open-Drain,

T = Three-State (when SBTS

I/O/T* Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,

LBOOT = 0). In a multiprocessor system, BMS
booting will occur and that ADSP-21061 will begin executing instructions from external memory. See table
below. This input is a system configuration selection that should be hardwired. *Three-statable only in
EPROM boot mode (when BMS

EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS
0 0 1(Input) Host Processor.
0 0 0 (Input) No Booting. Processor executes from external memory.

not be halted, changed, or operated below the minimum specified frequency.

I/A Processor Reset. Resets the ADSP-21061 to a known state and begins program execution at the program

memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.

resistor.

I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held

low for proper operation of the ADSP-21061. TRST has a 20 kΩ internal pull-up resistor.

O Emulation Status. Must be connected to the ADSP-21061 EZ-ICE target board connector only. EMU has a

50 kΩ internal pull-up resistor.

is asserted, or when the ADSP-21061 is a bus slave)

is an output).

inputs determine booting mode. See the table in the BMS pin

is output by the bus master. Input: When low, indicates that no

to EPROM chip select.)

Rev. C | Page 12 of 56 | July 2007

ADSP-21061/ADSP-21061L

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and
GND signals be made accessible on the target system via a
14-pin connector (a 2-row, 7-pin strip header) such as that
shown in Figure 5. The EZ-ICE probe plugs directly onto this
connector for chip-on-board emulation. You must add this con­nector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZ­ICE connector and the farthest device sharing the EZ-ICE JTAG
pin should be limited to 15 inches maximum for guaranteed
operation. This length restriction must include EZ-ICE JTAG
signals that are routed to one or more ADSP-2106x devices, or a
combination of ADSP-2106x devices and other JTAG devices
on the chain.

12

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator

3 4

56

7 8

910

11 12

BTDI

13 14

GND

TOP VIE W

(Jumpers in Place)

9

The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca­tion—Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inches in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST

, and BTDI signals are provided so that the test access

port can also be used for board-level testing.
When the connector is not being used for emulation, place

jumpers between the Bxxx pins and the xxx pins as shown in

Figure 5. If you are not going to use the test access port for

board testing, tie BTRST
V

. The TRST pin must be asserted (pulsed low) after power-

DD

up (through BTRST

to GND and tie or pull up BTCK to

on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.

EMU

GND

TMS

TCK

TRST

TDI

TDO

The JTAG signals are terminated on the EZ-ICE probe as shown
in Table 3.

Table 3. Core Instruction Rate/CLKIN Ratio Selection

Signal Termination

TMS Driven Through 22 Ω Resistor (16 mA Driver)
TCK Driven at 10 MHz Through 22 Ω Resistor (16 mA

Driver)

1

TRST

Active Low Driven Through 22 Ω Resistor (16 mA

Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
TDI Driven by 22 Ω Resistor (16 mA Driver)
TDO One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU

Active Low, 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

1

TRST is driven low until the EZ-ICE probe is turned on by the emulator at software

startup. After software startup, is driven high.

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.

The emulator only uses CLKIN when directed to perform oper­ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces­sors, simply tie Pin 4 of the EZ-ICE header to ground.

If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-21061 processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces­sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU

should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-21061s (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See

Figure 7 below and “JTAG Clock Tree” and “Clock Distribu-

tion” in the “High Frequency Design Considerations” section of
the ADSP-21061 SHARC User’s Manual, Revision 2.1.)

If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina­tion on TCK and TMS. TDI, TDO, EMU,

and TRST are not

critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the

ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.

Rev. C | Page 13 of 56 | July 2007

ADSP-21061/ADSP-21061L

OTHER

JTAG

CONTROLLER

JTAG

DEVICE

(OPTIONAL)

TDI

K
C
T

TDO TDO

T

S

S

M

R

T

T

EZ-ICE

JTAG

CONNECTOR

EMU

TRST

CLKIN

TDI

TCK
TMS

TDO

ADSP-2106x

TDI

K
C
T

OPTIONAL

#1

TDO

T

U

S

S

M

R

M
T

T

E

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

TDI TDO TDI TDO

5k⍀

*

TDI TDO

TDI TDO

TDI TDO

TDI TDO

ADSP-2106x

TDI

K
C

M

T

T

n

T

U

S

S

M

R

E

T

TDI

EMU

TCK
TMS

TRST

TDO

CLKIN

5k⍀

*

*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e,

EMU

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

SYSTEM

CLKIN

Rev. C | Page 14 of 56 | July 2007

ADSP-21061/ADSP-21061L

ADSP-21061 SPECIFICATIONS

OPERATING CONDITIONS (5 V)

K Grade

Parameter Description Min Max Unit

V

DD

T

CASE

1

V

1

IH

2

2

V

IH

2

1,

V

IL

1

Applies to input and bidirectional pins: DATA

TFS1, RFS0, RFS1, EBOOT, BMS

2

Applies to input pins: CLKIN, RESET, TRST.

Supply Voltage 4.75 5.25 V

Case Operating Temperature 0 85 °C

High Level Input Voltage @ VDD = Max 2.0 VDD + 0.5 V

High Level Input Voltage @ VDD = Max 2.2 VDD + 0.5 V

Low Level Input Voltage @ VDD = Min –0.5 +0.8 V

, ADDR

, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

47–0

, RD, WR, SW , ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR

31–0

6–1

, ID

2–0

, RPBA, CPA, TFS0,

ELECTRICAL CHARACTERISTICS (5 V)

Parameter Description Test Conditions Min Max Unit

1, 2

V

OH

1, 2

V

OL

3, 4

I

IH

3

I

IL

4

I

ILP

5, 6, 7, 8

I

OZH

5

I

OZL

I

OZHP

7

I

OZLC

9

I

OZLA

8

I

OZLAR

6

I

OZLS

10, 11

C

IN

1

Applies to output and bidirectional pins: DATA

BR

, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS, TDO, EMU, ICSA.

6–1

2

See “Output Drive Currents” for typical drive current capabilities.

3

Applies to input pins: ACK, SBTS, IRQ

4

Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI, EMU.

5

Applies to three-statable pins: DATA

TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
mastership.)

6

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

7

Applies to CPA pin.

8

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID

is not requesting bus mastership).

9

Applies to ACK pin when keeper latch enabled.

10

Applies to all signal pins.

11

Guaranteed but not tested.

High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 4.1 V

Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V

High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA

Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA

Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA

Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA

Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA

Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA

Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA

Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA

Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA

Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA

Input Capacitance fIN = 1 MHz, T

, ADDR

47-0

, HBR, CS, DMAR1, DMAR2, ID

2–0

47–0

, ADDR

31–0

, MS

, 3-0, MS

31-0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG

3–0

, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

3–0

, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

2–0

= 25°C, VIN = 2.5 V 4.7 pF

CASE

, HBG, REDY, DMAG1, DMAG2, BMS, BR

3–0

= 001 and another ADSP-21061 is not requesting bus

2–0

= 001 and another ADSP-21061L

2–0

6–1

, TFSx, RFSx,

Rev. C | Page 15 of 56 | July 2007

ADSP-21061/ADSP-21061L

INTERNAL POWER DISSIPATION (5 V)

These specifications apply to the internal power portion of VDD
only. See the Power Dissipation section of this data sheet for cal­culation of external supply current and total supply current. For

Operation Peak Activity (I

a complete discussion of the code used to measure power dissi­pation, see the technical note “SHARC Power Dissipation
Measurements.”

Specifications are based on the operating scenarios:

) High Activity (I

DDINPEAK

) Low Activity (I

DDINHIGH

Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access 2 per Cycle (DM and PM) 1 per Cycle (DM) None
Internal Memory DMA 1 per Cycle 1 per 2 Cycles 1 per 2 Cycles

To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro­gram spends in that state:

%PEAK I
%IDLE I

DDINPEAK

DDIDLE

+ %HIGH I

DDINHIGH

= power consumption

+ %LOW I

DDINLOW

+

Parameter Test Conditions Max Unit

4

5

DDINPEAK

1

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 20 ns, VDD = Max

2

tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max
tCK = 20 ns, VDD = Max

3

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 20 ns, VDD = Max
VDD = Max

VDD = Max

represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power

is a composite average based on a range of low activity code.

DDINLOW

595
680
850

460
540
670

270
320
390

200
55

mA
mA

mA
mA

mA
mA

mA
mA

I

I

I

I
I

1

The test program used to measure I

2

I

3

I

4

Idle denotes ADSP-21061L state during execution of IDLE instruction.

5

Idle16 denotes ADSP-2106x state during execution of IDLE16 instruction.

Supply Current (Internal)

DDINPEAK

Supply Current (Internal)

DDINHIGH

Supply Current (Internal)

DDINLOW

Supply Current (Idle)

DDIDLE

Supply Current (Idle16)

DDIDLE

measurements made using typical applications are less than specified.

is a composite average based on a range of high activity code. I

DDINHIGH

is a composite average based on a range of low activity code.

DDINLOW

DDINLOW

)

Rev. C | Page 16 of 56 | July 2007

ADSP-21061/ADSP-21061L

EXTERNAL POWER DISSIPATION (5 V)

Total power dissipation has two components, one due to inter­nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc­tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:

P

= I

INT

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

—the number of output pins that switch during each cycle

(O)
—the maximum frequency at which they can switch (f)
—their load capacitance (C)
—their voltage swing (V

and is calculated by:
PEXT = O

DDIN

× V

DD

×

C × V

DD

)

DD

2

× f

The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can
drive high and low at a maximum rate of 1/(2t

). The write

CK

strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t

Example: Estimate P

), but selects can switch on each cycle.

CK

with the following assumptions:

EXT

• A system with one bank of external data memory RAM
(32-bit)

• Four 128k × 8 RAM chips are used, each with a load of
10 pF

• External data memory writes occur every other cycle, a rate
of 1/(4t

• The instruction cycle rate is 40 MHz (t

The P

EXT

), with 50% of the pins switching

CK

= 25 ns)

CK

equation is calculated for each class of pins that can

drive:

Table 4. External Power Calculations

Pin Type No. of Pins % Switching × C × f × V

DD

2

= P

EXT

Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 W
MS0
WR

10 × 44.7 pF × 10 MHz × 25 V = 0.000 W

1— × 44.7 pF × 20 MHz × 25 V = 0.022 W
Data 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 W
ADDRCLK 1 — × 4.7 pF × 20 MHz × 25 V = 0.002 W
P

= 0.167 W

EXT

. Select pins

CK

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:

P

= P

TOTAL

EXT

+ (I

Note that the conditions causing a worst-case P
from those causing a worst-case P

DDIN2

× 5.0 V)

. Maximum P

INT

are different

EXT

cannot

INT

occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.

Rev. C | Page 17 of 56 | July 2007