ANALOG DEVICES ADSP-21060, ADSP-21060L, ADSP-21062, ADSP-21062L, ADSP-21060C Service Manual

SHARC Processor

MULT

BARREL

SERIAL PORTS

(2)

LINK PORTS

(6)

4

6

6

36

IOP

REGISTERS

(MEMORY
MAPPED)

CONTROL,

STATUS AND

DATA BUFFERS

I/O PROCESSOR

TIMER

INSTRUCTION

CACHE

ADDR DATA

DATA ADDR

ADDR DATA ADDR

TWO INDEPENDENT

DUAL-PORTED BLOCKS

PROCESSOR PORT I/O PORT

DUAL-PORTED SRAM

JTAG

TEST AND

EMULATION

7

HOST PORT

ADDR BUS

MUX

IOA

17

IOD

48

MULTIPROCESSOR

INTERFACE

EXTERNAL

PORT

DATA BU S

MUX

48

32

24

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DAG1

32

48

40/32

CORE PROCESSOR

PROGRAM

SEQUENCER

BLOCK 0

BLOCK 1

8  4  32

DAG2

8  4  24

32  48-BIT

PM ADDRESS BUS

DATA

CONTROLLER

DMA

DATA

REGISTER

FILE

16  40-BIT

ALU

SHIFTER

S

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

SUMMARY

High performance signal processor for communications,

graphics and imaging applications

Super Harvard Architecture

4 independent buses for dual data fetch, instruction fetch,

and nonintrusive I/O

32-bit IEEE floating-point computation units—multiplier,

ALU, and shifter

Dual-ported on-chip SRAM and integrated I/O peripherals—a

complete system-on-a-chip
Integrated multiprocessing features
240-lead thermally enhanced MQFP_PQ4 package, 225-ball

plastic ball grid array (PBGA), 240-lead hermetic CQFP

package
RoHS compliant packages

KEY FEATURES—PROCESSOR CORE

40 MIPS, 25 ns instruction rate, single-cycle instruction

execution
120 MFLOPS peak, 80 MFLOPS sustained performance
Dual data address generators with modulo and bit-reverse

addressing)
Efficient program sequencing with zero-overhead looping:

Single-cycle loop setup
IEEE JTAG Standard 1149.1 Test Access Port and on-chip

emulation
32-bit single-precision and 40-bit extended-precision IEEE

floating-point data formats or 32-bit fixed-point data

format

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Figure 1. Functional Block Diagram

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

PARALLEL COMPUTATIONS

Single-cycle multiply and ALU operations in parallel with

dual memory read/writes and instruction fetch

Multiply with add and subtract for accelerated FFT butterfly

computation

UP TO 4M BIT ON-CHIP SRAM

Dual-ported for independent access by core processor and

DMA

OFF-CHIP MEMORY INTERFACING

4 gigawords addressable
Programmable wait state generation, page-mode DRAM

support

DMA CONTROLLER

10 DMA channels for transfers between ADSP-2106x internal

memory and external memory, external peripherals, host
processor, serial ports, or link ports

Background DMA transfers at up to 40 MHz, in parallel with

full-speed processor execution

HOST PROCESSOR INTERFACE TO 16- AND 32-BIT MICROPROCESSORS

Host can directly read/write ADSP-2106x internal memory

and IOP registers

MULTIPROCESSING

Glueless connection for scalable DSP multiprocessing

architecture

Distributed on-chip bus arbitration for parallel bus connect

of up to six ADSP-2106xs plus host

Six link ports for point-to-point connectivity and array

multiprocessing
240 MBps transfer rate over parallel bus
240 MBps transfer rate over link ports

SERIAL PORTS

Two 40 Mbps synchronous serial ports with companding

hardware
Independent transmit and receive functions

Table 1. ADSP-2106x SHARC Processor Family Features

Feature ADSP-21060 ADSP-21062 ADSP-21060L ADSP-21062L ADSP-21060C ADSP-21060LC

SRAM 4M bits 2M bits 4M bits 2M bits 4M bits 4M bits

Operating
Voltage 5 V 5 V 3.3 V 3.3 V 5 V 3.3 V

Instruction
Rate

Package

33 MHz
40 MHz

MQFP_PQ4
PBGA

33 MHz
40 MHz

MQFP_PQ4
PBGA

33 MHz
40 MHz

MQFP_PQ4
PBGA

33 MHz
40 MHz

MQFP_PQ4
PBGA CQFP CQFP

33 MHz
40 MHz

33 MHz
40 MHz

Rev. G | Page 2 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

CONTENTS

Summary ............................................................... 1

Revision History ...................................................... 3

General Description ................................................. 4

SHARC Family Core Architecture ............................ 4

Memory and I/O Interface Features ........................... 5

Development Tools ............................................... 8

Evaluation Kit ...................................................... 9

Designing an Emulator-Compatible DSP Board

(Target) ........................................................... 9

Additional Information .......................................... 9

Related Signal Chains ............................................ 9

Pin Function Descriptions ........................................ 10

Target Board Connector for EZ-ICE Probe ................ 13

ADSP-21060/ADSP-21062 Specifications ..................... 15

Operating Conditions (5 V) .................................... 15

Electrical Characteristics (5 V) ................................ 15

Internal Power Dissipation (5 V) ............................. 16

REVISION HISTORY

8/10—Rev. F to Rev. G

Added new section, Related Signal Chains.......................9

Revised Table 14 ..................................................... 25

Revised Table 15 ..................................................... 26

Revised Table 28 ..................................................... 43

Clarification of Table 41 Title..................................... 54

Clarification of Table 42 Title..................................... 55

Changes to Ordering Guide ....................................... 62

External Power Dissipation (5 V) ............................ 17

ADSP-21060L/ADSP-21062L Specifications ................. 18

Operating Conditions (3.3 V) ................................. 18

Electrical Characteristics (3.3 V) ............................. 18

Internal Power Dissipation (3.3 V) .......................... 19

External Power Dissipation (3.3 V) .......................... 20

Absolute Maximum Ratings ................................... 20

ESD Caution ...................................................... 21

Package Marking Information ................................ 21

Timing Specifications ........................................... 21

Test Conditions .................................................. 48

Environmental Conditions .................................... 51

225-Ball PBGA Ball Configuration .............................. 52

240-Lead MQFP_PQ4/CQFP Pin Configuration . ........... 54

Outline Dimensions ................................................ 56

Surface-Mount Design .......................................... 61

Ordering Guide ..................................................... 62

Rev. G | Page 3 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

3

4

RESET JTAG

6

ADSP-2106x

BMS

1 3 CLOCK

LINK

DEVICES

(6 MAX)

(OPTIONAL)

CS

BOOT

EPROM

(OPTIONAL)

MEMO RY-

MAPPED
DEVICES

(OPTIONAL)

OE

DATA

DMA DEVICE

(OPTIONAL)

DATA

ADDR

DATA

HOST

PROCE SSOR

INTERFACE
(OPTIONAL)

CS

RD

PAGE

ADRCLK

ACK

BR1–6

DMAR1–2

CLKIN

IRQ2–0

LxCLK

TCLK0

RPBA

EBOOT

LBOOT

FLAG3–0

TIMEXP

LxACK
LxDAT3–0

DR0

DT0

RSF0

TFS0

RCLK0

TCLK1

DR1

DT1

RSF1

TFS1

RCLK1

ID2–0

SERIAL

DEVICE

(OPTIONAL)

SERIAL
DEVICE

(OPTIONAL)

PA

REDY

HBG

HBR

DMAG1–2

SBTS

MS3–0

WR

DATA47–0

DATA

ADDR

CS

ACK

WE

ADDR31–0

D

A

T

A

C

O

N

T

R

O

L

A

D

D

R

E

S

S

ADDR

GENERAL DESCRIPTION

The ADSP-2106x SHARC®—Super Harvard Architecture Com­puter—is a 32-bit signal processing microcomputer that offers
high levels of DSP performance. The ADSP-2106x builds on the
ADSP-21000 DSP core to form a complete system-on-a-chip,
adding a dual-ported on-chip SRAM and integrated I/O periph­erals supported by a dedicated I/O bus.

Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates at
40 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table 2 shows perfor­mance benchmarks for the ADSP-2106x.

The ADSP-2106x SHARC represents a new standard of integra­tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea­tures including up to 4M bit SRAM memory (see Table 1), a
host processor interface, DMA controller, serial ports and link
port, and parallel bus connectivity for glueless DSP
multiprocessing.

Table 2. Benchmarks (at 40 MHz)

Benchmark Algorithm Speed Cycles

1024 Point Complex FFT (Radix 4, with

0.46 μs 18,221

reversal)
FIR Filter (per tap) 25 ns 1
IIR Filter (per biquad) 100 ns 4
Divide (y/x) 150 ns 6
Inverse Square Root 225 ns 9
DMA Transfer Rate 240 Mbytes/s

The ADSP-2106x continues SHARC’s industry-leading stan­dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.

The block diagram on Page 1 illustrates the following architec­tural features:

• Computation units (ALU, multiplier and shifter) with a
shared data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro­cessor cycle

•Interval timer

•On-chip SRAM

• External port for interfacing to off-chip memory and
peripherals

• Host port and multiprocessor Interface

• DMA controller

Rev. G | Page 4 of 64 | August 2010

• Serial ports and link ports

• JTAG Test Access Port

Figure 2. ADSP-2106x System Sample Configuration

SHARC FAMILY CORE ARCHITECTURE

The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-2106x processors
are code- and function-compatible with the ADSP-21020.

Independent, Parallel Computation Units

The arithmetic/logic unit (ALU), multiplier and shifter all per­form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi­function instructions execute parallel ALU and multiplier oper­ations. These computation units support IEEE 32-bit single­precision floating-point, extended precision 40-bit floating­point, and 32-bit fixed-point data formats.

Data Register File

A general–purpose data register file is used for transferring data
between the computation units and the data buses, and for stor­ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Single-Cycle Fetch of Instruction and Two Operands

The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro­gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With its separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.

Instruction Cache

The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.

Data Address Generators with Hardware Circular Buffers

The ADSP-2106x’s two data address generators (DAGs) imple­ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem­ory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example, the
ADSP-2106x can conditionally execute a multiply, an add, a
subtract and a branch, all in a single instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-2106x processors add the following architectural
features to the SHARC family core.

Dual-Ported On-Chip Memory

The ADSP-21062/ADSP-21062L contains two megabits of on­chip SRAM, and the ADSP-21060/ADSP-21060L contains
4M bits of on-chip SRAM. The internal memory is organized as
two equal sized blocks of 1M bit each for the ADSP-21062/
ADSP-21062L and two equal sized blocks of 2M bits each for
the ADSP-21060/ADSP-21060L. Each can be configured for dif­ferent combinations of code and data storage. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle.

On the ADSP-21062/ADSP-21062L, the memory can be config­ured as a maximum of 64k words of 32-bit data, 128k words of
16-bit data, 40k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to two megabits. All of
the memory can be accessed as 16-bit, 32-bit, or 48-bit words.

On the ADSP-21060/ADSP-21060L, the memory can be config­ured as a maximum of 128k words of 32-bit data, 256k words of
16-bit data, 80k words of 48-bit instructions (or 40-bit data), or
combinations of different word sizes up to four megabits. All of
the memory can be accessed as 16-bit, 32-bit or 48-bit words.

A 16-bit floating-point storage format is supported, which effec­tively doubles the amount of data that can be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float­ing-point formats is done in a single instruction.

While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-2106x’s external port.

On-Chip Memory and Peripherals Interface

The ADSP-2106x’s external port provides the processor’s inter­face to off-chip memory and peripherals. The 4-gigaword off­chip address space is included in the ADSP-2106x’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.

Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim­plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external mem­ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold and disable time
requirements.

Host Processor Interface

The ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit­tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x’s exter­nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.

The host processor requests the ADSP-2106x’s external bus with
the host bus request (HBR
(REDY) signals. The host can directly read and write the inter­nal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.

), host bus grant (HBG), and ready

Rev. G | Page 5 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ADDR31–0

CPA

BMS

C

O

N

T

R

O

L

ADSP-2106x #1

5

CONTROL

ADSP-2106x #2

ADDR31–0

CONTROL

ADSP-2106x #3

5

ID2–0

RESET

RPBA

CLKIN

ID2–0

RESET

RPBA

ID2–0

RESET

RPBA

CLKIN

ADSP-2 106x #6
ADSP-2 106x #5
ADSP-2 106x #4

CLOCK

RESET

ADDR

DATA

HOSTPROCESSOR
INTERFACE (O PTIONAL)

ACK

GLOBAL MEMORY
AND
PERIPHERAL (O PTIONAL)

OE

ADDR

DATA

CS

ADDR

DATA

BOOT EPROM (OPTIONAL)

RDx

MS3–0

SBTS

CS

ACK

ADDR31–0

CLKIN

3

001

PAGE

3

010

3

011

BR1

BR2–6

REDY

HBG

HBR

CS

WE

WRx

5

C

O

N

T

R

O

L

A

D

D

R

E

S

S

D

A

T

A

C

O

N

T

R

O

L

A

D

D

R

E

S

S

D

A

T

A

DATA47–0

BR1–2, BR4–6

BR3

DATA47–0

BR1, BR3–6

BR2

DATA47–0

BUS

PRIORITY

CPA

Figure 3. Shared Memory Multiprocessing System

Rev. G | Page 6 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

0x0004 0000

0x0010 0000

0x0008 0000

0x0018 0000

0x0012 0000

0x0028 0000

0x0038 0000

0x0000 0000

0x0002 0000

0x0040 0000

BANK 1

MS0

BANK 2

MS1

BANK 3

MS2

MS3

IOP REGISTERS

SHORT WORD ADDRESSING

(16-BIT DATA WORDS)

NORMAL WORD ADDRESSING

(32-BIT DATA WORDS

48-BIT INSTRUCTION WORDS)

ADDRESS

BANK 0

SDRAM

(OPTIONAL)

0x0FFF FFFF

NONBANKED

NOTE: BANK SIZES ARE SELECTED BY
MSIZE BITS IN THE SYSCON REGISTER

0x0030 0000

INTERNAL
MEMORY
SPACE

MULTIPROCESSOR
MEMOR Y
SPACE

ADDRESS

INTERNAL MEMORY SPACE

WITH ID = 001

0x003F FFFF

EXTERNAL
MEMORY
SPACE

INTERNAL MEMORY SPACE

WITH ID = 010

INTERNAL MEMORY SPACE

WITH ID = 011

INTERNAL MEMORY SPACE

WITH ID = 100

INTERNAL MEMORY SPACE

WITH ID = 101

INTERNAL MEMORY SPACE

WITH ID = 110

BROADCASTWRITE

TO ALL ADSP-21061s

DMA Controller

The ADSP-2106x’s on-chip DMA controller allows zero-over­head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul­taneously executing its program instructions.

DMA transfers can occur between the ADSP-2106x’s internal
memory and external memory, external peripherals, or a host
processor. DMA transfers can also occur between the ADSP­2106x’s internal memory and its serial ports or link ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.

Ten channels of DMA are available on the ADSP-2106x—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-2106xs, memory, or I/O transfers). Four additional link
port DMA channels are shared with Serial Port 1 and the exter­nal port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can

control two DMA channels using DMA request/grant lines
(DMAR1–2

, DMAG1–2). Other DMA features include inter­rupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.

Multiprocessing

The ADSP-2106x offers powerful features tailored to multipro­cessor DSP systems. The unified address space (see Figure 4)
allows direct interprocessor accesses of each ADSP-2106x’s
internal memory. Distributed bus arbitration logic is included
on-chip for simple, glueless connection of systems containing
up to six ADSP-2106xs and a host processor. Master processor
changeover incurs only one cycle of overhead. Bus arbitration is
selectable as either fixed or rotating priority. Bus lock allows
indivisible read-modify-write sequences for semaphores. A vec­tor interrupt is provided for interprocessor commands. Maxi­mum throughput for interprocessor data transfer is
240M bytes/s over the link ports or external port. Broadcast
writes allow simultaneous transmission of data to all
ADSP-2106xs and can be used to implement reflective
semaphores.

Figure 4. Memory Map

Rev. G | Page 7 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Link Ports

The ADSP-2106x features six 4-bit link ports that provide addi­tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits of data per cycle. Link­port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems.

The link ports can operate independently and simultaneously,
with a maximum data throughput of 240M bytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.

Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.

Program Booting

The internal memory of the ADSP-2106x can be booted at sys­tem power-up from an 8-bit EPROM, a host processor, or
through one of the link ports. Selection of the boot source is
controlled by the BMS (boot memory select), EBOOT (EPROM
Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host
processors can be used for booting. The processor also sup­ports a no-boot mode in which instruction execution is sourced
from the external memory.

DEVELOPMENT TOOLS

The ADSP-2106x is supported by a complete set of
CROSSCORE
Devices emulators and VisualDSP++
ment. The same emulator hardware that supports other SHARC
processors also fully emulates the ADSP-2106x.

The VisualDSP++ project management environment lets pro­grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-2106x
SHARC DSP has architectural features that improve the effi­ciency of compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea­tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa­tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com­plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta­tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

®

†

software development tools, including Analog

®

‡

development environ-

the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi­ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source
and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and
stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-2106x
development tools, including the color syntax highlighting in
the VisualDSP++ editor. This capability permits:

• Control in how the development tools process inputs and
generate outputs

• Maintenance of a one-to-one correspondence with the
tools’ command line switches

The VisualDSP++ kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem­ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre­emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen­eration of various VDK-based objects, and visualizing the
system state, when debugging an application that uses the VDK.

Use the expert linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza­tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with a drag of
the mouse, and examine run-time stack and heap usage. The

Rev. G | Page 8 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

expert linker is fully compatible with existing linker definition
file (LDF), allowing the developer to move between the graphi­cal and textual environments.

In addition to the software development tools available from
Analog Devices, third parties provide a wide range of tools sup­porting the SHARC processor family. Third party software tools
include DSP libraries, real-time operating systems, and block
diagram design tools.

EVALUATION KIT

®

Analog Devices offers a range of EZ-KIT Lite
forms to use as a cost-effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user’s PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces­sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a stand­alone unit, without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus­tom-defined system. Connecting an Analog Devices JTAG
emulator to the EZ-KIT Lite board enables high speed, nonin­trusive emulation.

†

evaluation plat-

Reference on the Analog Devices website (www.analog.com)—
use site search on “EE-68.” This document is updated regularly
to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-2106x
architecture and functionality. For detailed information on the
ADSP-21000 family core architecture and instruction set, refer
to the ADSP-2106x SHARC User’s Manual, Revision 2.1.

RELATED SIGNAL CHAINS

A signal chain is a series of signal-conditioning electronic com­ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the

Glossary of EE Terms on the Analog Devices website.

Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the

www.analog.com website.

The Application Signal Chains page in the Circuits from the

TM

Lab

site (http://www.analog.com/signalchains) provides:

• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications

• Drill down links for components in each chain to selection
guides and application information

• Reference designs applying best practice design techniques

DESIGNING AN EMULATOR-COMPATIBLE DSP BOARD (TARGET)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter­face—the emulator does not affect target system loading or tim­ing. The emulator uses the TAP to access the internal features of
the DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers. The
DSP must be halted to send data and commands, but once an
operation has been completed by the emulator, the DSP system
is set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

Rev. G | Page 9 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

PIN FUNCTION DESCRIPTIONS

The ADSP-2106x pin definitions are listed below. Inputs identi­fied as synchronous (S) must meet timing requirements with
respect to CLKIN (or with respect to TCK for TMS, TDI).
Inputs identified as asynchronous (A) can be asserted asynchro­nously to CLKIN (or to TCK for TRST

).

Unused inputs should be tied or pulled to VDD or GND, except
for ADDR31–0, DATA47–0, FLAG3–0, and inputs that have
internal pull-up or pull-down resistors (CPA

, ACK, DTx, DRx,
TCLKx, RCLKx, LxDAT3–0, LxCLK, LxACK, TMS, and
TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.

Table 3. Pin Descriptions

Pin Type Function

ADDR31–0 I/O/T External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on these

pins. In a multiprocessor system, the bus master outputs addresses for read/write of the internal memory
or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host processor or multi­processing bus master is reading or writing its internal memory or IOP registers.

DATA47–0 I/O/T External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit single-

precision floating-point data and 32-bit fixed-point data is transferred over bits 47–16 of the bus. 40-bit
extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short word data is
transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over bits 23–16. Pull-up
resistors on unused DATA pins are not necessary.

MS3–0

RD I/O/T Memory Read Strobe. This pin is asser ted (low) when the ADSP-2106x reads from external memory devices

WR

PAG E O /T DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page boundary

ADRCLK O/T Clock Output Reference. In a multiprocessing system, ADRCLK is output by the bus master.
SW

A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

O/T Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of external

memory. Memory bank size must be defined in the ADSP-2106x’s system control register (SYSCON). The
MS3–0 lines are decoded memory address lines that change at the same time as the other address lines.
When no external memory access is occurring, the MS3–0
a conditional memory access instruction is executed, whether or not the condition is true. MS0 can be used
with the PAGE signal to implement a bank of DR AM memory (Bank 0). In a multiprocessing system the MS3–0
lines are output by the bus master.

or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-2106xs) must
assert RD to read from the ADSP-2106x’s internal memory. In a multiprocessing system, RD is output by the
bus master and is input by all other ADSP-2106xs.

I/O/T Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x wri tes to external memory devices

or to the internal memory of other ADSP-2106xs. External devices must assert WR
2106x’s internal memory. In a multiprocessing system, WR is output by the bus master and is input by all
other ADSP-2106xs.

has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control register (WAIT).
DRAM can only be implemented in external memory Bank 0; the PAGE signal can only be activated for Bank
0 accesses. In a multiprocessing system, PAGE is output by the bus master

I/O/T Synchronous Write Select. T hi s si g na l i s u s ed t o interface the ADSP-2106x to synchronous memory devices

(including other ADSP-2106xs). The ADSP-2106x asserts SW
impending write cycle, which can be aborted if WR
instruction). In a multiprocessing system, SW is output by the bus master and is input by all other
ADSP-2106xs to determine if the multiprocessor memory access is a read or write. SW
time as the address output. A host processor using synchronous writes must assert this pin when writing to
the ADSP-2106x(s).

lines are inactive; they are active however when

to write to the ADSP-

(low) to provide an early indication of an

is not later asserted (e.g., in a conditional write

is asserted at the same

Rev. G | Page 10 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Table 3. Pin Descriptions (Continued)

Pin Type Function

ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory

access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an
external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous
access of its internal memory. In a multiprocessing system, a slave ADSP-2106x deasserts the bus master’s
ACK input to add wait state(s) to an access of its internal memory. The bus master has a keeper latch on its
ACK pin that maintains the input at the level to which it was last driven.

SBTS

IRQ2–0
FLAG3–0 I/O/A Flag Pins. Each is configured via control bits as either an input or output. As an input, they can be tested as

TIMEXP O Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to zero.
HBR

HBG

CS
REDY O (O/D) Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchronous access

DMAR2–1
DMAG2–1
BR6–1

ID2–0

RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus

CPA

DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 kΩ internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 kΩ internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

I/S Suspend Bus Three-State. External devices can assert SBTS (low) to place the external bus address, data,

selects, and strobes in a high impedance state for the following cycle. If the ADSP-2106x attempts to access
external memory while SBTS is asserted, the processor will halt and the memory access will not be completed
until SBTS
or used with a DRAM controller.

I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

a condition. As an output, they can be used to signal external peripherals.

I/A Host Bus Request. This pin must be asserted by a host processor to request control of the ADSP-2106x’s

external bus. When HBR
relinquish the bus and assert HBG. To relinquish the bus, the ADSP-2106x places the address, data, select
and strobe lines in a high impedance state. HBR
multiprocessing system.

I/O Host Bus Grant. Acknowledges a bus request, indicating that the host processor may take control of the

external bus. HBG is asser ted (held low) by the ADSP-2106x until HBR is released. In a multiprocessing system,
HBG

I/A Chip Select. Asserted by host processor to select the ADSP-2106x.

of its internal memory or IOP registers by a host. This pin is an open-drain output (O/D) by default; it can be
programmed in the ADREDY bit of the SYSCON register to be active drive (A/D). REDY will only be output if

the CS
I/A DMA Request 1 (DMA Channel 7) and DMA Request 2 (DMA Channel 8).
O/T DMA Grant 1 (DMA Channel 7) and DMA Grant 2 (DMA Channel 8).
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-ship. An

ADSP-2106x only drives its own BR

others. In a multiprocessor system with less than six ADSP-2106xs, the unused BR

high; the processor’s own BRx line must not be pulled high or low because it is an output.
O (O/D) Multiprocessing ID. Determines which multiprocessing bus request (BR1– BR6) is used by ADSP-2106x.

ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor systems. These

lines are a system configuration selection that should be hardwired or changed at reset only.

arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration

selection that must be set to the same value on every ADSP-2106x. If the value of RPBA is changed during

system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
I/O (O/D) Core Priority Access. Asserting its CPA pin allows the core processor of an ADSP-2106x bus slave to interrupt

background DMA transfers and gain access to the external bus. CPA

to all ADSP-2106xs in the system. The CPA

not required in a system, the CPA pin should be left unconnected.

is deasserted. SBTS should only be used to recover from host processor/ADSP-2106x deadlock,

is asserted in a multiprocessing system, the ADSP-2106x that is bus master will

has priority over all ADSP-2106x bus requests BR6–1 in a

is output by the ADSP-2106x bus master and is monitored by all others.

and HBR inputs are asserted.

x line (corresponding to the value of its ID2-0 inputs) and monitors all

x pins should be pulled

is an open drain output that is connected

pin has an internal 5 kΩ pull-up resistor. If core access priority is

Rev. G | Page 11 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Table 3. Pin Descriptions (Continued)

Pin Type Function

TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
LxDAT3–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 kΩ internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 kΩ internal pull-down resistor that is enabled or

disabled by the LPDRD bit of the LCOM register.

LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 kΩ internal pull-down resistor that is

enabled or disabled by the LPDRD bit of the LCOM register.

EBOOT I EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM.

When EBOOT is low, the LBOOT and BMS
description below. This signal is a system configuration selection that should be hardwired.

LBOOT I Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low,

the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS
description below. This signal is a system configuration selection that should be hardwired.

BMS

CLKIN I Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should

RESET I/A Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program

TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.
TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST

EMU
ICSA O Reserved, leave unconnected.
VDD P Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).
GND G Power Supply Return. (30 pins).
NC Do Not Connect. Reserved pins which must be left open and unconnected.
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,

T = Three-State (when SBTS

I/OT Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0).

In a multiprocessor system, BMS
occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This
input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot
mode (when BMS

EBOOT LBOOT BMS
1 0 Output EPROM (Connect BMS to EPROM chip select.)
0 0 1 (Input) Host Processor
0 1 1 (Input) Link Port
0 0 0 (Input) No Booting. Processor executes from external memory.
010 (Input) Reserved
1 1 x (Input) Reserved

not be halted, changed, or operated below the minimum specified frequency.

memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.

resistor.

I/A Test Reset (JTAG). Resets the test state machine. TRST must be asser ted (pulsed low) after power-up or held

low for proper operation of the ADSP-2106x. TRST

O Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.

is asserted, or when the ADSP-2106x is a bus slave)

is an output).

is output by the bus master. Input: When low, indicates that no booting will

inputs determine booting mode. See the table in the BMS pin

pin

Booting Mode

has a 20 kΩ internal pull-up resistor.

Rev. G | Page 12 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

TOP VIE W

13 14

11 12

910

9

7 8

56

3 4

12

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE® Emulator uses the IEEE

1149.1JTAG test access port of the ADSP-2106x to monitor and
control the target board processor during emulation. The
EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST

, TDI, TDO, EMU, and GND signals be made accessible
on the target system via a 14-pin connector (a 2-row 7-pin strip
header) such as that shown in Figure 5. The EZ-ICE probe plugs
directly onto this connector for chip-on-board emulation. You
must add this connector to your target board design if you
intend to use the ADSP-2106x EZ-ICE. The total trace length
between the EZ-ICE connector and the furthest device sharing
the EZ-ICE JTAG pin should be limited to 15 inches maximum
for guaranteed operation. This length restriction must include
EZ-ICE JTAG signals that are routed to one or more
ADSP-2106x devices, or a combination of ADSP-2106x devices
and other JTAG devices on the chain.

Figure 5. Target Board Connector for ADSP-2106x EZ-ICE Emulator

(Jumpers in Place)

The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca­tion—Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST

, and BTDI signals are provided so that the test access

port can also be used for board-level testing.

When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in

Figure 5. If you are not going to use the test access port for

board testing, tie BTRST
V

. The TRST pin must be asserted (pulsed low) after power-

DD

up (through BTRST
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.

to GND and tie or pull up BTCK to

on the connector) or held low for proper

Rev. G | Page 13 of 64 | August 2010

The JTAG signals are terminated on the EZ-ICE probe as shown
in Table 4.

Table 4. Core Instruction Rate/CLKIN Ratio Selection

Signal Termination

TMS Driven Through 22 Ω Resistor (16 mA Driver)
TCK Driven at 10 MHz Through 22 Ω Resistor (16 mA

Driver)

1

TRST

Active Low Driven Through 22 Ω Resistor (16 mA

Driver) (Pulled-Up by On-Chip 20 kΩ Resistor)
TDI Driven by 22 Ω Resistor (16 mA Driver)
TDO One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU

Active Low 4.7 kΩ Pull-Up Resistor, One TTL Load

(Open-Drain Output from the DSP)

1

TRST is driven low until the EZ-ICE probe is turned on by the emulator at software

start-up. After software start-up, is driven high.

Figure 6 shows JTAG scan path connections for systems that

contain multiple ADSP-2106x processors.

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform oper­ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces­sors, simply tie Pin 4 of the EZ-ICE header to ground.

If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-2106x processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces­sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU

should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-2106xs (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See

Figure 7 and “JTAG Clock Tree” and “Clock Distribution” in

the “High Frequency Design Considerations” section of the
ADSP-2106x User’s Manual, Revision 2.1.)

If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina­tion on TCK and TMS. TDI, TDO, EMU

and TRST are not

critical signals in terms of skew.

For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

T

R

S

T

E

M

U

T

R

S

T

ADSP-21 06x

#1

JTA G

DEVICE

(OPTIONAL)

ADSP-2106x

n

TDI

EZ-ICE

JTAG

CONNECTOR

OTHER

JTAG

CONTROLLER

OPTION AL

T

C

K

T

M

S

EMU

TMS

TCK

TDO

CLKIN

TRST

T

C

K

T

M

S

T

C

K

T

M

S

TDI

TDO

TDI

TDO TDO

TDI

T

R

S

T

T

R

S

T

E

M

U

E

M

U

SYSTEM

CLKIN

EMU

5kV

*

TDI TDO

5kV

TDI

EMU

TMS

TCK

TDO

TRST

CLKIN

*OPEN-DRAIN DRIVER OR EQUIVALENT, i.e.,

TDI TDO

TDI TDO

TDI TDO TDI TDO

TDI TDO

*

Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems

Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems

Rev. G | Page 14 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ADSP-21060/ADSP-21062 SPECIFICATIONS

Note that component specifications are subject to change
without notice.

OPERATING CONDITIONS (5 V)

A Grade C Grade K Grade

Parameter Description Min Max Min Max Min Max Unit

V

DD

T

CASE

1

1

V

IH

2

V

2

IH

2

1,

V

IL

1

Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA, TFS0,

TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.

2

Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS (5 V)

Parameter Description Test Conditions Min Max Unit

1, 2

V

OH

1, 2

V

OL

3, 4

I

IH

3

I

IL

4

I

ILP

5, 6, 7, 8

I

OZH

5, 9

I

OZL

9

I

OZHP

7

I

OZLC

10

I

OZLA

8

I

OZLAR

6

I

OZLS

11, 12

C

IN

1

Applies to output and bidirectional pins: DATA47–0, ADDR31-0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

BR6–1

2

See “Output Drive Currents” for typical drive current capabilities.

3

Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

4

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

5

Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,

TDO, EMU
mastership.)

6

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

7

Applies to CPA pin.

8

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL

is not requesting bus mastership).

9

Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.

10

Applies to ACK pin when keeper latch enabled.

11

Applies to all signal pins.

12

Guaranteed but not tested.

Supply Voltage 4.75 5.25 4.75 5.25 4.75 5.25 V
Case Operating Temperature –40 +85 –40 +100 –40 +85 °C
High Level Input Voltage @ VDD = Max 2.0 VDD + 0.5 2.0 VDD + 0.5 2.0 VDD + 0.5 V
High Level Input Voltage @ VDD = Max 2.2 VDD + 0.5 2.2 VDD + 0.5 2.2 VDD + 0.5 V
Low Level Input Voltage @ VDD = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 4.1 V
Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V
High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA
Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA
Input Capacitance fIN = 1 MHz, T

. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus

= 25°C, VIN = 2.5 V 4.7 pF

CASE

Rev. G | Page 15 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

INTERNAL POWER DISSIPATION (5 V)

These specifications apply to the internal power portion of VDD
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi­pation Measurements.”

Specifications are based on the operating scenarios.

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core memory Access 2 Per Cycle (DM and PM) 1 Per Cycle (DM) None
Internal Memory DMA 1 Per Cycle 1 Per 2 Cycles 1 Per 2 Cycles

To estimate power consumption for a specific application, use
the following equation where% is the amount of time your pro­gram spends in that state:

%PEAK I
%IDLE I

+%HIGH I

DDINPEAK

= Power Consumption

DDIDLE

DDINHIGH

+%LOW I

DDINLOW

+

Parameter Test Conditions Max Units

3

DDINPEAK

1

2

2

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max

745
850

575
670

340
390

mA
mA

mA
mA

mA
mA

VDD = Max 200 mA

represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power

is a composite average based on a range of low activity code.

DDINLOW

I

I

I

I

1

The test program used to measure I

2

I

3

Idle denotes ADSP-2106x state during execution of IDLE instruction.

Supply Current (Internal)

DDINPEAK

Supply Current (Internal)

DDINHIGH

Supply Current (Internal)

DDINLOW

Supply Current (Idle)

DDIDLE

measurements made using typical applications are less than specified.

is a composite average based on a range of high activity code. I

DDINHIGH

DDINLOW

)

Rev. G | Page 16 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

EXTERNAL POWER DISSIPATION (5 V)

Total power dissipation has two components, one due to inter­nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc­tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:

P

= I

INT

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle
(O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (V

and is calculated by:

P

EXT

The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can

× V

DDIN

= O × C × V

DD

DD

2

× f

DD

)

drive high and low at a maximum rate of 1/(2t
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t

Example: Estimate P

), but selects can switch on each cycle.

CK

with the following assumptions:

EXT

• A system with one bank of external data memory RAM
(32-bit)

• Four 128K × 8 RAM chips are used, each with a load of
10 pF

• External data memory writes occur every other cycle, a rate
of 1/(4t

), with 50% of the pins switching

CK

• The instruction cycle rate is 40 MHz (t

The P

equation is calculated for each class of pins that can

EXT

drive:

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:

P

= P

TOTAL

EXT

+ (I

DDIN

× 5.0 V)

2

Note that the conditions causing a worst-case P
from those causing a worst-case P

. Maximum P

INT

occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to

). The write

CK

= 25 ns)

CK

EXT

have 100% or even 50% of the outputs switching
simultaneously.

Table 5. External Power Calculations (5 V Devices)

Pin Type No. of Pins % Switching × C × f × V

DD

2

= P

EXT

Address 15 50 × 44.7 pF × 10 MHz × 25 V = 0.084 W
MS0
WR

10 × 44.7 pF × 10 MHz × 25 V = 0.000 W

1– × 44.7 pF × 20 MHz × 25 V = 0.022 W
Data 32 50 × 14.7 pF × 10 MHz × 25 V = 0.059 W
ADDRCLK 1 – × 4.7 pF × 20 MHz × 25 V = 0.002 W

. Select pins

CK

are different

cannot

INT

P

= 0.167 W

EXT

Rev. G | Page 17 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

ADSP-21060L/ADSP-21062L SPECIFICATIONS

Note that component specifications are subject to change
without notice.

OPERATING CONDITIONS (3.3 V)

A Grade C Grade K Grade

Parameter Description Min Max Min Max Min Max Unit

V

DD

T

CASE

1

1

V

IH

2

V

2

IH

2

1,

V

IL

1

Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA,

TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1

2

Applies to input pins: CLKIN, RESET, TRST

ELECTRICAL CHARACTERISTICS (3.3 V)

Parameter Description Test Conditions Min Max Unit

1, 2

V

OH

1, 2

V

OL

3, 4

I

IH

3

I

IL

4

I

ILP

5, 6, 7, 8

I

OZH

5, 9

I

OZL

9

I

OZHP

7

I

OZLC

10

I

OZLA

8

I

OZLAR

6

I

OZLS

11, 12

C

IN

1

Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,

, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.

BR6–1

2

See “Output Drive Currents” for typical drive current capabilities.

3

Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.

4

Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.

5

Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,

TDO, EMU
mastership.)

6

Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.

7

Applies to CPA pin.

8

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL

is not requesting bus mastership).

9

Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.

10

Applies to ACK pin when keeper latch enabled.

11

Applies to all signal pins.

12

Guaranteed but not tested.

Supply Voltage 3.15 3.45 3.15 3.45 3.15 3.45 V
Case Operating Temperature –40 +85 –40 +100 –40 +85 °C
High Level Input Voltage @ VDD = Max 2.0 VDD + 0.5 2.0 VDD + 0.5 2.0 VDD + 0.5 V
High Level Input Voltage @ VDD = Max 2.2 VDD + 0.5 2.2 VDD + 0.5 2.2 VDD + 0.5 V
Low Level Input Voltage @ VDD = Min –0.5 +0.8 –0.5 +0.8 –0.5 +0.8 V

High Level Output Voltage @ VDD = Min, IOH = –2.0 mA 2.4 V
Low Level Output Voltage @ VDD = Min, IOL = 4.0 mA 0.4 V
High Level Input Current @ VDD = Max, VIN = VDD Max 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 10 μA
Low Level Input Current @ VDD = Max, VIN = 0 V 150 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 10 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 10 μA
Three-State Leakage Current @ VDD = Max, VIN = VDD Max 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 1.5 mA
Three-State Leakage Current @ VDD = Max, VIN = 1.5 V 350 μA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 4.2 mA
Three-State Leakage Current @ VDD = Max, VIN = 0 V 150 μA
Input Capacitance fIN = 1 MHz, T

. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus

= 25°C, VIN = 2.5 V 4.7 pF

CASE

Rev. G | Page 18 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

INTERNAL POWER DISSIPATION (3.3 V)

These specifications apply to the internal power portion of VDD
only. For a complete discussion of the code used to measure
power dissipation, see the technical note “SHARC Power Dissi­pation Measurements.”

Specifications are based on the operating scenarios.

Operation Peak Activity (I

DDINPEAK

) High Activity (I

DDINHIGH

) Low Activity (I

Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core memory Access 2 Per Cycle (DM and PM) 1 Per Cycle (DM) None
Internal Memory DMA 1 Per Cycle 1 Per 2 Cycles 1 Per 2 Cycles

To estimate power consumption for a specific application, use
the following equation where % is the amount of time your pro­gram spends in that state:

%PEAK I
%IDLE I

+ %HIGH I

DDINPEAK

= Power Consumption

DDIDLE

DDINHIGH

+ %LOW I

DDINLOW

+

Parameter Test Conditions Max Units

3

DDINPEAK

1

2

2

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 30 ns, VDD = Max

= 25 ns, VDD = Max

t

CK

tCK = 30 ns, VDD = Max
tCK = 25 ns, VDD = Max

540
600

425
475

250
275

mA
mA

mA
mA

mA
mA

VDD = Max 180 mA

represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power

is a composite average based on a range of low activity code.

DDINLOW

I

I

I

I

1

The test program used to measure I

2

I

3

Idle denotes ADSP-2106xL state during execution of IDLE instruction.

Supply Current (Internal)

DDINPEAK

Supply Current (Internal)

DDINHIGH

Supply Current (Internal)

DDINLOW

Supply Current (Idle)

DDIDLE

measurements made using typical applications are less than specified.

is a composite average based on a range of high activity code. I

DDINHIGH

DDINLOW

)

Rev. G | Page 19 of 64 | August 2010

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

EXTERNAL POWER DISSIPATION (3.3 V)

Total power dissipation has two components, one due to inter­nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc­tion execution sequence and the data operands involved.
Internal power dissipation is calculated in the following way:

P

= I

INT

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

• the number of output pins that switch during each cycle
(O)

• the maximum frequency at which they can switch (f)

• their load capacitance (C)

• their voltage swing (V

and is calculated by:

P

EXT

The load capacitance should include the processor’s package
capacitance (CIN). The switching frequency includes driving
the load high and then back low. Address and data pins can

× V

DDIN

= O × C × V

DD

DD

2

× f

DD

)

drive high and low at a maximum rate of 1/(2t
strobe can switch every cycle at a frequency of 1/t
switch at 1/(2t

Example: Estimate P

), but selects can switch on each cycle.

CK

with the following assumptions:

EXT

• A system with one bank of external data memory RAM
(32-bit)

• Four 128K × 8 RAM chips are used, each with a load of
10 pF

• External data memory writes occur every other cycle, a rate
of 1/(4t

), with 50% of the pins switching

CK

• The instruction cycle rate is 40 MHz (t

The P

equation is calculated for each class of pins that can

EXT

drive:

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:

P

= P

TOTAL

EXT

+ (I

DDIN

× 5.0 V)

2

Note that the conditions causing a worst-case P
from those causing a worst-case P

. Maximum P

INT

occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to

). The write

CK

= 25 ns)

CK

EXT

CK

are different

INT

have 100% or even 50% of the outputs switching
simultaneously.

Table 6. External Power Calculations (3.3 V Devices)

Pin Type No. of Pins % Switching × C × f × V

DD

2

= P

EXT

Address 15 50 × 44.7 pF × 10 MHz × 10.9 V = 0.037 W
MS0
WR

10 × 44.7 pF × 10 MHz × 10.9 V = 0.000 W

1– × 44.7 pF × 20 MHz × 10.9 V = 0.010 W
Data 32 50 × 14.7 pF × 10 MHz × 10.9 V = 0.026 W
ADDRCLK 1 – × 4.7 pF × 20 MHz × 10.9 V = 0.001 W

P

EXT

. Select pins

cannot

= 0.074 W

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed Table 7 may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater

Table 7. Absolute Maximum Ratings

Parameter

Supply Voltage (V

) –0.3 V to +7.0 V –0.3 V to +4.6 V

DD

Input Voltage –0.5 V to V
Output Voltage Swing –0.5 V to V
Load Capacitance 200 pF 200 pF
Storage Temperature Range –65°C to +150°C–65°C to +150°C
Lead Temperature (5 seconds) 280°C280°C
Junction Temperature Under Bias 130°C130°C

Rev. G | Page 20 of 64 | August 2010

than those indicated in the operational sections of this specifica­tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ADSP-21060/ADSP-21060C

ADSP-21062

ADSP-21060L/ADSP-21060LC

ADSP-21062L

5 V 3.3 V

+ 0.5 V –0.5 V to VDD +0.5 V

DD

+ 0.5 V –0.5 V to VDD + 0.5 V

DD