Analog Devices ADM8696AN, ADM8697ARW, ADM8697ARU, ADM8696ARW, ADM8696ARU Datasheet

Microprocessor

a

FEATURES
Upgrade for ADM696/ADM697, MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance

0.7 V Normal, 7 V in Backup
400 nA Standby Current
Automatic Battery Backup Switching (ADM8696)
Fast On-Board Gating of Chip Enable Signals (ADM8697)
Voltage Monitor for Power Fail or Low Battery Warning
Also Available in TSSOP Package

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring

CC

V

BATT

V

CC

LL

OSC IN

OSC SEL

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

Supervisory Circuits

ADM8696/ADM8697

FUNCTIONAL BLOCK DIAGRAMS

BATT ON

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TRANSITION DETECTOR

1.3V

WATCHDOG

TIMER

ADM8696

V

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

GENERAL DESCRIPTION

The ADM8696/ADM8697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include µP reset, backup battery switchover, watchdog timer,
CMOS RAM write protection and power failure warning.

The ADM8696/ADM8697 are available in 16-pin DIP and small
outline packages (including TSSOP) and provide the following
functions:

1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The
put remains operational with V

as low as 1 V.

CC

RESET out-

2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.

3. Separate watchdog timeout and low line status outputs.

4. Adjustable reset and watchdog timeout periods.

5. A 1.3 V threshold detector for power fail warning, low battery
detection or to monitor a power supply other than VCC.

6. Battery backup switching for CMOS RAM, CMOS micro­processor or other low power logic (ADM8696).

7. Write protection of CMOS RAM or EEPROM (ADM8697).

CE

LL

OSC IN

OSC SEL

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

IN

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TIMER

WATCHDOG

TRANSITION DETECTOR

ADM8697

1.3V

CE

OUT

LOW LINE

RESET

RESET

WATCHDOG
OUTPUT (WDO)

POWER FAIL
OUTPUT (PFO)

The ADM8696/ADM8697 is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(0.7 mW), extremely fast Chip Enable gating (2 ns) and high re­liability.

RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini­mal voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

ADM8696/ADM8697–SPECIFICATIONS

P

arameter Min Typ Max Units Test Conditions/Comments

unless otherwise noted.)

(VCC = Full Operating Range, V

= +2.8 V, TA = T

BATT

VCC Operating Voltage Range 3.0 5.5 V
V

Operating Voltage Range 2.0 VCC – 0 3 V

BATT

BATTERY BACKUP SWITCHING (ADM8696)

V

Output Voltage VCC – 0.005 VCC – 0.0025 V I

OUT

VCC – 0.2 VCC – 0.125 V I

V

in Battery Backup Mode V

OUT

Supply Current (Excludes I

) 115 200 µAI

OUT

– 0.005 V

BATT

– 0.002 V I

BATT

Supply Current in Battery Backup Mode 0.4 1 µAVCC = 0 V, V
Battery Standby Current 5.5 V > VCC > V

= 1 mA

OUT

≤ 100 mA

OUT

= 250 µA, VCC < V

OUT

= 100 mA

OUT

BATT

= 2.8 V

+ 0.2 V

BATT

BATT

(+ = Discharge, – = Charge) –0.1 +0.02 µA
Battery Switchover Threshold 70 mV Power-Up
VCC – V

BATT

50 mV Power-Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V I
BATT ON Output Short Circuit Current 30 mA BATT ON = V

0.5 2.5 25 µA BATT ON = V

= 3.2 mA

SINK

= 2.4 V Sink Current

OUT

, VCC = 0 V, Source Current

OUT

RESET AND WATCHDOG TIMER

Low Line Threshold (LLIN) 1.25 1.3 1.35 V
Reset Timeout Delay 35 50 70 ms OSC SEL = HIGH
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period

70 100 140 ms Short Period

Watchdog Timeout Period, External Clock 4032 4063 4097 Cycles Long Period

960 1011 1025 Cycles Short Period

Minimum WDI Input Pulse Width 50 ns VIL = 0.8, VIH = 3.75 V, VCC = 5 V

100 ns VIL = 0.8, VIH = 3.5 V, VCC = 5 V

100 ns VIL = 0.8, VIH = 2.6 V, VCC = 3 V
RESET Output Voltage @ VCC = +1 V 4 20 mV I
RESET, RESET Output Voltage 0.1 0.4 V I

0.1 0.4 V I

3.5 V I

2.7 V I

LOW LINE, WDO Output Voltage 0.4 V I

3.5 V I

2.7 V I
Output Short Circuit Source Current 1 10 25 µAVCC = 5 V
WDI Input Threshold

1

= 10 µA, VCC = 1 V

SINK

= 400 µA, VCC = 2 V, V

SINK

= 3.2 mA, 3 V < VCC < 5.5 V

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1 µA, VCC = 3 V

SOURCE

= 3.2 mA,

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1 µA, VCC = 3 V

SOURCE

Logic Low 0.8 V
Logic High 3.5 V VCC = 5 V

1.2 V VCC = 3 V
WDI Input Current 1 10 µA WD1 = V

OUT

, (VCC)

–10 –1 µA WD1 = 0 V

POWER FAIL DETECTOR

PFI Input Threshold 1.2 1.3 1.4 V
PFI–LLIN Threshold Difference –50 ±15 +50 mV
PFI Input Current –25 ±0.01 +25 nA
LLIN Input Current –50 ±0.01 +50 nA
PFO Output Voltage 0.4 V I

3.5 V I

2.7 V I

= 3.2 mA

SINK

= 1 µA

SOURCE

= 1 µA, VCC = 3 V

SOURCE

PFO Short Circuit Source Current 1 10 25 µA PFI = Low, PFO = 0 V

CHIP ENABLE GATING (ADM8697)

CE

Threshold 0.8 V V

IN

3.0 V V

IL
IH

1.2 V VCC = 3 V

CE

Pull-Up Current 3 µA

IN

CE

Output Voltage 0.4 V I

OUT

VCC – 0.5 V I

= 3.2 mA

SINK
SOURCE

= 800 µA

CE Propagation Delay 2 7 ns VCC = 5.0 V

4nsV

= 3.0 V

CC

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 500 kHz OSC SEL = 0 V

OSC IN Frequency with Ext. Capacitor 4 kHz OSC SEL = 0 V, C

NOTE

1

WDI is a three-level input internally biased to 38% of VCC and has an input impedance of approximately 5 MΩ.

= 47 pF

OSC

Specifications subject to change without notice.

–2–

MIN

– 0.2 V

= 0 V

BATT

to T

MAX

REV. 0

ADM8696/ADM8697

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

BATT

OUT

+ 0.5 V

Input Current

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

BATT

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

JA

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.

Power Dissipation, RU-16 TSSOP . . . . . . . . . . . . . . .500 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 158°C/W

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM8696/ADM8697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

PIN CONFIGURATIONS

Package

Model Temperature Range Option*

1

V

ADM8696AN –40°C to +85°C N-16
ADM8696ARW –40°C to +85°C R-16
ADM8696ARU –40°C to +85°C RU-16

ADM8697AN –40°C to +85°C N-16
ADM8697ARW –40°C to +85°C R-16
ADM8697ARU –40°C to +85°C RU-16

*N = Plastic DIP; R = Small Outline (Wide Body); RU = Thin Shrink Small

Outline (TSSOP).

BATT

V

OUT

V

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

CC

2

3

ADM8696

4

(Not to Scale)

5
6

7

8

TOP VIEW

16

15
14

13

12

11

10

9

RESET

RESET

WDO
LL

IN

NC

WDI

PFO

PFI

REV. 0

–3–

TEST

V
LL

GND

LOW LINE

OSC IN

OSC SEL

NC

CC

IN

1

2

3

ADM8697

4

TOP VIEW

(Not to Scale)

5

6

7

8

16

RESET

15

RESET

14

WDO

13

CE

IN

12

CE

OUT

11

WDI

10

PFO

9

PFI

ADM8696/ADM8697

Pin No.

Mnemonic ADM8696 ADM8697 Function

PIN FUNCTION DESCRIPTION

V
V
V

CC
BATT
OUT

3 3 Power Supply Input +3 V to +5 V.
1 — Backup Battery Input.
2 — Output Voltage, VCC or V

the highest potential. When V
threshold, V
reset threshold, V
RAM. Connect V

is switched to V

CC

is switched to V

BATT

to VCC if V

OUT

is internally switched to V

BATT

is higher than V

CC

. When VCC is lower than V

OUT

OUT

OUT

and V

depending on which is at

OUT

and LLIN is higher than the reset

BATT

. V

can supply up to 100 mA to power CMOS

OUT

are not used.

BATT

and LLIN is below the

BATT

GND 4 5 0 V. Ground reference for all signals.
RESET 15 15 Logic Output. RESET goes low whenever LLIN falls below 1.3 V and remains low for 50 ms

after LL
abled but not serviced within its timeout period. The

goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is en-

IN

RESET pulse width can be adjusted as

shown in Table I.

WDI 11 11 Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer

than the watchdog timeout period,

RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.

PFI 9 9 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is

less than 1.3 V,

PFO goes low. Connect PFI to GND or V

OUT

when not used. See Figure 1.

PFO 10 10 Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI

is less than 1.3 V. The comparator is turned off and
V

.

BATT

CE

CE

IN
OUT

— 13 Logic Input. The input to the CE gating circuit. Connect to GND or V
— 12 Logic Output. CE

is above 1.3 V. If LLIN is below 1.3 V, CE

is a gated version of the CEIN signal. CE

OUT

OUT

BATT ON 5 — Logic Output. BATT ON goes high when V

It goes low when V

is internally switched to VCC. The output typically sinks 7 mA and

OUT

OUT

PFO goes low when VCC is below

OUT

tracks CEIN when LL

OUT

is forced high.

is internally switched to the V

if not used.

input.

BATT

IN

can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V

OUT

.

LOW LINE 6 6 Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as

LL

rises above 1.3 V.

IN

RESET 16 16 Logic Output. RESET is an active high output. It is the inverse of

RESET.

OSC SEL 8 8 Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal

oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pull-up. See
Table I and Figure 4.

OSC IN 7 7 Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock

to adjust both the reset delay and the watchdog timeout period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.

WDO 14 14 Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low

for longer than the watchdog timeout period.
WDI. If WDI is unconnected or at midsupply,
when

LOW LINE goes low.

WDO is set high by the next transition at

WDO remains high. WDO also goes high

NC 12 2 No Connect. It should be left open.
LL

IN

13 4 Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V

reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a
RESET/

RESET output. The comparator output also controls the battery switchover circuitry.

LOW LINE output signal. It also generates a

TEST — 1 This is a special test pin using during device manufacture. It should be connected to GND.

–4–

REV. 0