Supervisory Circuits with Watchdog and
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Manual Reset in 5-Lead SC70 and SOT-23
FEATURES
Precision 2.5 V to 5 V power supply monitor
7 reset threshold options: 2.19 V to 4.63 V
140 ms (minimum) reset timeout
Watchdog timer with 1.6 sec timeout (ADM823, ADM824)
Manual reset input (ADM823, ADM825)
Push-pull output stages
(ADM823)
RESET
, RESET (ADM824/ADM825)
RESET
Low power consumption: 5 μA
Guaranteed reset output valid to V
Power supply glitch immunity
Specified over automotive temperature range
5-lead SC70 and SOT-23 packages
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
= 1 V
CC
ADM823/ADM824/ADM825
FUNCTIONAL BLOCK DIAGRAM
ADM823
V
MR
CC
V
REF
DEBOUNCE
GND WDI
RESET
GENERATOR
WATCHDOG
DETECTOR
Figure 1.
V
CC
RESET
04534-001
GENERAL DESCRIPTION
The ADM823/ADM824/ADM825 are supervisory circuits that
monitor power supply voltage levels and code execution integrity
in microprocessor-based systems. In addition to providing
power-on reset signals, an on-chip watchdog timer can reset the
microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by an external pushbutton, through a manual reset input. The three parts feature
different combinations of watchdog input, manual reset input,
and output stage configuration, as shown in Tab le 1 .
Table 1. Selection Table
Part No. Watchdog Timer Manual Reset
ADM823 Yes Yes Push-Pull –
ADM824 Yes – Push-Pull Push-Pull
ADM825 – Yes Push-Pull Push-Pull
These parts are available in a choice of seven reset threshold
options ranging from 2.19 V to 4.63 V. The reset and watchdog
timeout periods are fixed at 140 ms (minimum) and 1.6 sec
(typical), respectively.
The ADM823/ADM824/ADM825 are available in 5-lead SC70
and SOT-23 packages and typically consume only 5 µA, making
them suitable for use in low power, portable applications.
Output Stage
RESET
RESET
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description ........................................................................... 9
REVISION HISTORY
5/08—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 4 ............................................................................ 6
Changes to Ordering Guide .......................................................... 11
2/07—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 11
10/04—Revision 0: Initial Version
Reset Output ..................................................................................9
Manual Reset Input .......................................................................9
Watchdog Input .............................................................................9
Applications Information .............................................................. 10
Watchdog Input Current ........................................................... 10
Negative-Going V
Ensuring Reset Valid to V
Watchdog Software Considerations ......................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Transients ................................................ 10
CC
= 0 V ........................................... 10
CC
Rev. B | Page 2 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
SPECIFICATIONS
VCC = 4.75 V to 5.5 V for ADM82xL, VCC = 4.5 V to 5.5 V for ADM82xM, VCC = 3.15 V to 3.6 V for ADM82xT, VCC = 3 V to 3.6 V
for ADM82xS, V
T
= T
MIN
to T
A
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range 1 5.5 V TA = 0°C to 70°C
1.2 V TA = T
Supply Current 10 24 μA
5 12 μA
RESET THRESHOLD VOLTAGE
ADM82xL
4.50 4.75 V TA = T
ADM82xM
4.25 4.50 V TA = T
ADM82xT
3.00 3.15 V TA = T
ADM82xS
2.85 3.00 V TA = T
ADM82xR
2.55 2.70 V TA = T
ADM82xZ (SC70 Only)
2.25 2.38 V TA = T
ADM82xY (SC70 Only)
2.13 2.25 V TA = T
RESET THRESHOLD TEMPERATURE COEFFICIENT 40 ppm/°C
RESET THRESHOLD HYSTERESIS 10 mV ADM82xL/M
5 mV ADM82xT/S/R/Z/Y
RESET TIMEOUT PERIOD 140 200 280 ms
VCC TO RESET DELAY 40 μs VTH − VCC = 100 mV
RESET/RESET
RESET Output Voltage
0.3 V
0.3 V
V
0.8 × VCC V
RESET Output Voltage (ADM824, ADM825) 0.4 V
0.3 V
0.8 × VCC V VCC ≥ 1.8 V, I
= 2.7 V to 3.6 V for ADM82xR, VCC = 2.38 V to 2.75 V for ADM82xZ, VCC = 2.25 V to 2.75 V for ADM82xY,
CC
, unless otherwise noted.
MAX
to T
MIN
MAX
WDI and MR
unconnected
ADM82xL/M
WDI and MR
unconnected
ADM82xT/S/R/Z/Y
4.56 4.63 4.70 V TA = 25°C
to T
MIN
4.31 4.38 4.45 V TA = 25°C
to T
MIN
3.04 3.08 3.11 V TA = 25°C
to T
MIN
2.89 2.93 2.96 V TA = 25°C
to T
MIN
2.59 2.63 2.66 V TA = 25°C
to T
MIN
2.28 2.32 2.35 V TA = 25°C
to T
MIN
2.16 2.19 2.22 V TA = 25°C
to T
MIN
MAX
MAX
MAX
MAX
MAX
MAX
MAX
0.4 V
VCC = VTH min, I
ADM82xL/M
= VTH min, I
V
CC
ADM82xT/S/R/Z/Y
= 0°C to 70°C, VCC = 1 V,
T
A
V
falling, I
− 1.5 V
CC
CC
= VTH max, I
V
CC
SINK
ADM82xL/M
= VTH max, I
V
CC
ADM82xT/S/R/Z/Y
= VTH max, I
V
CC
ADM82xL/M
= VTH max, I
V
CC
ADM82xT/S/R/Z/Y
SOURCE
= 3.2 mA,
SINK
= 1.2 mA,
SINK
= 50 μA
= 120 μA,
SOURCE
= 30 μA,
SOURCE
= 3.2 mA,
SINK
= 1.2 mA,
SINK
= 150 μA
Rev. B | Page 3 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
Parameter Min Typ Max Unit Test Conditions/Comments
WATCHDOG INPUT (ADM823, ADM824)
Watchdog Timeout Period 1.12 1.6 2.40 sec
WDI Pulse Width 50 ns VIL = 0.4 V, VIH = 0.8 × VCC
WDI Input Threshold, VIL 0.7 × VCC 0.3 × VCC V
WDI Input Current 120 160 μA V
MANUAL RESET INPUT (ADM823, ADM825)
MR Input Threshold
MR Input Pulse Width
MR Glitch Rejection
MR Pull-Up Resistance
MR to Reset Delay
= VCC, time average
WDI
−20 −15 μA V
0.7 × V
1 μs
100 ns
35 52 75 kΩ
500 ns
0.3 × VCC V
CC
= 0 V, time average
WDI
Rev. B | Page 4 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC −0.3 V to +6 V
Output Current (RESET, RESET)
All Other Pins −0.3 V to (VCC + 0.3 V)
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance
SC70 146°C/W
SOT-23 270°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
20 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RESET
GND
MR
1
ADM823
2
TOP VIEW
(Not to Scale)
3
5
V
CC
4
WDI
04534-002
RESET
GND
RESET
1
ADM824
2
TOP VIEW
(Not to Scale)
3
5
4
Figure 2. ADM823 Pin Configuration Figure 3. ADM824 Pin Configuration Figure 4. ADM825 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
RESET
Active Low, Push-Pull Reset Output. Asserted whenever VCC is below the reset threshold, VTH.
2 GND Ground.
3
(ADM823) Manual Reset Input. This is an active low input which, when forced low for at least 1 μs, generates
MR
a reset. It features a 52 kΩ internal pull-up.
RESET (ADM824/ADM825) Active High, Push-Pull Reset Output.
4 WDI (ADM823/ADM824)
Watchdog Input. Generates a reset if the voltage on the pin remains low or high for the duration
of the watchdog timeout. The timer is cleared if a logic transition occurs on this pin or if a reset is
generated.
(ADM825) Manual Reset Input. This is an active low input which, when forced low for at least 1 μs, generates
MR
a reset. It features a 52 kΩ internal pull-up.
5 VCC Power Supply Voltage Being Monitored.
V
WDI
1
CC
04534-003
RESET
GND
RESET
ADM825
2
TOP VIEW
(Not to Scale)
3
5
V
CC
4
MR
04534-004
Rev. B | Page 6 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
10.0
9.5
9.0
8.5
ADM823 L
8.0
7.5
7.0
(µA)
6.5
CC
I
6.0
ADM824Y
5.5
5.0
4.5
4.0
3.5
ADM825R
TEMPERATURE (°C)
120–40 –20 0 20 40 60 80 100
04534-005
100
90
80
70
60
50
40
TO RESET DELAY (µs)
30
CC
V
20
10
0
TEMPERATURE (°C)
120–40 40200–20 60 80 100
04534-008
Figure 8. Reset Comparator Propagation Delay vs. Temperature (V
80
75
70
65
60
55
50
45
40
(µA)
35
CC
I
30
25
20
15
10
5
0
VCC (V)
5.502.01.51.00.5 2.5 3.0 3.5 4.0 4.5 5.0
04534-006
340
320
300
280
260
240
220
200
180
160
140
MANUAL RESET TO RES ET DELAY (ns)
120
100
TEMPERATURE (°C)
Falling) Figure 5. Supply Current vs. Temperature
CC
120–40 40200–20 60 80 100
04534-009
Figure 6. Supply Current vs. Supply Voltage Figure 9. Manual Reset to Reset Propagation Delay vs. Temperature
(ADM823/ADM825)
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
NORMALIZE D RESET THRESHOLD (V)
0.96
0.95
TEMPERATURE (° C)
120–40 40200–20 60 80 100
04534-007
250
240
230
220
210
200
190
RESET TIMEOUT PERIOD (ms)
180
170
TEMPERATURE ( °C)
120–40 40200–20 60 80 100
04534-010
Figure 10. Reset Timeout Period vs. Temperature Figure 7. Normalized Reset Threshold vs. Temperature
Rev. B | Page 7 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
WATCHDOG TIMEOUT PERIOD (s)
0.2
0
TEMPERATURE (° C)
Figure 11. Watchdog Timeout Period vs. Temperature
(ADM823/ADM824)
160
140
120
100
TRANSIENT DURAT ION (µs)
CC
MAXIMUM V
VTH = 4.63V
80
60
40
20
VTH = 2.93V
0
RESET OCCURS ABOV E GRAPH
OVERDRIVE VO D (mV)
120–40 –20 0 20 40 60 80 100
04534-011
100010 100
04534-012
190
180
170
160
150
140
130
120
MR MINIMUM PULSE WIDTH (ns)
110
100
TEMPERATURE (°C)
100–50 0 50
Figure 13. Manual Reset Minimum Pulse Width vs. Temperature
(ADM823/ADM825)
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
MINIMUM PULSE WIDTH (ns)
2.2
2.0
NEGATIVE PULSE
POSITIVE PULSE
TEMPERATURE (°C)
04534-013
160–40 10 11060
04534-014
Figure 12. Maximum V
Transient Duration vs. Reset Threshold Overdrive
CC
Figure 14. Watchdog Input Minimum Pulse Width vs. Temperature
(ADM823/ADM824)
Rev. B | Page 8 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
CIRCUIT DESCRIPTION
The ADM823/ADM824/ADM825 provide microprocessor
supply voltage supervision by controlling the reset input of the
microprocessor. Code execution errors are avoided during
power-up, power-down, and brownout conditions by asserting a
reset signal when the supply voltage is below a preset threshold.
Errors are also avoided by allowing supply voltage stabilization
with a fixed timeout reset pulse after the supply voltage rises
above the threshold. In addition, problems with microprocessor
code execution can be monitored and corrected with a watchdog
timer (ADM823/ADM824). By including watchdog strobe
instructions in microprocessor code, a watchdog timer can
detect whether the microprocessor code breaks down or becomes
stuck in an infinite loop. If this happens, the watchdog timer
asserts a reset pulse that restarts the microprocessor in a known
state. If the user detects a problem with the system’s operation, a
manual reset input is available (ADM823/ADM825) to reset the
microprocessor with an external push-button, for example.
RESET OUTPUT
The ADM823 features an active low, push-pull reset output, and
the ADM824/ADM825 feature dual active low and active high
push-pull reset outputs. For active low and active high outputs,
the reset signal is guaranteed to be logic low and logic high,
respectively, for V
The reset output is asserted when V
threshold (V
serviced within the watchdog timeout period (t
remains asserted for the duration of the reset active timeout
period (t
) after VCC rises above the reset threshold, after MR
RP
transitions from low to high, or after the watchdog timer times
out. illustrates the behavior of the reset outputs. Figure 15
V
CC
V
CC
1V
0V
V
RESET
RESET
CC
0V
V
CC
1V
0V
≥ 1 V.
CC
is below the reset
CC
), when MR is driven low, or when WDI is not
TH
). Reset
WD
V
TH
t
RP
t
RP
Figure 15. Reset Timing Diagram
V
TH
t
RD
t
RD
04534-018
MANUAL RESET INPUT
The ADM823/ADM825 feature a manual reset input (MR)
which, when driven low, asserts the reset output. When
MR
transitions from low to high, reset remains asserted for the
duration of the reset active timeout period before deasserting.
MR
The
input has a 52 k internal pull-up so that the input is
always high when unconnected. An external push-button
switch can be connected between
MR
and ground so that the
user can generate a reset. Debounce circuitry for this purpose is
integrated on chip. Noise immunity is provided on the
MR
input and fast, negative-going transients of up to 100 ns (typical)
are ignored. A 0.1 µF capacitor between
MR
and ground
provides additional noise immunity.
WATCHDOG INPUT
The ADM823/ADM824 feature a watchdog timer that monitors
microprocessor activity. A timer circuit is cleared with every
low-to-high or high-to-low logic transition on the watchdog
input pin (WDI), which detects pulses as short as 50 ns. If the
timer counts through the preset watchdog timeout period (t
reset is asserted. The microprocessor is required to toggle the
WDI pin to avoid being reset. Failure of the microprocessor to
toggle WDI within the timeout period, therefore, indicates a
code execution error, and the reset pulse generated restarts the
microprocessor in a known state.
In addition to logic transitions on WDI, the watchdog timer is
also cleared by a reset assertion due to an undervoltage condition on V
or by MR being pulled low. When reset is asserted,
CC
the watchdog timer is cleared and does not begin counting again
until reset is deasserted. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
V
RESET
WDI
V
CC
CC
1V
0V
V
CC
0V
V
CC
0V
V
TH
t
RP
Figure 16. Watchdog Timing Diagram
t
WD
t
RD
WD
04534-021
),
Rev. B | Page 9 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
APPLICATIONS INFORMATION
WATCHDOG INPUT CURRENT
To minimize the watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw as
much as 160 µA. Pulsing WDI low-high-low at a low duty cycle
reduces the effect of the large input current. When WDI is
unconnected, a window comparator disconnects the watchdog
timer from the reset output circuitry so that reset is not asserted
when the watchdog timer times out.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM823/ADM824/ADM825 are equipped with
glitch rejection circuitry. The typical performance characteristic
in Figure 12 plots V
transient duration vs. the transient mag-
CC
nitude. The curves show combinations of transient magnitude
and duration for which a reset is not generated for 4.63 V and
2.93 V reset threshold parts. For example, with the 2.93 V
threshold, a transient that goes 100 mV below the threshold and
lasts 8 µs typically does not cause a reset, but if the transient is
any larger in magnitude or duration, a reset is generated. An
optional 0.1 µF bypass capacitor mounted close to V
provides
CC
additional glitch rejection.
ENSURING RESET VALID TO VCC = 0 V
Both active low and active high reset outputs are guaranteed to
be valid for V
resistor with push-pull configured reset outputs, valid outputs
for V
as low as 0 V are possible. For an active low reset output,
CC
a resistor connected between
low when it is unable to sink current. For an active high reset
output, a resistor connected between RESET and V
output high when it is unable to source current. A large resistance such as 100 kΩ should be used so that the reset output is
not overloaded when V
V
as low as 1 V. However, by using an external
CC
and ground pulls the output
RESET
is above 1 V.
CC
V
CC
CC
pulls the
CC
WATCHDOG SOFTWARE CONSIDERATIONS
In implementing the microprocessor watchdog strobe code,
quickly switching WDI low-to-high and then high-to-low
(minimizing WDI high time) is desirable for current consumption
reasons. However, a more effective way of using the watchdog
function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
the watchdog timing out. However, if the subroutine becomes
stuck in an infinite loop, the watchdog cannot detect this condition because the subroutine continues to toggle WDI. A more
effective coding scheme for detecting this error involves using a
slightly longer watchdog timeout. In the program that calls the
subroutine, WDI is set high (see Figure 18). The subroutine sets
WDI low when it is called. If the program executes without error,
WDI is toggled high and low with every loop of the program.
If the subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE
SET WDI
LOW
RETURN
Figure 18. Watchdog Flow Diagram
V
CC
RESET
INFINITE LOOP:
WATCHDOG
TIMES OUT
04534-020
100kΩ
ADM823/
ADM824/
ADM825
RESET
100kΩ
Figure 17. Ensuring Reset Valid to V
ADM824/
ADM825
= 0 V
CC
RESET
04534-017
Rev. B | Page 10 of 12
RESET RESET
ADM823
WDI I/OMR
Figure 19. Typical Application Circuit
MICROPROCESSOR
04534-019
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
2.20
2.00
1.80
1.35
1.25
1.15
1.00
0.90
0.70
0
.
1
0
M
123
PIN 1
X
A
0.10 COPLANARITY
0.30
0.15
COMPLIANT TO JEDEC STANDARDS MO-203-AA
Figure 20. 5-Lead Thin Shrink Small Outline Transistor Package [SC70]
Dimensions shown in millimeters
2.90 BSC
45
0.65 BSC
2.40
2.10
1.80
1.10
0.80
SEATING
PLANE
(KS-5)
0.40
0.10
0.22
0.08
0.46
0.36
0.26
1.60 BSC
1.30
1.15
0.90
0.15 MAX
5
123
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-178-A A
1.90
BSC
0.50
0.30
4
2.80 BSC
0.95 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
10°
5°
0°
0.60
0.45
0.30
Figure 21. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model Reset Threshold (V) Temperature Range Quantity Package Description Package Option Branding
ADM823LYKS-R7 4.63 −40°C to +125°C 3k 5-Lead SC70 KS-5 N07
ADM823LYKSZ-R7
ADM823LYRJ-R7 4.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM823LYRJZ-R7
ADM823MYKSZ-R7
ADM823MYRJZ-R7
ADM823TYKS-R7 3.08 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM823TYKSZ-R7
ADM823TYRJ-R7 3.08 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM823TYRJZ-R7
ADM823SYKS-R7 2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM823SYKSZ-R7
ADM823SYRJ-R7 2.93 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM823SYRJZ-R7
1
4.63 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
N07
1
4.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M4L
1
4.38 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
1
4.38 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M4L
N07
1
3.08 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
N07
1
3.08 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M4L
N07
1
2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
N07
1
2.93 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M4L
Rev. B | Page 11 of 12
ADM823/ADM824/ADM825
www.BDTIC.com/ADI
Model Reset Threshold (V) Temperature Range Quantity Package Description Package Option Branding
ADM823RYKS-R7 2.63 −40°C to +125°C 3k 5-Lead SC70 KS-5 N07
ADM823RYRJZ-R7
ADM823ZYKS-R7 2.32 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM823ZYKSZ-R7
ADM823YYKS-R7 2.19 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM823YYKSZ-R7
ADM824LYKS-REEL7 4.63 −40°C to +125°C 3k 5-Lead SC70 KS-5 N08
ADM824SYKS-REEL 2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5 N08
ADM824SYKSZ-REEL7
ADM824SYRJ-REEL7 2.93 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM825LYKS-R7 4.63 −40°C to +125°C 3k 5-Lead SC70 KS-5 N09
ADM825LYRJ-R7 4.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 N09
ADM825LYRJZ-R7
ADM825MYKS-R7 4.38 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM825MYRJ-R7 4.38 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM825TYKS-R7 3.08 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM825TYKSZ-R7
ADM825TYRJ-R7 3.08 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM825TYRJZ-R7
ADM825SYKS-R7 2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM825SYKSZ-R7
ADM825SYRJ-R7 2.93 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM825SYRJZ-R7
ADM825RYKS-R7 2.63 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM825RYRJ-R7 2.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5
ADM825ZYKS-R7 2.32 −40°C to +125°C 3k 5-Lead SC70 KS-5
ADM825ZYKSZ-R7
ADM825YYKS-R7 2.19 −40°C to +125°C 3k 5-Lead SC70 KS-5 N09
1
Z = RoHS Compliant Part.
1
2.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M4L
N07
1
2.32 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
N07
1
2.19 −40°C to +125°C 3k 5-Lead SC70 KS-5 M4L
1
2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5 M8G
N08
1
4.63 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M8H
N09
N09
N09
1
3.08 −40°C to +125°C 3k 5-Lead SC70 KS-5 M8H
N09
1
3.08 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M8H
N09
1
2.93 −40°C to +125°C 3k 5-Lead SC70 KS-5 M8H
N09
1
2.93 −40°C to +125°C 3k 5-Lead SOT-23 RJ-5 M8H
N09
N09
N09
1
2.32 −40°C to +125°C 3k 5-Lead SC70 KS-5 M8H
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D04534-0-5/08(B)
Rev. B | Page 12 of 12
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