FEATURES
Superior Upgrade for MAX811/MAX812
Specified over Temperature
Low Power Consumption (5 A Typ)
Precision Voltage Monitor: 2.5 V, 3 V, 3.3 V, 5 V Options
Reset Assertion Down to 1 V V
CC
140 ms Min Power-On Reset
Logic Low RESET Output (ADM811)
Logic High RESET Output (ADM812)
Built-In Manual Reset
APPLICATIONS
Microprocessor Systems
Controllers
Intelligent Instruments
Automotive Systems
Safety Systems
Portable Instruments
GENERAL DESCRIPTION
The ADM811/ADM812 is a reliable voltage monitoring device
suitable for use in most voltage monitoring applications. The
ADM811/ADM812 is designed to monitor six different voltages,
each allowing for a 5% or 10% degradation of standard PSU
voltages before a reset occurs. These voltages have been selected
for the effective monitoring of 2.5 V, 3 V, 3.3 V, and 5 V supply
voltage levels.
Included in this circuit is a debounced manual reset input.
Reset can be activated using an electrical switch (or an input
from another digital device) or by a degradation of the supply
voltage. The manual reset function is very useful, especially if
the circuit in which the ADM811/ADM812 is operating enters
into a state that can only be detected by the user. Allowing the
user to reset a system manually can reduce the damage or
danger that could otherwise be caused by an out-of-control or
locked system.
FUNCTIONAL BLOCK DIAGRAM
MR
V
CC
ADM811
GND
MICROPROCESSOR
RESET
100k⍀
RESET
V
SYSTEM
GND
CC
Figure 1. Typical ADM811 Operating Circuit
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
ADM811LART-REEL4.63–40°C to +85°CMBV10
ADM811LART-REEL-74.63–40°C to +85°CMBV3
ADM811MART-REEL4.38–40°C to +85°CMBT10
ADM811MART-REEL-74.38–40°C to +85°CMBT3
ADM811TART-REEL3.08–40°C to +85°CMBG10
ADM811TART-REEL-73.08–40°C to +85°CMBG3
ADM811-3TART-REEL3.08–40°C to +85°CMB310
ADM811-3TART-REEL-73.08–40°C to +85°CMB33
ADM811SART-REEL2.93–40°C to +85°CMBE10
ADM811SART-REEL-72.93–40°C to +85°CMBE3
ADM811RART-REEL2.63–40°C to +85°CMBB10
ADM811RART-REEL-72.63–40°C to +85°CMBB3
ADM811ZART-REEL2.32–40°C to +85°CMBZ10
ADM811ZART-REEL-72.32–40°C to +85°CMBZ3
ADM812LART-REEL4.63–40°C to +85°CMCV10
ADM812LART-REEL-74.63–40°C to +85°CMCV3
ADM812MART-REEL4.38–40°C to +85°CMCT10
ADM812MART-REEL-74.38–40°C to +85°CMCT3
ADM812TART-REEL3.08–40°C to +85°CMCG10
ADM812TART-REEL-73.08–40°C to +85°CMCG3
ADM812SART-REEL2.93–40°C to +85°CMCE10
ADM812SART-REEL-72.93–40°C to +85°CMCE3
ADM812RART-REEL2.63–40°C to +85°CMCB10
ADM812RART-REEL-72.63–40°C to +85°CMCB3
ADM812ZART-REEL2.32–40°C to +85°CMCZ10
ADM812ZART-REEL-72.32–40°C to +85°CMCZ3
*Only available in reels.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM811/ADM812 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
ADM811/ADM812
PIN CONFIGURATION
GND
RESET/RESET
1
ADM811/
ADM812
TOP VIEW
2
(Not to Scale)
4
V
CC
3
MR
PIN FUNCTION DESCRIPTIONS
Pin MnemonicFunction
1GND0 V. Ground reference for all signals.
2RESET (ADM811) Active Low Logic Output. RESET remains low while V
RESET then remains low for at least 140 ms (at least 300 ms for the ADM811-3T) after V
is below the reset threshold or when MR is low;
CC
rises above
CC
the reset threshold.
RESET (ADM812) Active High Logic Output. RESET remains high while V
RESET then remains high for 240 ms (typical) after V
is below the reset threshold or when MR is low;
CC
rises above the reset threshold.
CC
3MRManual Reset. This active low debounced input will ignore input pulses of 100 ns or less (typical) and is
guaranteed to accept input pulses of greater than 10 µs. Leave floating when not used.
4V
CC
2.5 V, 3 V, 3.3 V, or 5 V Monitored Supply Voltage.
–4–
REV. C
Typical Performance Characteristics—ADM811/ADM812
900
POWER-DOWN RESET DELAY – s
800
700
600
500
400
300
200
100
0
VOD = 20mV
VOD = 200mV
VOD = 125mV
TEMPERATURE – ⴗC
–40 –2002030507085100 120
12
10
8
6
– A
DD
I
4
2
0
–40
–2002030507085100 120
IDD @ VCC = 5.5V
IDD @ VCC = 3V
IDD @ VCC = 1V
TEMPERATURE – ⴗC
TPC 1. Supply Current vs. Temperature (ADM81_R/S/T/Z)
1000
900
800
700
600
500
400
300
200
POWER-DOWN RESET DELAY – s
100
VOD = 200mV
0
–40 –2002030507085100 120
TPC 2. Power-Down
VOD = 20mV
VOD = 125mV
RESET
TEMPERATURE – ⴗC
Delay vs. Temperature
(ADM81_R/S/T/Z)
10
9
8
7
6
5
– A
DD
I
4
3
2
1
0
–40 –2002030507085100 120
IDD @ VCC = 5.5V
IDD @ VCC = 3V
IDD @ VCC = 1V
TEMPERATURE – ⴗC
TPC 4. Supply Current vs. Temperature (ADM81_L/M)
TPC 5. Power-Down
RESET
Delay vs. Temperature
(ADM81_L/M)
289
284
279
274
269
264
259
REV. C
254
POWER-UP RESET TIMEOUT – ms
249
244
–40 –2002030507085100 120
TPC 3. Power-Up Reset Timeout vs. Temperature
ADM81_L/M
ADM81_R/S/T/Z
TEMPERATURE – ⴗC
–5–
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
NORMALIZED RESET THRESHOLD
0.996
0.995
–40 –2002030507085100 120
TEMPERATURE – ⴗC
TPC 6. Reset Threshold Deviation vs. Temperature
ADM811/ADM812
RESET
ADM811
GND
V
CC
V
CC
CIRCUIT INFORMATION
Reset Thresholds
A reset output is provided to the microprocessor whenever the
input is below the reset threshold. The actual reset thresh-
V
CC
old is dependent on whether an L, M, T, S, R, or Z suffix is
used. Refer to Table I.
On power-up and after VCC rises above the reset threshold, an
internal timer holds the reset output active for 240 ms (typical).
This is intended as a power-on reset signal for the processor. It
allows time for both the power supply and the microprocessor to
stabilize after power-up. If a power supply brownout or interruption occurs, the reset output is similarly activated and remains
active for 240 ms (typical) after the supply recovers. This allows
time for the power supply and microprocessor to stabilize.
The ADM811 provides an active low reset output (RESET)
while the ADM812 provides an active high output (RESET).
During power-down of the ADM811, the RESET output remains
valid (low) with V
as low as 1 V. This ensures that the micro-
CC
processor is held in a stable shutdown condition as the supply
falls and also ensures that no spurious activity can occur via
the microprocessor as it powers up.
Glitch Immunity
The ADM811/ADM812 contains internal filtering circuitry
providing glitch immunity from fast transient glitches on the
power supply line.
V
V
RESET
CC
V
REF
t
= RESET TIME = 240ms TYPICAL
1
V
= RESET VOLTAGE THRESHOLD
REF
Figure 2. Power Fail
V
REF
t
1
V
REF
t
1
RESET
Timing
REF
INTERFACING TO OTHER DEVICES
Output
The ADM811/ADM812 is designed to integrate with as many
devices as possible. One feature of the ADM811/ADM812 is
the reset output, which is directly proportional to V
guaranteed only while V
is greater than 1 V). This enables the
CC
(this is
CC
part to be used with both 3 V and 5 V, or any nominal voltage
within the minimum and maximum specifications for V
CC
.
BENEFITS OF A VERY ACCURATE RESET THRESHOLD
Because the ADM811/ADM812 can operate effectively even when
there are large degradations of the supply voltages, the possibility
of a malfunction during a power failure is greatly reduced. Another
advantage of the ADM811/ADM812 is its very accurate internal
voltage reference circuit. Combined, these benefits produce an
exceptionally reliable microprocessor supervisory circuit.
Figure 3. Ensuring a Valid
Down to V
= 0 V
CC
RESET
Output
MANUAL RESET
The ADM811/ADM812 is equipped with a manual reset input.
This input is designed to operate in a noisy environment where
unwanted glitches could be induced. These glitches could be
produced by the bouncing action of a switch contact, or where a
manual reset switch may be located some distance away from
the circuit (the cabling of which may pick-up noise).
The manual reset input is guaranteed to ignore logically valid
inputs that are faster than 100 ns and to accept inputs longer in
duration than 10 µs.
ENSURING A VALID RESET OUTPUT DOWN TO V
When VCC falls below 0.8 V, the ADM811/ADM812’s RESET
no longer sinks current. Therefore, a high impedance CMOS
logic input connected to RESET may drift to undetermined
logic levels. To eliminate this problem, a 100 kΩ resistor should
be connected from RESET to ground.