Analog Devices ADM811 2 c Datasheet

Microprocessor Supervisory
DEBOUNCE
RESET/RESET
GND
V
CC
V
REF
ADM811/ADM812
RESET
GENERATOR
MR
Circuit in 4-Lead SOT-143
FEATURES Superior Upgrade for MAX811/MAX812 Specified over Temperature Low Power Consumption (5 A Typ) Precision Voltage Monitor: 2.5 V, 3 V, 3.3 V, 5 V Options Reset Assertion Down to 1 V V
CC
140 ms Min Power-On Reset
Logic Low RESET Output (ADM811) Logic High RESET Output (ADM812)
Built-In Manual Reset
APPLICATIONS Microprocessor Systems Controllers Intelligent Instruments Automotive Systems Safety Systems Portable Instruments

GENERAL DESCRIPTION

The ADM811/ADM812 is a reliable voltage monitoring device suitable for use in most voltage monitoring applications. The ADM811/ADM812 is designed to monitor six different voltages, each allowing for a 5% or 10% degradation of standard PSU voltages before a reset occurs. These voltages have been selected for the effective monitoring of 2.5 V, 3 V, 3.3 V, and 5 V supply voltage levels.
Included in this circuit is a debounced manual reset input. Reset can be activated using an electrical switch (or an input from another digital device) or by a degradation of the supply voltage. The manual reset function is very useful, especially if the circuit in which the ADM811/ADM812 is operating enters into a state that can only be detected by the user. Allowing the user to reset a system manually can reduce the damage or danger that could otherwise be caused by an out-of-control or locked system.

FUNCTIONAL BLOCK DIAGRAM

MR
V
CC
ADM811
GND
MICROPROCESSOR
RESET
100k
RESET
V
SYSTEM
GND
CC
Figure 1. Typical ADM811 Operating Circuit
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADM811/ADM812–SPECIFICATIONS
(VCC = Full Operating Range; TA = T
3.3 V for T/S, 3 V for R, 2.5 V for Z Models; unless otherwise noted.)
MIN
to T
; VCC typ = 5 V for L/M,
MAX
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
Voltage 1.0 5.5 V T
1.2 V T
Current 8 15 µAV
510 µAV
= 0°C to 70°C
A
= –40°C to +85°C
A
< 5.5 V, ADM81_L/M, I
CC
< 3.6 V, ADM81_R/S/T/Z, I
CC
OUT
RESET VOLTAGE THRESHOLD
ADM81_L 4.54 4.63 4.72 V T ADM81_L 4.50 4.75 V T ADM81_M 4.30 4.38 4.46 V T ADM81_M 4.25 4.50 V T ADM81_T 3.03 3.08 3.14 V T ADM81_T 3.00 3.15 V T ADM81_S 2.88 2.93 2.98 V T ADM81_S 2.85 3.00 V T ADM81_R 2.58 2.63 2.68 V T ADM81_R 2.55 2.70 V T ADM81_Z 2.28 2.32 2.35 V T
= 25°C
A
= –40°C to +85°C
A
= 25°C
A
= –40°C to +85°C
A
= 25°C
A
= –40°C to +85°C
A
= 25°C
A
= –40°C to +85°C
A
= 25°C
A
= –40°C to +85°C
A
= 25°C
A
ADM81_Z 2.25 2.38 V TA = –40°C to +85°C
RESET THRESHOLD
TEMPERATURE COEFFICIENT 30 ppm/°C
TO RESET/RESET DELAY 40 µsV
V
CC
20 µsV
RESET ACTIVE TIMEOUT PERIOD 140 560 ms V
= 125 mV, ADM81_L/M
OD
= 125 mV, ADM81_R/S/T/Z
OD
= V
CC
TH(MAX)
300 700 ms (ADM811-3T Only)
MANUAL RESET
Minimum Pulsewidth 10 µs Glitch Immunity 100 ns RESET/RESET Propagation Delay 0.5 µs Pull-Up Resistance 10 20 30 k The Manual Reset Circuit Will Act On:
An Input Rising Above 2.3 V V An Input Falling Below 0.8 V V An Input Rising Above 0.7 ⫻ V
CC
VV
An Input Falling Below 0.25 ⫻ VCCVV
CC
CC
CC
CC
> V > V > V > V
TH(MAX),
TH(MAX),
TH(MAX),
TH(MAX),
ADM81_L/M ADM81_L/M ADM81_R/S/T/Z ADM81_R/S/T/Z
RESET/RESET Output Voltage
Low (ADM812R/S/T/Z) 0.3 V V Low (ADM812L/M) 0.4 V V High (ADM812R/S/T/Z/L/M) 0.8 ⫻ V
CC
V 1.8 V < VCC < V Low (ADM811R/S/T/Z) 0.3 V V Low (ADM811L/M) 0.4 V V Low (ADM811R/S/T/Z/L/M) 0.3 V V High (ADM811R/S/T/Z) 0.8 ⫻ V High (ADM811L/M) V
Specifications subject to change without notice.
CC
– 1.5 V VCC > V
CC
VV
= V
CC
= V
CC
= V
CC
= V
CC
> 1.0 V, I
CC
> V
CC
TH(MAX)
TH(MAX)
TH(MIN)
TH(MIN)
TH(MAX)
TH(MAX)
, I , I
TH(MIN)
, I
SINK
, I
SINK
SINK
, I , I
= 1.2 mA
SINK
= 3.2 mA
SINK
, I = 1.2 mA = 3.2 mA
= 50 µA
SOURCE
SOURCE
SOURCE
= 500 µA = 800 µA
= 0 mA
= 0 mA
OUT
= 150 µA
REV. C–2–
ADM811/ADM812

ABSOLUTE MAXIMUM RATINGS*

(Typical values are at TA = 25°C, unless otherwise noted.)
Terminal Voltage (With Respect to Ground)
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
CC
All Other Inputs . . . . . . . . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
Input Current
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
CC
MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output Current
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Power Dissipation (T
= 70°C)
A
Operating Temperature Range . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +160°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability.
RT-4, (SOT-143) . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mW
Derate by 4 mW/°C above 70°C
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 330°C/W
θ
JA

ORDERING GUIDE

Reset Temperature Branding
Model* Threshold (V) Range Information Quantity (K)
ADM811LART-REEL 4.63 –40°C to +85°C MBV 10 ADM811LART-REEL-7 4.63 –40°C to +85°C MBV 3 ADM811MART-REEL 4.38 –40°C to +85°C MBT 10 ADM811MART-REEL-7 4.38 –40°C to +85°C MBT 3 ADM811TART-REEL 3.08 –40°C to +85°C MBG 10 ADM811TART-REEL-7 3.08 –40°C to +85°C MBG 3 ADM811-3TART-REEL 3.08 –40°C to +85°CMB3 10 ADM811-3TART-REEL-7 3.08 –40°C to +85°CMB3 3 ADM811SART-REEL 2.93 –40°C to +85°C MBE 10 ADM811SART-REEL-7 2.93 –40°C to +85°C MBE 3 ADM811RART-REEL 2.63 –40°C to +85°CMBB 10 ADM811RART-REEL-7 2.63 –40°C to +85°CMBB 3 ADM811ZART-REEL 2.32 –40°C to +85°C MBZ 10 ADM811ZART-REEL-7 2.32 –40°C to +85°C MBZ 3 ADM812LART-REEL 4.63 –40°C to +85°C MCV 10 ADM812LART-REEL-7 4.63 –40°C to +85°C MCV 3 ADM812MART-REEL 4.38 –40°C to +85°C MCT 10 ADM812MART-REEL-7 4.38 –40°C to +85°C MCT 3 ADM812TART-REEL 3.08 –40°C to +85°C MCG 10 ADM812TART-REEL-7 3.08 –40°C to +85°C MCG 3 ADM812SART-REEL 2.93 –40°C to +85°C MCE 10 ADM812SART-REEL-7 2.93 –40°C to +85°C MCE 3 ADM812RART-REEL 2.63 –40°C to +85°CMCB 10 ADM812RART-REEL-7 2.63 –40°C to +85°CMCB 3 ADM812ZART-REEL 2.32 –40°C to +85°C MCZ 10 ADM812ZART-REEL-7 2.32 –40°C to +85°C MCZ 3
*Only available in reels.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM811/ADM812 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
ADM811/ADM812

PIN CONFIGURATION

GND
RESET/RESET
1
ADM811/
ADM812
TOP VIEW
2
(Not to Scale)
4
V
CC
3
MR

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function
1GND 0 V. Ground reference for all signals. 2 RESET (ADM811) Active Low Logic Output. RESET remains low while V
RESET then remains low for at least 140 ms (at least 300 ms for the ADM811-3T) after V
is below the reset threshold or when MR is low;
CC
rises above
CC
the reset threshold.
RESET (ADM812) Active High Logic Output. RESET remains high while V
RESET then remains high for 240 ms (typical) after V
is below the reset threshold or when MR is low;
CC
rises above the reset threshold.
CC
3 MR Manual Reset. This active low debounced input will ignore input pulses of 100 ns or less (typical) and is
guaranteed to accept input pulses of greater than 10 µs. Leave floating when not used.
4V
CC
2.5 V, 3 V, 3.3 V, or 5 V Monitored Supply Voltage.
–4–
REV. C
Typical Performance Characteristics—ADM811/ADM812
900
POWER-DOWN RESET DELAY – ␮s
800
700
600
500
400
300
200
100
0
VOD = 20mV
VOD = 200mV
VOD = 125mV
TEMPERATURE – ⴗC
–40 –20 0 20 30 50 70 85 100 120
12
10
8
6
␮A
DD
I
4
2
0
–40
–20 0 20 30 50 70 85 100 120
IDD @ VCC = 5.5V
IDD @ VCC = 3V
IDD @ VCC = 1V
TEMPERATURE – ⴗC
TPC 1. Supply Current vs. Temperature (ADM81_R/S/T/Z)
1000
900
800
700
600
500
400
300
200
POWER-DOWN RESET DELAY – ␮s
100
VOD = 200mV
0
–40 –20 0 20 30 50 70 85 100 120
TPC 2. Power-Down
VOD = 20mV
VOD = 125mV
RESET
TEMPERATURE – ⴗC
Delay vs. Temperature
(ADM81_R/S/T/Z)
10
9
8
7
6
5
␮A
DD
I
4
3
2
1
0
–40 –20 0 20 30 50 70 85 100 120
IDD @ VCC = 5.5V
IDD @ VCC = 3V
IDD @ VCC = 1V
TEMPERATURE – ⴗC
TPC 4. Supply Current vs. Temperature (ADM81_L/M)
TPC 5. Power-Down
RESET
Delay vs. Temperature
(ADM81_L/M)
289
284
279
274
269
264
259
REV. C
254
POWER-UP RESET TIMEOUT – ms
249
244
–40 –20 0 20 30 50 70 85 100 120
TPC 3. Power-Up Reset Timeout vs. Temperature
ADM81_L/M
ADM81_R/S/T/Z
TEMPERATURE – ⴗC
–5–
1.007
1.006
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
NORMALIZED RESET THRESHOLD
0.996
0.995 –40 –20 0 20 30 50 70 85 100 120
TEMPERATURE – ⴗC
TPC 6. Reset Threshold Deviation vs. Temperature
ADM811/ADM812
RESET
ADM811
GND
V
CC
V
CC
CIRCUIT INFORMATION Reset Thresholds
A reset output is provided to the microprocessor whenever the
input is below the reset threshold. The actual reset thresh-
V
CC
old is dependent on whether an L, M, T, S, R, or Z suffix is used. Refer to Table I.
Table I. Reset Threshold Options
Reset
Model Threshold (V)
ADM811LART 4.63 ADM811MART 4.38 ADM811TART 3.08 ADM811-3TART 3.08 ADM811SART 2.93 ADM811RART 2.63 ADM811ZART 2.32 ADM812LART 4.63 ADM812MART 4.38 ADM812TART 3.08 ADM812SART 2.93 ADM812RART 2.63 ADM812ZART 2.32

RESET OUTPUT

On power-up and after VCC rises above the reset threshold, an internal timer holds the reset output active for 240 ms (typical). This is intended as a power-on reset signal for the processor. It allows time for both the power supply and the microprocessor to stabilize after power-up. If a power supply brownout or inter­ruption occurs, the reset output is similarly activated and remains active for 240 ms (typical) after the supply recovers. This allows time for the power supply and microprocessor to stabilize.
The ADM811 provides an active low reset output (RESET) while the ADM812 provides an active high output (RESET).
During power-down of the ADM811, the RESET output remains valid (low) with V
as low as 1 V. This ensures that the micro-
CC
processor is held in a stable shutdown condition as the supply falls and also ensures that no spurious activity can occur via the microprocessor as it powers up.

Glitch Immunity

The ADM811/ADM812 contains internal filtering circuitry providing glitch immunity from fast transient glitches on the power supply line.
V
V
RESET
CC
V
REF
t
= RESET TIME = 240ms TYPICAL
1
V
= RESET VOLTAGE THRESHOLD
REF
Figure 2. Power Fail
V
REF
t
1
V
REF
t
1
RESET
Timing
REF
INTERFACING TO OTHER DEVICES Output
The ADM811/ADM812 is designed to integrate with as many devices as possible. One feature of the ADM811/ADM812 is the reset output, which is directly proportional to V guaranteed only while V
is greater than 1 V). This enables the
CC
(this is
CC
part to be used with both 3 V and 5 V, or any nominal voltage within the minimum and maximum specifications for V
CC
.

BENEFITS OF A VERY ACCURATE RESET THRESHOLD

Because the ADM811/ADM812 can operate effectively even when there are large degradations of the supply voltages, the possibility of a malfunction during a power failure is greatly reduced. Another advantage of the ADM811/ADM812 is its very accurate internal voltage reference circuit. Combined, these benefits produce an exceptionally reliable microprocessor supervisory circuit.
Figure 3. Ensuring a Valid Down to V
= 0 V
CC
RESET

Output

MANUAL RESET

The ADM811/ADM812 is equipped with a manual reset input. This input is designed to operate in a noisy environment where unwanted glitches could be induced. These glitches could be produced by the bouncing action of a switch contact, or where a manual reset switch may be located some distance away from the circuit (the cabling of which may pick-up noise).
The manual reset input is guaranteed to ignore logically valid inputs that are faster than 100 ns and to accept inputs longer in duration than 10 µs.
ENSURING A VALID RESET OUTPUT DOWN TO V
When VCC falls below 0.8 V, the ADM811/ADM812’s RESET no longer sinks current. Therefore, a high impedance CMOS logic input connected to RESET may drift to undetermined logic levels. To eliminate this problem, a 100 kresistor should be connected from RESET to ground.
–6–
= 0 V
CC
REV. C

OUTLINE DIMENSIONS

4-Lead Small Outline Transistor Package [SOT-143]
(RT-4)
Dimensions shown in millimeters
1.92 BSC
ADM811/ADM812
1.40
1.20
PIN 1
0.15
0.05
SEATING
PLANE
4
1
0.20 BSC
COMPLIANT TO JEDEC STANDARDS TO-253D
3.04
2.80
0.89
0.76
3
2.64
2.10
2
1.22
0.80
0.20
0.08
0.45
0.30
0.60
0.40
8 0
REV. C
–7–
ADM811/ADM812

Revision History

Location Page
2/03Data Sheet changed from REV. B to REV. C.
Changes FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Removed Note 2 from ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Removed Note from Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1/03Data Sheet changed from REV. A to REV. B.
Added ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additions to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Manual Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C00092–0–2/03(C)
5/02Data Sheet changed from REV. 0 to REV. A.
Deletion of ADM812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
–8–
PRINTED IN U.S.A.
REV. C
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