Analog Devices ADM708ARM, ADM708AR, ADM708AN, ADM707ARM, ADM707AR Datasheet

Low Cost ␮P

a

FEATURES
Guaranteed RESET Valid with V
190 ␮A Quiescent Current
Precision Supply-Voltage Monitor

4.65 V (ADM705/ADM707)

4.40 V (ADM706/ADM708)

200 ms Reset Pulsewidth
Debounced TTL/CMOS Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout

(ADM705/ADM706)
Active High Reset Output (ADM707/ADM708)
Voltage Monitor for Power-Fail or Low Battery

Warning
Superior Upgrade for MAX705–MAX708
Also Available in MicroSOIC Packages

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical ␮P Monitoring
Automotive Systems
Critical ␮P Power Monitoring

GENERAL DESCRIPTION

The ADM705–ADM708 are low cost µP supervisory circuits.
They are suitable for monitoring the 5 V power supply/battery
and can also monitor microprocessor activity.

The ADM705/ADM706 provide the following functions:

1. Power-On Reset output during power-up, power-down and

brownout conditions. The RESET output remains opera­tional with V

as low as 1 V.

CC

2. Independent watchdog timeout, WDO, that goes low if the

watchdog input has not been toggled within 1.6 seconds.

3. A 1.25 V threshold detector for power-fail warning, low
battery detection or to monitor a power supply other than
5V.

4. An active low debounced manual reset input (MR).

The ADM707/ADM708 differ in that:

1. A watchdog timer function is not available.

2. An active high reset output in addition to the active low
output is available.

= 1 V

CC

Supervisory Circuits

ADM705–ADM708

FUNCTIONAL BLOCK DIAGRAMS

WATCHDOG

INPUT (WDI)

MR

V

POWER-FAIL

INPUT (PFI)

MR

V

POWER-FAIL

INPUT (PFI)

Two supply-voltage monitor levels are available. The ADM705/
ADM707 generate a reset when the supply voltage falls below

4.65 V, while the ADM706/ADM708 require that the supply
fall below 4.40 V before a reset is issued.

All parts are available in 8-lead DIP and SOIC packages. The
ADM707 and ADM708 are also available in space-saving
microSOIC packages.

WATCHDOG
TRANSITION

DETECTOR

V

CC

250␮A

CC

4.65V*

1.25V

*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)

V

CC

250␮A

CC

4.65V*

1.25V

*VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)

WATCHDOG

TIMER

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

ADM705/
ADM706

RESET

GENERATOR

ADM707/
ADM708

WATCHDOG
OUTPUT (WDO)

RESET

POWER-FAIL
OUTPUT (PFO)

RESET

RESET

POWER-FAIL
OUTPUT (PFO)

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Fax: [phone] © Analog Devices, Inc., 2000

ADM705–ADM708–SPECIFICATIONS

(VCC = 4.75 V to 5.5 V, TA = T

MIN

to T

unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Test Conditions/Comments

V

Operating Voltage Range 1.0 5.5 V

CC

Supply Current 190 250 µA

Reset Threshold 4.5 4.65 4.75 V ADM705, ADM707

4.25 4.40 4.50 V ADM706, ADM708
Reset Threshold Hysteresis 40 mV
Reset Pulsewidth 160 200 280 ms
RESET Output Voltage V

RESET Output Voltage V

Watchdog Timeout Period (t
WDI Pulsewidth (t

)50 nsV

WP

) 1.00 1.60 2.25 sec

WD

– 1.5 V I

CC

0.4 V I

0.3 V V

0.3 V V

– 1.5 V ADM707, ADM708, I

CC

0.4 V ADM707, ADM708, I

= 800 µA

SOURCE

= 3.2 mA

SINK

= 1 V, I

CC

= 1.2 V, I

CC

= 0.4 V, VIH = VCC × 0.8

IL

SINK

SINK

= 50 µA

= 100 µA

SOURCE

= 1.2 mA

SINK

= 800 µA

WDI Input Threshold

Logic Low 0.8 V
Logic High 3.5 V

WDI Input Current 50 150 µA WDI = V

CC

–150 –50 µA WDI = 0 V

WDO Output Voltage V

– 1.5 V I

CC

0.4 V I

SOURCE

= 1.2 mA

SINK

= 800 µA

MR Pull-Up Current 100 250 600 µA MR = 0 V
MR Pulsewidth 150 ns
MR Input Threshold 0.8 V

2.0 V
MR to Reset Output Delay 250 ns

PFI Input Threshold 1.2 1.25 1.3 V
PFI Input Current –25 0.01 25 nA
PFO Output Voltage V

Specifications subject to change without notice.

– 1.5 V I

CC

0.4 V I

SOURCE

= 3.2 mA

SINK

= 800 µA

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

Input Current

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

CC

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

θ

JA

Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability

ORDERING GUIDE

Model Temperature Range Package Option

ADM705AN –40°C to +85°C N-8
ADM705AR –40°C to +85°C SO-8

ADM706AN –40°C to +85°C N-8
ADM706AR –40°C to +85°C SO-8

ADM707AN –40°C to +85°C N-8
ADM707AR –40°C to +85°C SO-8
ADM707ARM –40°C to +85°C RM-8

ADM708AN –40°C to +85°C N-8
ADM708AR –40°C to +85°C SO-8
ADM708ARM –40°C to +85°C RM-8

–2–

REV. B

ADM705–ADM708

PIN FUNCTION DESCRIPTION

Pin No.

ADM705 ADM707
ADM706 ADM708

Mnemonic DIP, SOIC DIP, SPOC MicroSOIC Function

MR 1 1 3 Manual Reset Input. When taken below 0.8 V, a RESET is gener-

ated. MR can be driven from TTL, CMOS logic or from a manual
reset switch as it is internally debounced. An internal 250 µA pull-up
current holds the input high when floating.

V

CC

GND 3 3 5 0 V. Ground reference for all signals.

PFI 4 4 6 Power-Fail Input. PFI is the noninverting input to the Power-Fail

PFO 5 5 7 Power-Fail Output. PFO is the output from the Power-Fail Compara-

WDI 6 N/A N/A Watchdog Input. WDI is a three-level input. If WDI remains either

NC N/A 6 8 No Connect.

RESET 7 7 1 Logic Output. RESET goes low for 200 ms when triggered. It can be

WDO 8 N/A N/A Logic Output. The Watchdog Output, WDO, goes low if the internal

RESET N/A 8 2 Logic Output. RESET is an active high output suitable for systems

2 2 4 5 V Power Supply Input.

Comparator. When PFI is less than 1.25 V, PFO goes low. If unused,
PFI should be connected to GND or V

tor. It goes low when PFI is less than 1.25 V.

high or low for longer than the watchdog timeout period, the watch­dog output WDO goes low. The timer resets with each transition at
the WDI input.

Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. The
watchdog timer is disabled when WDI is left floating or connected to
a three-state buffer.

triggered either by V

being below the reset threshold or by a low

CC

signal on the manual reset (MR) input. RESET will remain low
whenever V

is below the reset threshold (4.65 V in ADM705, 4.4 V

CC

in ADM706). It remains low for 200 ms after V
reset threshold or MR goes from low to high. A watchdog timeout
will not trigger RESET unless WDO is connected to MR.

watchdog timer times out as a result of inactivity on the WDI input. It
remains low until the watchdog timer is cleared. WDO also goes low
during low line conditions. Whenever V

WDO remains low. As soon as V
WDO goes high immediately.

that use active high RESET logic. It is the inverse of RESET.

.

CC

goes above the

CC

is below the reset threshold,

CC

goes above the reset threshold,

CC

REV. B

PIN CONFIGURATION

DIP, SOIC DIP, SOIC MicroSOIC

1

MR

V

GND

PFI

CC

1

ADM705/

2

3

(Not to Scale)

4

ADM706

TOP VIEW

8

7

6

5

WDO

RESET

WDI

PFO

1

MR

2

V

CC

3

GND

(Not to Scale)

4

PFI

NC = NO CONNECT

ADM707/

ADM708

TOP VIEW

8

7

6

5

RESET

RESET

NC

PFO

RESET

2

RESET

3

MR

V

4

CC

NC = NO CONNECT

ADM707/

ADM708

TOP VIEW

(Not to Scale)

–3–

8

NC

PFO

7

6

PFI

GND

5