Analog Devices ADM697AR, ADM697AQ, ADM697AN, ADM696SQ, ADM696AR Datasheet

1.3V

V

OUT

V

BATT

V

CC

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI) POWER FAIL

OUTPUT (PFO)

RESET

WATCHDOG

TIMER

BATT ON

OSC IN

OSC SEL

WATCHDOG
OUTPUT (WDO)

RESET

LOW LINE

LL

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TRANSITION DETECTOR

ADM696

1.3V

CE

OUT

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI) POWER FAIL

OUTPUT (PFO)

RESET

WATCHDOG

TIMER

OSC IN

OSC SEL

WATCHDOG
OUTPUT (WDO)

RESET

LOW LINE

LL

IN

RESET GENERATOR

TIMEBASE FOR RESET

AND WATCHDOG

WATCHDOG

TRANSITION DETECTOR

ADM697

CE

IN

Microprocessor

a

FEATURES
Superior Upgrade for MAX696/MAX697
Specified Over Temperature
Adjustable Low Line Voltage Monitor
Power OK/Reset Time Delay
Reset Assertion Down to 1 V V
Watchdog Timer—100 ms, 1.6 s, or Adjustable
Low Switch On Resistance

1.5 V Normal, 20 V in Backup
600 nA Standby Current
Automatic Battery Backup Switching (ADM696)
Fast On-Board Gating of Chip Enable Signals (ADM697)
Voltage Monitor for Power Fail or Low Battery Warning

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical mP Power Monitoring

CC

Supervisory Circuits

ADM696/ADM697

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

The ADM696/ADM697 supervisory circuits offer complete
single chip solutions for power supply monitoring and battery
control functions in microprocessor systems. These functions
include µP reset, backup-battery switchover, watchdog timer,
CMOS RAM write protection, and power failure warning.

The ADM696/ADM697 are available in 16-pin DIP and small
outline packages and provide the following functions:

1. Power-On Reset output during power-up, power-down and
brownout conditions. The RESET voltage threshold is
adjustable using an external voltage divider. The
output remains operational with V

as low as 1 V.

CC

2. A Reset pulse if the optional watchdog timer has not been
toggled within specified time.

3. Separate watchdog time-out and low line status outputs.

4. Adjustable reset and watchdog timeout periods.

5. A 1.3 V threshold detector for power fail warning, low bat­tery detection, or to monitor a power supply other than VCC.

6. Battery backup switching for CMOS RAM, CMOS micro­processor or other low power logic (ADM696).

7. Write protection of CMOS RAM or EEPROM (ADM697).

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

RESET

The ADM696/ADM697 is fabricated using an advanced epitaxial
CMOS process combining low power consumption (5 mW),
extremely fast Chip Enable gating (5 ns) and high reliability.
RESET assertion is guaranteed with VCC as low as 1 V. In
addition, the power switching circuitry is designed for minimal
voltage drop thereby permitting increased output current drive
of up to 100 mA without the need for an external pass transistor.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

(VCC = Full Operating Range, V

ADM696/ADM697–SPECIFICATIONS

P

arameter Min Typ Max Units Test Conditions/Comments

unless otherwise noted.)

= +2.8 V, TA = T

BATT

MIN

to T

VCC Operating Voltage Range 3.0 5.5 V
V

Operating Voltage Range 2.0 VCC – 0 3 V

BATT

BATTERY BACKUP SWITCHING (ADM696)

V

Output Voltage VCC – 0.05 VCC – 0.025 V I

OUT

V

in Battery Backup Mode V

OUT

Supply Current (Excludes I

) 1 1.95 mA I

OUT

VCC – 0.5 VCC – 0.25 V I

– 0.05 V

BATT

– 0.02 V I

BATT

Supply Current in Battery Backup Mode 0.6 1 µAVCC = 0 V, V
Battery Standby Current 5.5 V > VCC > V
(+ = Discharge, – = Charge) –0.1 +0.02 µAT

= 1 mA

OUT

≤ 100 mA

OUT

= 250 µA, VCC < V

OUT

= 100 mA

OUT

= +25°C

A

BATT

= 2.8 V

+ 0.2 V

BATT

BATT

– 0.2 V

–1 +0.02 µA

Battery Switchover Threshold 70 mV Power-Up
VCC – V

BATT

50 mV Power-Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.4 V I
BATT ON Output Short Circuit Current 7 mA BATT ON = V

0.5 1 25 µA BATT ON = V

= 1.6 mA

SINK

= 2.4 V Sink Current

OUT

, VCC = 0 V, Source Current

OUT

RESET AND WATCHDOG TIMER

Low Line Threshold (LLIN) 1.25 1.3 1.35 V VCC = +5 V, +3 V
Reset Timeout Delay 35 50 70 ms OSC SEL = HIGH, VCC= 5 V, TA = +25°C
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period, VCC = 5 V, TA = +25°C

70 100 140 ms Short Period, VCC = 5 V, TA = +25°C

Watchdog Timeout Period, External Clock 4032 4097 Cycles Long Period

960 1025 Cycles Short Period
Minimum WDI Input Pulse Width 50 ns VIL = 0.4, VIH = 3.5 V, VCC = 5 V
RESET Output Voltage @ VCC = +1 V 4 200 mV I
RESET, RESET Output Voltage 0.4 V I

0.4 V I

3.5 V I

LOW LINE, WDO Output Voltage 0.4 V I

3.5 V I

Output Short Circuit Source Current 1 3 25 µA
WDI Input Threshold VCC = 5 V

= 10 µA, VCC = 1 V

SINK

= 400 µA, VCC = 2 V, V

SINK

= 1.6 mA, 3 V < VCC < 5.5 V

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1.6 mA,

SINK

= 1 µA, VCC = 5 V

SOURCE

1

BATT

= 0 V

Logic Low 0.8 V
Logic High 3.5 V
WDI Input Current 20 50 µA WD1 = V

, (VCC) TA = +25°C

OUT

–50 –15 µA WD1 = 0 V, TA = +25°C

MAX

POWER FAIL DETECTOR

PFI Input Threshold 1.2 1.3 1.4 V VCC = +3 V, +5 V
PFI–LLIN Threshold Difference –50 ± 15 +50 mV VCC = +3 V, +5 V
PFI Input Current –25 ±0.01 +25 nA
LLIN Input Current –50 ±0.01 +50 nA
PFO Output Voltage 0.4 V I

3.5 V I

= 1.6 mA

SINK

= 1 µA, VCC = 5 V

SOURCE

PFO Short Circuit Source Current 1 3 25 µA PFI = Low, PFO = 0 V

CHIP ENABLE GATING (ADM697)

CEIN Threshold 0.8 V V

IL

3.0 V VIH, VCC = 5 V

CE

Pullup Current 3 µA

IN

CE

Output Voltage 0.4 V I

OUT

VCC – 0.5 V I
CE Propagation Delay 5 25 ns

= 1.6 mA

SINK
SOURCE

= 800 µA

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pullup Current 5 µA
OSC IN Frequency Range 0 250 kHz OSC SEL = 0 V
OSC IN Frequency with Ext. Capacitor 4 kHz OSC SEL = 0 V, C

NOTE

1

WDI is a three-level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ .

Specifications subject to change without notice.

= 47 pF

OSC

REV. 0–2–

ADM696/ADM697

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

BATT

OUT

+ 0.5 V

Input Current

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

BATT

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

JA

Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W

JA

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

θ

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . .–40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM696/ADM697 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

PIN CONFIGURATIONS

Model Temperature Range Package Option

WARNING!

ESD SENSITIVE DEVICE

ADM696AN –40°C to +85°C N-16
ADM696AR –40°C to +85°C R-16
ADM696AQ –40°C to +85°C Q-16
ADM696SQ –55°C to +125°C Q-16

ADM697AN –40°C to +85°C N-16
ADM697AR –40°C to +85°C R-16
ADM697AQ –40°C to +85°C Q-16
ADM697SQ –55°C to +125°C Q-16

V

BATT

V

OUT

V

GND

BATT ON

LOW LINE

OSC IN

OSC SEL

TEST

V

LL

GND

LOW LINE

OSC IN

OSC SEL

NC

CC

CC

IN

1
2

3

4

5

(Not to Scale)

6

7

8

1

2

3

4

5

(Not to Scale)

6

7

8

ADM696

TOP VIEW

ADM697

TOP VIEW

15
14

13

11

16

12

10

9

15

16

14

13

12

11

10

9

RESET

RESET

WDO

LL

IN

NC

WDI

PFO

PFI

RESET

RESET

WDO

CE
CE

WDI

PFO

PFI

IN

OUT

REV. 0

–3–

ADM696/ADM697

Pin No.

Mnemonic ADM696 ADM697 Function

PIN FUNCTION DESCRIPTION

V
V
V

CC

BATT

OUT

3 3 Power Supply Input +3 V to +5 V.
1 — Backup Battery Input. Connect to Ground if a backup battery is not used.
2 — Output Voltage, VCC or V

highest potential. V
V

if V

CC

OUT

and V

OUT

BATT

is internally switched to V

BATT

depending on which is at the

OUT

can supply up to 100 mA to power CMOS RAM. Connect V
are not used.

OUT

to

GND 4 5 0 V. Ground reference for all signals.
RESET 15 15 Logic Output. RESET goes low whenever LLIN falls below 1.3 V or when VCC falls below

the V

input voltage. RESET remains low for 50 ms after LLIN goes above 1.3 V,

BATT

RESET also goes low for 50 ms if the watchdog timer is enabled but not serviced within its
timeout period. The

RESET pulse width can be adjusted as shown in Table I.

WDI 11 11 Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer

than the watchdog timeout period,

RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.

PFI 9 9 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is

less than 1.3 V,

PFO goes low. Connect PFI to GND or V

OUT

when not used. See Figure 1.

PFO 10 10 Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI

is less than 1.3 V. The comparator is turned off and
V

.

BATT

CE

CE

IN

OUT

— 13 Logic Input. The input to the CE gating circuit. Connect to GND or V
— 12 Logic Output. CE

is above 1.3 V. If LLIN is below 1.3 V, CE

is a gated version of the CEIN signal. CE

OUT

OUT

BATT ON 5 — Logic Output. BATT ON goes high when V

It goes low when V

is internally switched to VCC. The output typically sinks 7 mA and

OUT

OUT

PFO goes low when VCC is below

OUT

tracks CEIN when LL

OUT

is forced high.

is internally switched to the V

if not used.

input.

BATT

IN

can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V

OUT

.

LOW LINE 6 6 Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as

LL

rises above 1.3 V.

IN

RESET 16 16 Logic Output. RESET is an active high output. It is the inverse of

RESET.

OSC SEL 8 8 Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal

oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low,
the external oscillator input, OSC IN, is enabled. OSC SEL has a 3 µA internal pullup. See

Table I and Figure 4.

OSC IN 7 7 Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock

to adjust both the reset delay and the watchdog time-out period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods.

WDO 14 14 Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low

for longer than the watchdog time-out period.
WDI. If WDI is unconnected or at midsupply,

when

LOW LINE goes low.

WDO is set high by the next transition at

WDO remains high. WDO also goes high

NC 12 2 No Connect. It should be left open.
LL

IN

13 4 Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V

reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a
RESET/

RESET output.

LOW LINE output signal. It also generates a

TEST — 1 This is a special test pin using during device manufacture. It should be connected to GND.

REV. 0–4–