Analog Devices ADM695, ADM694, ADM693, ADM691, ADM692 Datasheet

Microprocessor

4.65V

1

WATCHDOG

TRANSITION DETECTOR

1.3V

ADM691
ADM693
ADM695

V

OUT

V

BATT

V

CC

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

1

VOLTAGE DETECTOR = 4.65V (ADM691, ADM695)

4.40V (ADM693)

POWER FAIL
OUTPUT (PFO)

RESET

WATCHDOG

TIMER

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

BATT ON

OSC IN

OSC SEL

WATCHDOG
OUTPUT (WDO)

RESET

LOW LINE

CE

OUT

CE

IN

4.65V

1

RESET

GENERATOR

2

WATCHDOG

TRANSITION DETECTOR

(1.6s)

1.3V

ADM690
ADM692
ADM694

V

OUT

V

BATT

V

CC

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

1

VOLTAGE DETECTOR = 4.65V (ADM690, ADM694)

4.40V (ADM692)

2

RESET PULSE WIDTH = 50ms (ADM690, ADM692)

200ms (ADM694)

POWER FAIL
OUTPUT (PFO)

RESET

a

FEATURES
Superior Upgrade for MAX690–MAX695
Specified Over Temperature
Low Power Consumption (5 mW)
Precision Voltage Monitor
Reset Assertion Down to 1 V V
Low Switch On-Resistance 1.5 V Normal,

20 V in Backup
High Current Drive (100 mA)
Watchdog Timer—100 ms, 1.6 s, or Adjustable
600 nA Standby Current
Automatic Battery Backup Power Switching
Extremely Fast Gating of Chip Enable Signals (5 ns)
Voltage Monitor for Power Fail

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems

CC

Supervisory Circuits

ADM690–ADM695

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

The ADM690–ADM695 family of supervisory circuits offers
complete single chip solutions for power supply monitoring and
battery control functions in microprocessor systems. These
functions include µP reset, backup battery switchover, watchdog
timer, CMOS RAM write protection, and power failure warn­ing. The complete family provides a variety of configurations to
satisfy most microprocessor system requirements.

The ADM690, ADM692 and ADM694 are available in 8-pin
DIP packages and provide:

1. Power-on reset output during power-up, power-down and
brownout conditions. The
tional with V

as low as 1 V.

CC

RESET output remains opera-

2. Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.

3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.

4. A 1.3 V threshold detector for power fail warning, low battery
detection, or to monitor a power supply other than +5 V.

The ADM691, ADM693 and ADM695 are available in 16-pin
DIP and small outline packages and provide three additional
functions.

1. Write protection of CMOS RAM or EEPROM.

2. Adjustable reset and watchdog timeout periods.

3. Separate watchdog timeout, backup battery switchover, and
low V

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

status outputs.

CC

The ADM690–ADM695 family is fabricated using an advanced
epitaxial CMOS process combining low power consumption
(5 mW), extremely fast Chip Enable gating (5 ns) and high reli­ability.

RESET assertion is guaranteed with VCC as low as 1 V.
In addition, the power switching circuitry is designed for mini­mal voltage drop thereby permitting increased output current
drive of up to 100 mA without the need for an external pass
transistor.

© Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] Fax: [phone]

ADM690–ADM695–SPECIFICA TIONS

(VCC = Full Operating Range, V
T

unless otherwise noted)

MAX

= +2.8 V, TA = T

BATT

Parameter Min Typ Max Units Test Conditions/Comments

BATTERY BACKUP SWITCHING

V

Operating Voltage Range

CC

ADM690, ADM691, ADM694, ADM695 4.75 5.5 V
ADM692, ADM693 4.5 5.5 V

V

Operating Voltage Range

BATT

ADM690, ADM691, ADM694, ADM695 2.0 4.25 V
ADM692, ADM693 2.0 4.0 V

V

Output Voltage VCC – 0.05 VCC – 0.025 V I

OUT

V

in Battery Backup Mode V

OUT

Supply Current (Excludes I

) 1 1.95 mA I

OUT

V

– 0.5 VCC – 0.25 V I

CC
BATT

– 0.05 V

– 0.02 V I

BATT

Supply Current in Battery Backup Mode 0.6 1 µAV
Battery Standby Current 5.5 V > V

(+ = Discharge, – = Charge) –0.1 +0.02 µAT

= 1 mA

OUT

≤ 100 mA

OUT

= 250 µA, VCC < V

OUT

= 100 mA

OUT

= 0 V, V

CC

= +25°C

A

CC

BATT

> V

= 2.8 V

+ 0.2 V

BATT

BATT

– 0.2 V

–1.0 +0.02 µA
Battery Switchover Threshold 70 mV Power Up
V

CC

– V

BATT

50 mV Power Down
Battery Switchover Hysteresis 20 mV
BATT ON Output Voltage 0.3 V I
BATT ON Output Short Circuit Current 35 mA BATT ON = V

= 3.2 mA

SINK

= 4.5 V Sink Current

OUT

0.5 1 25 µA BATT ON = 0 V Source Current

RESET AND WATCHDOG TIMER

Reset Voltage Threshold

ADM690, ADM691, ADM694, ADM695 4.5 4.65 4.73 V

ADM692, ADM693 4.25 4.4 4.48 V
Reset Threshold Hysteresis 40 mV
Reset Timeout Delay

ADM690, ADM691, ADM692, ADM693 35 50 70 ms OSC SEL = HIGH, V

ADM694, ADM695 140 200 280 ms OSC SEL = HIGH, V
Watchdog Timeout Period, Internal Oscillator 1.0 1.6 2.25 s Long Period, V

70 100 140 ms Short Period, V

CC
CC

= 5 V, TA = +25°C

CC

= 5 V, TA = +25°C

CC

= 5 V, TA = +25°C

= 5 V, TA = +25°C

Watchdog Timeout Period, External Clock 3840 4097 Cycles Long Period

768 1025 Cycles Short Period

Minimum WDI Input Pulse Width 50 ns V

RESET Output Voltage @ VCC = +1 V 4 200 mV I
RESET, LOW LINE Output Voltage 0.4 V I

3.5 V I

RESET, WDO Output Voltage 0.4 V I

3.5 V I

= 0.4, VIH = 3.5 V

IL

= 10 µA, VCC = 1 V

SINK

= 1.6 mA, VCC = 4.25 V

SINK

= 1 µA, VCC = 5 V

SOURCE

= 1.6 mA, VCC = 5 V

SINK

= 1 µA, VCC = 4.25 V

SOURCE

Output Short Circuit Source Current 1 3 25 µA
Output Short Circuit Sink Current 25 mA
WDI Input Threshold V

CC

= 5 V

1

Logic Low 0.8 V

Logic High 3.5 V
WDI Input Current 20 50 µA WDI = V

, TA = +25°C

OUT

–50 –15 µA WDI = 0 V, TA = +25°C

POWER FAIL DETECTOR

PFI Input Threshold 1.25 1.3 1.35 V V

= +5 V

CC

PFI Input Current –25 ±0.01 +25 nA
PFO Output Voltage 0.4 V I

3.5 V I

= 3.2 mA

SINK
SOURCE

= 1 µA

PFO Short Circuit Source Current 1 3 25 µA PFI = Low, PFO = 0 V
PFO Short Circuit Sink Current 25 mA PFI = High, PFO = V

OUT

CHIP ENABLE GATING

CE

Threshold 0.8 V V

IN

3.0 V V

CE

Pull-Up Current 3 µA

IN

CE

Output Voltage 0.4 V I

OUT

V

– 1.5 V I

OUT

V

– 0.05 V I

OUT

IL
IH

= 3.2 mA

SINK

= 3.0 mA

SOURCE

= 1 µA, VCC = 0 V

SOURCE

CE Propagation Delay 5 9 ns

MIN

to

–2–

REV. A

ADM690–ADM695

Parameter Min Typ Max Units Test Conditions/Comments

OSCILLATOR

OSC IN Input Current ±2 µA
OSC SEL Input Pull-Up Current 5 µA
OSC IN Frequency Range 0 250 kHz OSC SEL = 0 V
OSC IN Frequency with External Capacitor 4 kHz OSC SEL = 0 V, C

NOTE

1

WDI is a three level input which is internally biased to 38% of VCC and has an input impedance of approximately 125 kΩ.

Specifications subject to change without notice.

= 47 pF

OSC

ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

BATT

OUT

+ 0.5 V

Input Current

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

BATT

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .400 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W

JA

Power Dissipation, Q-8 DIP . . . . . . . . . . . . . . . . . . . .500 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 125°C/W

JA

Power Dissipation, N-16 DIP . . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

JA

Power Dissipation, Q-16 DIP . . . . . . . . . . . . . . . . . . . 600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W

JA

Power Dissipation, R-16 SOIC . . . . . . . . . . . . . . . . . .600 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . .–55°C to +125°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

ORDERING GUIDE

Model Temperature Range Package Option

ADM690AN –40°C to +85°C N-8
ADM690AQ –40°C to +85°C Q-8
ADM690SQ –55°C to +125°C Q-8

ADM691AN –40°C to +85°C N-16
ADM691AR –40°C to +85°C R-16
ADM691AQ –40°C to +85°C Q-16
ADM691SQ –55°C to +125°C Q-16

ADM692AN –40°C to +85°C N-8
ADM692AQ –40°C to +85°C Q-8
ADM692SQ –55°C to +125°C Q-8

ADM693AN –40°C to +85°C N-16
ADM693AR –40°C to +85°C R-16
ADM693AQ –40°C to +85°C Q-16
ADM693SQ –55°C to +125°C Q-16

ADM694AN –40°C to +85°C N-8
ADM694AQ –40°C to +85°C Q-8
ADM694SQ –55°C to +125°C Q-8

ADM695AN –40°C to +85°C N-16
ADM695AR –40°C to +85°C R-16
ADM695AQ –40°C to +85°C Q-16
ADM695SQ –55°C to +125°C Q-16

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods of time may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADM690–ADM695 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.

REV. A

–3–

WARNING!

ESD SENSITIVE DEVICE

ADM690–ADM695

Mnemonic Function

PIN FUNCTION DESCRIPTION

V
V
V

CC
BATT
OUT

Power Supply Input: +5 V Nominal.
Backup Battery Input. Connect to Ground if a backup battery is not used.
Output Voltage, VCC or V

can supply up to 100 mA to power CMOS RAM. Connect V

is internally switched to V

BATT

depending on which is at the highest potential. V

OUT

to VCC if V

OUT

OUT

and V

are not used.

BATT

OUT

GND 0 V. Ground reference for all signals.
RESET Logic Output. RESET goes low if

1. V

falls below the Reset Threshold

CC

2. V

falls below V

CC

BATT

3. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM690/ADM691/ADM694/ADM695 and 4.4 V for the ADM692 and

ADM693.
after V
serviced within its timeout period. The
shown in Table I. The

RESET remains low for 50 ms (ADM690/ADM691/ADM692/ADM693) or 200 ms (ADM694/ADM695)

returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is enabled but not

CC

RESET pulse width can be adjusted on the ADM691/ADM693/ADM695 as

RESET output has an internal 3 µA pull up, and can either connect to an open collector

Reset bus or directly drive a CMOS gate without an external pull-up resistor.

WDI Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout

period,

RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog

timer may be disabled if WDI is left floating or is driven to midsupply.

PFI Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V,

goes low. Connect PFI to GND or V

when not used.

OUT

PFO

PFO Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The

comparator is turned off and

CE

CE

IN
OUT

Logic Input. The input to the CE gating circuit. Connect to GND or V
Logic Output. CE

threshold. If V

OUT

is below the reset threshold, CE

CC

BATT ON Logic Output. BATT ON goes high when V

PFO goes low when VCC is below V

is a gated version of the CEIN signal. CE

is forced high. See Figures 5 and 6.

OUT

is internally switched to the V

OUT

.

BATT

if not used.

OUT

tracks CEIN when VCC is above the reset

OUT

input. It goes low when V

BATT

OUT

is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of V

OUT

.

LOW LINE Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises

above the reset threshold.

RESET Logic Output. RESET is an active high output. It is the inverse of

RESET.

OSC SEL Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets

the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3 µA internal pull up, (see Table I).

OSC IN Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external

capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watch­dog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM691/ADM693) or 200 ms typ (ADM695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.

WDO Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the

watchdog timeout period.

WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,

the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.

–4–

REV. A

PIN CONFIGURATIONS

ADM690–ADM695

V

BATT

V

OUT

V

GND

BATT ON
LOW LINE

OSC IN

OSC SEL

CC

1

2

3
4

5

(Not to Scale)

6

7

8

ADM691
ADM693
ADM695

TOP VIEW

16

15
14

13

12

11

10

9

RESET

RESET

WDO

CE

IN

CE

OUT

WDI

PFO

PFI

V

OUT

V

GND

PFI

CC

1

2

3

(Not to Scale)

4

ADM690
ADM692
ADM694

TOP VIEW

8

7

6
5

V

BATT

RESET
WDI
PFO

PRODUCT SELECTION GUIDE

Part Nominal Reset Nominal V

CC

Nominal Watchdog Battery Backup Base Drive Chip Enable

Number Time Reset Threshold Timeout Period Switching Ext PNP Signals

ADM690 50 ms 4.65 V 1.6 s Yes No No
ADM691 50 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM692 50 ms 4.4 V 1.6 s Yes No No
ADM693 50 ms or ADJ 4.4 V 100 ms, 1.6 s, ADJ Yes Yes Yes
ADM694 200 ms 4.65 V 1.6 s Yes No No
ADM695 200 ms or ADJ 4.65 V 100 ms, 1.6 s, ADJ Yes Yes Yes

CIRCUIT INFORMATION
Battery Switchover Section

The battery switchover circuit compares VCC to the V
input, and connects V
occurs when V
when V

CC

is 50 mV higher than V

CC

is 70 mV greater than V

to whichever is higher. Switchover

OUT

BATT

as VCC falls, and

BATT

as VCC rises. This

20 mV of hysteresis prevents repeated rapid switching if V

BATT

CC

falls very slowly or remains nearly equal to the battery voltage.

If the continuous output current requirement at V
100 mA or if a lower V

CC–VOUT

voltage differential is desired,

OUT

exceeds

an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.

A 20 Ω MOSFET switch connects the V

input to V

BATT

OUT

during battery backup. This MOSFET has very low input-to­output differential (dropout voltage) at the low current levels
required for battery back up of CMOS RAM or other low
power CMOS circuitry. The supply current in battery back up
is typically 0.6 µA.

The ADM690/ADM691/ADM694/ADM695 operates with
battery voltages from 2.0 V to 4.25 V and the ADM692/ADM693
operates with battery voltages from 2.0 V to 4.0 V. High value
capacitors, either standard electrolytic or the farad size double
layer capacitors, can also be used for short-term memory back
up. A small charging current of typically 10 nA (0.1 µA max)
flows out of the V

terminal. This current is useful for

BATT

maintaining rechargeable batteries in a fully charged condition.
This extends the life of the back up battery by compensating
for its self discharge current. Also note that this current poses
no problem when lithium batteries are used for back up since
the maximum charging current (0.1 µA) is safe for even the

Figure 1. Battery Switchover Schematic

During normal operation with VCC higher than V
ternally switched to V

via an internal PMOS transistor

OUT

, VCC is in-

BATT

switch. This switch has a typical on-resistance of 1.5 Ω and can
supply up to 100 mA at the V

terminal. V

OUT

is normally

OUT

smallest lithium cells.
If the battery-switchover section is not used, V

connected to GND and V

should be connected to VCC.

OUT

should be

BATT

used to drive a RAM memory bank which may require instanta­neous currents of greater than 100 mA. If this is the case then a
bypass capacitor should be connected to V

. The capacitor

OUT

will provide the peak current transients to the RAM. A capaci­tance value of 0.1 µF or greater may be used.

REV. A

–5–