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Low Voltage Supervisory Circuits with
FEATURES
Precision low voltage monitoring
9 reset threshold options: 1.58 V to 4.63 V
140 ms (min) reset timeout
Watchdog timer with 1.6 sec timeout
Manual reset input
Reset output stages
Push-pull active-low
Open-drain active-low
Push-pull active-high
Low power consumption (7 μA)
Guaranteed reset output valid to V
Power supply glitch immunity
Specified from −40°C to +125°C
5-lead SOT-23 package
APPLICATIONS
Microprocessor systems
Computers
Controllers
Intelligent instruments
Portable equipment
= 1 V
CC
Watchdog and Manual Reset in 5-Lead SOT-23
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
FUNCTIONAL BLOCK DIAGRAM
ADM6823
V
MR
CC
V
REF
DEBOUNCE
GND WDI
RESET
GENERATOR
WATCHDOG
DETECTOR
Figure 1.
V
CC
RESET
04535-001
GENERAL DESCRIPTION
The ADM682x are supervisory circuits that monitor power
supply voltage levels and code execution integrity in
microprocessor-based systems. As well as providing power-on
reset signals, an on-chip watchdog timer can reset the
microprocessor if it fails to strobe within a preset timeout
period. A reset signal can also be asserted by means of an
external push-button through a manual reset input. The parts
feature different combinations of watchdog input and manual
reset input and output stage configurations, as shown in
Tabl e 1.
Table 1. Selection Table
Part No. Watchdog Timer Manual Reset
ADM6821 Yes Yes - Push-Pull
ADM6822 Yes Yes Open-Drain ADM6823 Yes Yes Push-Pull ADM6824 Yes - Push-Pull Push-Pull
ADM6825 - Yes Push-Pull Push-Pull
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Each part is available in nine reset threshold options, ranging
from 1.58 V to 4.63 V. The reset and watchdog timeout periods
are fixed at 140 ms (min) and 1.6 sec (typ), respectively.
The ADM682x are available in 5-lead SOT-23 packages and
ically consume only 7 μA, making them suitable for use in
typ
low power, portable applications.
Output Stage
RESET
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
RESET
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
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TABLE OF CONTENTS
Specifications..................................................................................... 3
Watc h d og I nput .............................................................................9
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reset Output ................................................................................. 9
Manual Reset Input ...................................................................... 9
REVISION HISTORY
6/05—Revision 0: Initial Version
Application Information................................................................ 10
Watc h d og I nput C ur r ent ........................................................... 10
Negative-Going V
Ensuring Reset Valid to V
Watchdog Software Considerations......................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
Transi e n t s ................................................ 10
CC
= 0 V........................................... 10
CC
Rev. 0 | Page 2 of 12
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ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
SPECIFICATIONS
VCC = 4.5 V to 5.5 V for ADM682_L/M; VCC = 2.7 V to 3.6 V for ADM682_T/S/R; VCC = 2.1 V to 2.75 V for ADM682_Z/Y; VCC = 1.53 V
to 2.0 V for ADM682_W/V; T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY
VCC Operating Voltage Range 1 5.5 V
Supply Current 10 20 μA
7 16 μA
RESET THRESHOLD VOLTAGE
ADM682xL
ADM682xM
ADM682xT
ADM682xS
ADM682xR
ADM682xZ
ADM682xY
ADM682xW
ADM682xV
RESET THRESHOLD TEMPERATURE COEFFICIENT 60 ppm/°C
RESET THRESHOLD HYSTERESIS 2 x V
VCC TO RESET DELAY 20 μs
RESET TIMEOUT PERIOD 140 200 280 ms
RESET Output Voltage
VOL (Push-Pull or Open-Drain) 0.3 V VCC > = 1 V, I
0.3 V VCC > = 1.2 V, I
0.3 V VCC > = 2.55 V, I
0.4 V VCC > = 4.25 V, I
VOH (Push-Pull Only) 0.8 × V
0.8 × V
0.8 × V
RESET OUTPUT LEAKAGE CURRENT (Open-Drain
Only)
RESET OUTPUT VOLTAGE (Push-Pull Only)
V
OH
0.8 × V
0.8 × V
0.8 × V
V
OL
0.3 V VCC > = 3.15 V, I
0.4 V VCC > = 4.75 V, I
MANUAL RESET INPUT
(ADM6821/ADM6822/ADM6823/ADM6825)
MR Input Threshold
V
IL
V
IH
MR Input Pulse Width
MR Glitch Rejection
MR to Reset Delay
MR Pull-Up Resistance
= –40°C to +125°C, unless otherwise noted.
A
4.50 4.63 4.75 V
4.25 4.38 4.50 V
3.00 3.08 3.15 V
2.85 2.93 3.00 V
2.55 2.63 2.70 V
2.25 2.32 2.38 V
2.12 2.19 2.25 V
1.62 1.67 1.71 V
1.52 1.58 1.62 V
TH
V VCC > = 1.8 V, I
CC
V VCC > = 3.15 V, I
CC
V VCC > = 4.75 V, I
CC
1 μA
0.8 × V
V VCC > = 1 V, I
CC
V VCC > = 1.5 V, I
CC
V VCC > = 2.55 V, I
CC
V VCC > = 4.25 V, I
CC
0.3 V VCC > = 1.8 V, I
0.3 × V
0.7 × V
V
CC
1 μs
100 ns
200 ns
25 50 75 kΩ
WDI and MR
WDI and MR
mV
VTH − VCC = 100 mV
RESET not asserted
V
CC
unconnected, VCC = 5.5 V
unconnected, VCC = 3.6 V
= 50 μA
SINK
= 100 μA
SINK
= 1.2 mA
SINK
= 3.2 mA
SINK
= 200 μA
SOURCE
= 500 μA
SOURCE
= 800 μA
SOURCE
= 1 μA
SOURCE
= 100 μA
SOURCE
= 500 μA
SOURCE
= 800 μA
SOURCE
= 500 μA
SINK
= 1.2 mA
SINK
= 3.2 mA
SINK
Rev. 0 | Page 3 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
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Parameter Min Typ Max Unit Test Conditions/Comments
WATCHDOG INPUT
(ADM6821/ADM6822/ADM6823/ADM6824)
Watchdog Timeout Period 1.12 1.6 2.40 sec
WDI Pulse Width 50 ns
WDI Input Threshold
V
IL
V
IH
WDI Input Current 120 160 μA V
0.3 × V
0.7 × V
−20 −15
V
CC
μA V
V
CC
WDI
WDI
= V
= 0
CC
Rev. 0 | Page 4 of 12
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ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
V
CC
Output Current (RESET, RESET)
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
Soldering Temperature
Sn/Pb 240°C, 30 sec
Pb-Free 260°C, 40 sec
−0.3 V to +6 V
20 mA
−40°C to +125°C
−65°C to +150°C
170°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
ma
y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 12
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
RESET
ADM6821
2
GND
MR
TOP VIEW
(Not to Scale)
3
Figure 2. ADM6821 Pin Configuration
1
RESET
ADM6822/
2
GND
ADM6823
TOP VIEW
(Not to Scale)
MR
3
Figure 3. ADM6822/ADM6823 Pin Configuration
V
5
CC
4
WDI
04535-002
Figure 4. ADM6824 Pin Configuration
V
5
CC
4
WDI
04535-003
Figure 5. ADM6825 Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Name Description
1
RESET
(ADM6822/ADM6823/ADM6824/ADM6825)
Active-Low Reset Output. Asserted whenever V
Open-Drain Output Stage for the ADM6822.
Push-Pull Output Stage for the ADM6823/ADM6824/ADM6825.
RESET (ADM6821) Active-High Push-Pull Reset Output.
2 GND
3
MR (ADM6821/ADM6822/ADM6823) Manual Reset Input. This is an active-low input, which, when forced low for at
Ground.
least 1 μs, generates a reset. It features a 50 kΩ internal pull-up.
RESET (ADM6824/ADM6825) Active-High Push-Pull Reset Output.
4
WDI
(ADM6821/AD
M6822/ADM6823/ADM6824)
Watchdog Input. Generates a reset if the voltage on the pin remains low or high
for the duration of the watchdog timeout. The timer is cleared if a logic transition
occurs on this pin or if a reset is generated.
5 V
(ADM6825)
MR
CC
Manual Reset Input.
Power Supply Voltage Being Monitored.
RESET
GND
RESET
RESET
GND
RESET
1
ADM6824
2
TOP VIEW
(Not to Scale)
3
1
ADM6825
2
TOP VIEW
(Not to Scale)
3
is below the reset threshold, VTH.
CC
V
5
CC
4
WDI
04535-004
V
5
CC
4
MR
04535-005
Rev. 0 | Page 6 of 12
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ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
TYPICAL PERFORMANCE CHARACTERISTICS
10.0
9.5
9.0
8.5
8.0
7.5
7.0
(μA)
6.5
CC
I
6.0
5.5
5.0
4.5
4.0
3.5
Figure 6. Supply Current vs. Temperature
VCC = 5V
VCC = 3.3V
VCC = 1.5V
TEMPERATURE (°C)
120–40 –20 0 20 40 60 80 100
04535-006
1.20
1.15
1.10
1.05
1.00
0.95
NORMALIZED WATCHDOG TIMEOUT
0.90
TEMPERATURE (°C)
Figure 9. Normalized Watchdog Timeout Period vs. Temperature
120–40 0–20 4020 1008060
04535-009
1.20
1.15
1.10
1.05
1.00
0.95
0.90
NORMALIZED RESET TIMEOUT
0.85
0.80
TEMPERATURE (°C)
Figure 7. Normalized RESET Timeout Period vs. Temperature
100
90
80
70
60
50
40
30
TO RESET DELAY (μs)
CC
V
20
10
0
TEMPERATURE (°C)
Figure 8. V
to RESET Output Delay vs. Temperature
CC
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
NORMALIZED RESET THRESHOLD
0.96
120–40 0–20 4020 1008060
04535-007
0.95
TEMPERATURE (°C)
120–40 0–20 4020 1008060
04535-010
Figure 10. Normalized RESET Threshold vs. Temperature
160
140
120
100
80
60
40
MINIMUM PULSE WIDTH (μs)
VCC = 2.93V
20
120–40 0–20 4020 1008060
04535-008
0
Figure 11. Maximum V
RESET THRESHOLD OVERDRIVE (mV)
Transient Duration vs. RESET Threshold Overdrive
CC
VCC = 4.63V
100010 100
04535-011
Rev. 0 | Page 7 of 12
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0.20
VCC = 2.9V
2.92
VCC = 2.9V
(V)
V
OUT
0.15
0.10
0.05
2.90
2.88
(V)
OUT
V
2.86
2.84
0
I
(mA)
SINK
Figure 12. Voltage Output Low vs. I
SINK
70123456
04535-017
2.82
I
(mA)
SOURCE
Figure 13. Voltage Output High vs. I
SOURCE
1.00 0.2 0.4 0.6 0.8
04535-018
Rev. 0 | Page 8 of 12
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ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
CIRCUIT DESCRIPTION
The ADM682x provide microprocessor supply voltage
supervision by controlling the microprocessor’s reset input.
Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when
the supply voltage is below a preset threshold. In addition, the
ADM682x allow supply voltage stabilization with a fixed
timeout before the reset deasserts after the supply voltage rises
above the threshold.
Problems with microprocessor code execution can be
m
onitored and corrected with a watchdog timer (ADM6821/
ADM6822/ADM6823/ADM6824). When watchdog strobe
instructions are included in microprocessor code, a watchdog
timer detects if the microprocessor code breaks down or
becomes stuck in an infinite loop. If this happens, the watchdog
timer asserts a reset pulse, which restarts the microprocessor in
a known state.
If the user detects a problem with the system’s operation,
a ma
nual reset input is available (ADM6821/ADM6822/
ADM6823/ADM6825) to reset the microprocessor by means
of an external push-button, for example.
RESET OUTPUT
The ADM6821 features an active-high push-pull reset output.
The ADM6822 features an active-low open-drain reset output,
while the ADM6823 features an active-low push-pull output.
The ADM6824/ADM6825 feature dual active-low and activehigh push-pull reset outputs. For active-low and active-high
outputs, the reset signal is guaranteed to be logic low and logic
high, respectively, for V
The reset output is asserted when V
threshold (V
), when MR is driven low, or when WDI is not
TH
serviced within the watchdog timeout period (t
remains asserted for the duration of the reset active timeout
period (t
) after VCC rises above the reset threshold, after MR
RP
transitions from low to high, or after the watchdog timer times
out.
Figure 14 shows the reset outputs.
V
CC
V
CC
1V
0V
V
RESET
RESET
CC
0V
V
CC
1V
0V
down to 1 V.
CC
is below the reset
CC
V
TH
t
RP
t
RP
Figure 14. Reset Timing Diagram
t
RD
). Reset
WD
V
TH
t
RD
04535-012
MANUAL RESET INPUT
The ADM6821/ADM6822/ADM6823/ADM6825 feature a
manual reset input (
reset output. When
), which, when driven low, asserts the
MR
transitions from low to high, reset
MR
remains asserted for the duration of the reset active timeout
period before deasserting. The
input has a 50 kΩ internal
MR
pull-up so that the input is always high when unconnected. An
external push-button switch can be connected between
MR
and
ground so that the user can generate a reset. Debounce circuitry
is integrated on-chip for this purpose. Noise immunity is
provided on the
up to 100 ns (typ) are ignored. A 0.1 μF capacitor between
input, and fast, negative-going transients of
MR
MR
and ground provides additional noise immunity.
WATCHDOG INPUT
The ADM6821/ADM6822/ADM6823/ADM6824 feature a
watchdog timer, which monitors microprocessor activity. A
timer circuit is cleared with every low-to-high or high-to-low
logic transition on the watchdog input pin (WDI), which
detects pulses as short as 50 ns. If the timer counts through the
preset watchdog timeout period (t
microprocessor is required to toggle the WDI pin to avoid
being reset. Failure of the microprocessor to toggle WDI within
the timeout period therefore indicates a code execution error,
and the reset pulse generated restarts the microprocessor in a
known state.
In addition to logic transitions on WDI, the watchdog timer is
lso cleared by a reset assertion due to an undervoltage condi-
a
tion on V
or MR being pulled low. When reset is asserted, the
CC
watchdog timer is cleared and does not begin counting again
until reset deassserts. The watchdog timer can be disabled by
leaving WDI floating or by three-stating the WDI driver.
V
RESET
WDI
V
CC
CC
1V
0V
V
CC
0V
V
CC
0V
V
TH
t
RP
Figure 15. Watchdog Timing Diagram
), reset is asserted. The
WD
t
t
RD
WD
04535-013
Rev. 0 | Page 9 of 12
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APPLICATION INFORMATION
WATCHDOG INPUT CURRENT
To minimize watchdog input current (and minimize overall
power consumption), leave WDI low for the majority of the
watchdog timeout period. When driven high, WDI can draw as
much as 160 μA. Pulsing WDI low-high-low at a low duty cycle
reduces the effect of the large input current. When WDI is
unconnected, a window comparator disconnects the watchdog
timer from the reset output circuitry so that reset is not asserted
when the watchdog timer times out.
NEGATIVE-GOING VCC TRANSIENTS
To avoid unnecessary resets caused by fast power supply
transients, the ADM682x are equipped with glitch rejection
circuitry. The typical performance characteristic in Figure 11
pl
ots V
transient duration versus. the transient magnitude.
CC
The curves show combinations of transient magnitude and
duration for which a reset is not generated for the 4.63 V and
2.93 V reset threshold parts. For example, with the 2.93 V
threshold, a transient that goes 100 mV below the threshold and
lasts 8 μs typically does not cause a reset, but if the transient is
any bigger in magnitude or duration, a reset is generated. An
optional 0.1 μF bypass capacitor mounted close to V
additional glitch rejection.
provides
CC
WATCHDOG SOFTWARE CONSIDERATIONS
In implementing the microprocessor’s watchdog strobe code,
quickly switching WDI low-high and then high-low
(minimizing WDI high time) is desirable for current
consumption reasons. However, a more effective way of using
the watchdog function can be considered.
A low-high-low WDI pulse within a given subroutine prevents
he watchdog from timing out. However, if the subroutine
t
becomes stuck in an infinite loop, the watchdog could not
detect this because the subroutine continues to toggle WDI. A
more effective coding scheme for detecting this error involves
using a slightly longer watchdog timeout. In the program that
calls the subroutine, WDI is set high. The subroutine sets WDI
low when it is called. If the program executes without error,
WDI is toggled high and low with every loop of the program. If
the subroutine enters an infinite loop, WDI is kept low, the
watchdog times out, and the microprocessor is reset.
START
SET WDI
HIGH
RESET
ENSURING RESET VALID TO VCC = 0 V
Both active-low and active-high reset outputs are guaranteed to
be valid for V
resistor with push-pull configured reset outputs, valid outputs
for V
as low as 0 V are possible. For an active-low reset
CC
output, a resistor connected between
the output low when it is unable to sink current. For the activehigh case, a resistor connected between RESET and V
the output high when it is unable to source current. A large
resistance such as 100 kΩ should be used so that it does not
overload the reset output when V
V
CC
ADM6822/
ADM6823/
ADM6824/
ADM6825
as low as 1 V. However, by using an external
CC
and ground pulls
RESET
is above 1 V.
CC
V
CC
RESET
100kΩ
GND GND
Figure 16. Ensuring Reset Valid to V
ADM6821/
ADM6824/
ADM6825
CC
RESET
= 0 V
CC
100kΩ
pulls
04535-015
PROGRAM
CODE
INFINITE LOOP:
WATCHDOG
SUBROUTINE
SET WDI
LOW
RETURN
Figure 17. Watchdog Flow Diagram
V
CC
RESET RESET
ADM6823
WDI I/OMR
Figure 18. Typical Application Circuit
TIMES OUT
μP
04535-014
04535-016
Rev. 0 | Page 10 of 12
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OUTLINE DIMENSIONS
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
2.90 BSC
1.60 BSC
1.30
1.15
0.90
0.15 MAX
5
123
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-178-AA
1.90
BSC
0.50
0.30
4
2.80 BSC
0.95 BSC
1.45 MAX
SEATING
PLANE
0.22
0.08
10°
5°
0°
0.60
0.45
0.30
Figure 19. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Di
mensions shown in millimeters
ADM682 x x YRJZ-RL7
ORDERING QUANTITY
RL7: 3,000 PIECE REEL
Z: LEAD-FREERESET
PACKAGE CODE
RJ: 5-LEAD SOT-23
04535-019
HRESHOLD
NUMBER
L: 4.63V
M: 4.38V
T: 3.08V
S: 2.93V
R: 2.63V
Z: 2.32V
Y: 2.19V
W: 1.67V
V: 1.58V
GENERIC NUMBER
TEMPERATURE RANGE
Y: –40°C TO +125°C
(1 TO 5)
Figure 20. Ordering Code Structure
ORDERING GUIDE
Standard Models
ADM6821SYRJZ-
2
RL7
ADM6822SYRJZ-RL722.93 140
ADM6822TYRJZ-RL723.08 140
ADM6823SYRJ-R7 2.93 140
ADM6823SYRJZ-RL722.93 140
ADM6823TYRJ-R7 3.08 140
ADM6823TYRJZ-RL723.08 140
ADM6824TYRJZ-R723.08 140
ADM6825TYRJZ-R723.08 140
1
If ordering nonstandard models, complete the ordering code shown in Figure 20 by inserting the part number and reset threshold suffixes. Contact Sales for
availability of nonstandard models.
2
Z = Pb-free part.
1
Reset Threshold (V) Reset Timeout (ms) Temperature Range Quantity Package Option Branding
2.93 140
Rev. 0 | Page 11 of 12
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
3k RJ-5 N0A
3k RJ-5 N0B
3k RJ-5 N0B
3k RJ-5 N0C
3k RJ-5 N0Q
3k RJ-5 N0C
3k RJ-5 N0Q
3k RJ-5 N0D
3k RJ-5 N0E
ADM6821/ADM6822/ADM6823/ADM6824/ADM6825
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NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04535–0–6/05(0)
Rev. 0 | Page 12 of 12
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