ANALOG DEVICES ADM1485 Service Manual
5 V Low Power
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a
FEATURES
Meets EIA RS-485 Standard
30 Mbps Data Rate
Single 5 V Supply
–7 V to +12 V Bus Common-Mode Range
High Speed, Low Power BiCMOS
Thermal Shutdown Protection
Short-Circuit Protection
Driver Propagation Delay: 10 ns
Receiver Propagation Delay: 15 ns
High-Z Outputs with Power Off
Superior Upgrade for LTC1485
APPLICATIONS
Low Power RS-485 Systems
DTE-DCE Interface
Packet Switching
Local Area Networks
Data Concentration
Data Multiplexers
Integrated Services Digital Network (ISDN)
EIA RS-485 Transceiver
ADM1485
FUNCTIONAL BLOCK DIAGRAM
8-Lead
ADM1485
RO
RE
DE
R
DI
D
V
CC
B
A
GND
GENERAL DESCRIPTION
The ADM1485 is a differential line transceiver suitable for high
speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced data transmission and
complies with both RS-485 and RS-422 EIA Standards. The part
contains a differential line driver and a differential line receiver.
Both the driver and the receiver may be enabled independently.
When disabled, the outputs are three-stated.
The ADM1485 operates from a single 5 V power supply. Excessive
power dissipation caused by bus contention or by output shorting
is prevented by a thermal shutdown circuit. This feature forces
the driver output into a high impedance state if, during fault conditions, a significant temperature increase is detected in the internal
driver circuitry.
Up to 32 transceivers may be connected simultaneously on a bus,
but only one driver should be enabled at any time. It is important,
therefore, that the remaining disabled drivers do not load the bus.
To ensure this, the ADM1485 driver features high output
impedance when disabled and also when powered down.
This minimizes the loading effect when the transceiver is not being
used. The high impedance driver output is maintained over the
entire common-mode voltage range from –7 V to +12 V.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM1485 is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with fast
switching bipolar technology. All inputs and outputs contain
protection against ESD; all driver outputs feature high source
and sink current capability. An epitaxial layer is used to guard
against latch-up.
The ADM1485 features extremely fast switching speeds. Minimal
driver propagation delays permit transmission at data rates up to
5 Mbps while low skew minimizes EMI interference.
The part is fully specified over the commercial and industrial
temperature range and is available in PDIP, SOIC, and small
MSOP packages.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
ADM1485–SPECIFICATIONS
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(VCC = 5 V ⴞ 5%. All specifications T
MIN
to T
, unless otherwise noted.)
MAX
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
2.0 5.0 V V
5.0 V R = ∞, Test Circuit 1
= 5 V, R = 50 Ω (RS-422), Test Circuit 1
CC
1.5 5.0 V R = 27 Ω (RS-485), Test Circuit 1
V
OD3
∆|V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Test Circuit 1
OD
Common-Mode Output Voltage V
∆|V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
OD
Output Short-Circuit Current (V
Output Short-Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
OC
= High) 35 250 mA –7 V ≤ VO ≤ +12 V
OUT
= Low) 35 250 mA –7 V ≤ VO ≤ +12 V
OUT
INL
INH
1.5 5.0 V V
3VR = 27 Ω or 50 Ω, Test Circuit 1
0.8 V
2.0 V
= –7 V to +12 V, Test Circuit 2
TST
Logic Input Current (DE, DI) ± 1.0 µA
RECEIVER
Differential Input Threshold Voltage, V
Input Voltage Hysteresis, ∆V
TH
TH
Input Resistance 12 kΩ –7 V ≤ V
Input Current (A, B) 1 mA V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
INL
INH
–0.2 +0.2 V –7 V ≤ VCM ≤ +12 V
70 mV VCM = 0 V
≤ +12 V
CM
= +12 V
–0.8 mA V
IN
= –7 V
IN
0.8 V
2.0 V
Logic Enable Input Current (RE) ± 1 µA
CMOS Output Voltage Low, V
CMOS Output Voltage High, V
OL
OH
4.0 V I
Short-Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ± 1.0 µA 0.4 V ≤ V
0.4 V I
= +4.0 mA
OUT
= –4.0 mA
OUT
= GND or V
OUT
OUT
CC
≤ 2.4 V
POWER SUPPLY CURRENT
ICC (Outputs Enabled) 1.0 2.2 mA Digital Inputs = GND or V
ICC (Outputs Disabled) 0.6 1 mA Digital Inputs = GND or V
Specifications subject to change without notice.
CC
CC
TIMING SPECIFICATIONS
(VCC = 5 V ⴞ 5%. All specifications T
MIN
to T
, unless otherwise noted.)
MAX
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output t
Driver O/P to O/P t
Driver Rise/Fall Time t
SKEW
, t
R
F
Driver Enable to Output Valid 10 25 ns R
Driver Disable Timing 10 25 ns R
Matched Enable Switching 0 2 ns R
|t
AZH–tBZL
|, |t
BZH–tAZL
|
Matched Disable Switching 0 2 ns R
|t
AHZ–tBLZ
|, |t
BHZ–tALZ
|
PLH
, t
21015 nsR
PHL
15 nsR
815 nsR
= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3
LDIFF
= 110 Ω, CL = 50 pF, Test Circuit 4
L
= 110 Ω, CL = 50 pF, Test Circuit 4
L
= 110 Ω, CL = 50 pF, Test Circuit 4*
L
= 110 Ω, CL = 50 pF, Test Circuit 4*
L
RECEIVER
Propagation Delay Input to Output t
Skew |t
PLH–tPHL
Receiver Enable t
Receiver Disable t
|5nsC
EN1
EN2
PLH
, t
PHL
81530 nsC
520 nsC
520 nsC
= 15 pF, Test Circuit 5
L
= 15 pF, Test Circuit 5
L
= 15 pF, RL = 1 kΩ, Test Circuit 6
L
= 15 pF, RL = 1 kΩ, Test Circuit 6
L
Tx Pulse Width Distortion 1 ns
Rx Pulse Width Distortion 1 ns
*Guaranteed by characterization.
Specifications subject to change without notice.
REV. E–2–
ADM1485
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Inputs
Driver Input (DI) . . . . . . . . . . . . . . . .–0.3 V to V
Control Inputs (DE, RE) . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
+ 0.3 V
CC
Receiver Inputs (A, B) . . . . . . . . . . . . . . . . . . –9 V to +14 V
Outputs
Driver Outputs (A, B) . . . . . . . . . . . . . . . . . . –9 V to +14 V
Receiver Output . . . . . . . . . . . . . . . . .–0.5 V to V
+ 0.5 V
CC
Power Dissipation 8-Lead MSOP . . . . . . . . . . . . . . . 900 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 206°C/W
JA
Power Dissipation 8-Lead PDIP . . . . . . . . . . . . . . . . 500 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 130°C/W
JA
Power Dissipation 8-Lead SOIC . . . . . . . . . . . . . . . . 450 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 170°C/W
JA
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
Table I. Transmitting
Inputs Outputs
DE DI B A
11 0 1
10 1 0
0XZ Z
Table II. Receiving
Inputs Outputs
RE A-B RO
0 ≥ +0.2 V 1
0 ≤ –0.2 V 0
0 Inputs Open 1
1X Z
Model Range Option Branding
ADM1485JN 0°C to 70°C N-8
ADM1485JR 0°C to 70°CR-8
ADM1485JR-REEL 0°C to 70°CR-8
ADM1485JR-REEL7 0°C to 70°CR-8
ADM1485AN –40°C to +85°C N-8
ADM1485AR –40°C to +85°CR-8
ADM1485AR-REEL –40°C to +85°CR-8
ADM1485AR-REEL7 –40°C to +85°CR-8
ADM1485ARM –40°C to +85°C RM-8 M42
ADM1485ARM-REEL –40°C to +85°C RM-8 M42
ADM1485ARM-REEL7 –40°C to +85°C RM-8 M42
ADM1485ARZ*
ADM1485ARZ-REEL
ADM1485ARZ-REEL7
ADM1485JCHIPS DIE
*Z = lead-free part.
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
No.
1ROReceiver Output. When enabled if A > B
by 200 mV, then RO = High. If A < B by
200 mV, then RO = Low.
2 RE Receiver Output Enable. A low level
enables the receiver output, RO. A high
level places it in a high impedance state.
3DEDriver Output Enable. A high level enables
the driver differential outputs, A and B. A low
level places it in a high impedance state.
4DIDriver Input. When the driver is enabled,
a logic low on DI forces A low and B high
while a logic high on DI forces A high and
B low.
5GND Ground Connection, 0 V.
6A Noninverting Receiver Input A/Driver
Output A.
7B Inverting Receiver Input B/Driver Output B
8V
CC
Power Supply, 5 V ± 5%.
PIN CONFIGURATION
RO
RE
DE
1
ADM1485
2
TOP VIEW
3
(Not to Scale)
4
8
V
CC
7
B
6
A
5
GNDDI
ORDERING GUIDE
Temperature Package
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM1485 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. E
–3–
ADM1485
www.BDTIC.com/ADI
Test Circuits
Test Circuit 1. Driver Voltage Measurement
Test Circuit 2. Driver Voltage Measurement
Test Circuit 3. Driver Propagation Delay
V
CC
R
L
S2
DE
A
S1
C
V
L
B
OUT
R
V
OD
R
V
OC
0V OR 3V
DE IN
Test Circuit 4. Driver Enable/Disable
375⍀
A
V
V
OD3
60⍀
375⍀
V
TST
RE
B
OUT
C
L
Test Circuit 5. Receiver Propagation Delay
+1.5V
A
R
LDIFF
B
C
L1
C
L2
–1.5V
RE IN
S1
RE
R
C
V
L
OUT
V
CC
L
S2
Test Circuit 6. Receiver Enable/Disable
Switching Characteristics
3V
–V
0V
B
A
V
O
0V
O
V
O
10% POINT
1/2VO
90% POINT
1.5V
t
PLH
t
= 円
t
PLH
–
SKEW
t
R
1.5V
t
PHL
t
円
PHL
90% POINT
10% POINT
t
F
Figure 1. Driver Propagation Delay, Rise/Fall Timing
3V
DE
A, B
A, B
1.5V
t
ZL
t
ZH
2.3V
2.3V
t
t
1.5V
LZ
HZ
V
V
OL
OH
+ 0.5V
– 0.5V
0V
V
OL
V
OH
0V
Figure 2. Driver Enable/Disable Timing
A, B
RO
t
0V
PLH
1.5V
t
SKEW
= 円
t
–
t
PLH
PHL
Figure 3. Receiver Propagation Delay
RE
R
R
0V
1.5V
t
t
ZH
ZL
1.5V
O/P LOW
t
t
O/P HIGH
1.5V
Figure 4. Receiver Enable/Disable Timing
t
円
1.5V
LZ
HZ
0V
PHL
VOL + 0.5V
V
OH
1.5V
– 0.5V
V
OH
V
OL
3V
0V
V
OL
V
OH
REV. E–4–
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