Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
ALERT output allows basic P-channel FET hot swap up to 26 V
SETV input for setting overcurrent alert threshold
Programmable overcurrent filtering via TIMER pin
CLRB input pin
2
I
C fast mode-compliant interface (400 kHz maximum)
10-lead MSOP
APPLICATIONS
Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers
Digital Power Monitor
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The ADM1192 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip
12-bit analog-to-digital converter (ADC), communicated
through an I
An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.
A 12-bit ADC can measure the current seen in the sense resistor
and in the supply voltage on the VCC pin. An industry-standard
2
I
C interface allows a controller to read current and voltage
data from the ADC. Measurements can be initiated by an I
command. Alternatively, the ADC can run continuously, and
the user can read the latest conversion data whenever it is
required. Up to four unique I
depending on the way the ADR pin is connected.
A SETV pin is also included. A voltage applied to this pin is
internally compared with the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier output exceeds the SETV voltage. This
event is detected at the ALERT block. The ALERT block then
charges up the external TIMER capacitor with a fixed current.
When this timing cycle is complete, the ALERT output asserts.
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
2
C® interface.
2
C addresses can be created,
2
C
The ALERT output can be used as a flag to warn a microcontroller or field programmable gate array (FPGA) of an
overcurrent condition. ALERT outputs of multiple ADM1192
devices can be tied together and used as a combined alert.
A basic P-channel FET hot swap circuit can be implemented
with the ALERT output. The value of the TIMER capacitor
should be set so that the charging time of this capacitor is much
longer than the period during which a higher than nominal
inrush current may be flowing.
The ADM1192 is packaged in a 10-lead MSOP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Figure 2. Applications Diagram
www.analog.com
ADM1192 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pull-Up Current (Overcurrent Fault), I
Pull-Down Current, I
Pin Threshold High, V
100 µA Normal operation, V
TIMERDN
1.275 1.3 1.325 V TIMER rising
TIMERH
−46 −62 −78 µA (18.125 × V
TIMERU POC
ALERT PIN
Output Low Voltage, V
0.05 0.1 V I
ALERTOL
1 1.5 mA I
Input Current, I
ALERT
−1 +1 µA V
ADR PIN
Set Address to 00, V
Set Address to 10, I
Set Address to 11, V
Input Current for 00 Decode, I
Input Current for 11 Decode, I
0
ADR LOWV
ADR LOWZ
−0.3
ADRHIGHZ
2
ADRHIGHV
−40 −25
ADRLO W
ADRHIGH
I2C TIMING
Low Level Input Voltage, V
High Level Input Voltage, V
Low Level Output Voltage on SDA, V
Output Fall Time on SDA from V
IL
IH
OL
to V
IHMIN
ILMAX
Maximum Width of Spikes Suppressed by
Input Filtering on SDA Pin and SCL Pin
0.3 V
0.7 V
BUS
0.4 V IOL = 3 mA
20 + 0.1 C
50 250 ns
Typ
Max
Unit Test Conditions/Comments
0.8
+0.3
5.5
3
6 µA V
µA V
V V
BUS
V V
250 ns C
BUS
) > V
, V
SENSE
= −100 µA
ALERT
= −2 mA
ALERT
= VCC; ALERT asserted
ALERT
SETV
TIMER
TIMER
= 1 V
= 1 V
Low state
specified resistance for 01 decode
Open state, maximum load allowed on
ADR pin for 10 decode
High state
= 0 V to 0.8 V
ADR
= 2.0 V to 5.5 V
ADR
= 3.0 V to 5.5 V
BUS
= 3.0 V to 5.5 V
BUS
= bus capacitance from SDA to GND
BUS
Driving a Logic Low Output
Input Capacitance on SDA/SCL
SCL Clock Frequency, f
SCL
Low Period of the SCL Clock
High Period of the SCL Clock
SU;STA
SDA Output Data Hold Time, t
Setup Time for a Stop Condition, t
HD ;DAT
SU;STO
Bus Free Time Between a Stop and a Start
Condition, t
BUF
Capacitive Load for Each Bus Line
1
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC
error, and error in ADC full-scale code conversion factor.
2
This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see the
Specifications for the Current Sense Absolute Accuracy parameter).
3
These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the
Specifications for the Voltage Sense Accuracy parameter).
4
Time between the receipt of the command byte and the actual ADC result being placed in the register.
5 pF 400 kHz
600 ns
1300 ns
100 900 ns
600 ns
1300 ns
400 pF
Rev. C | Page 4 of 20
Data Sheet ADM1192
ADR Pin
−0.3 V to +6 V
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC Pin 30 V
SENSE Pin 30 V
TIMER Pin −0.3 V to +6 V
CLRB Pin −0.3 V to +6 V
SETV Pin 6 V
ALERT Pin 30 V
SDA Pin, SCL Pin −0.3 V to +6 V
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
10-Lead MSOP 137.5 °C/W
ESD CAUTION
Rev. C | Page 5 of 20
ADM1192 Data Sheet
VCC
1
SENSE
2
SETV
3
GND
4
TIMER
5
ALERT
10
CLRB
9
ADR
8
SDA
7
SCL
6
ADM1192
TOP VIEW
(Not to Scale)
05754-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)
circuit resets the ADM1192 when a low supply voltage is detected.
2 SENSE Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
3 SETV Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert. Typical
response time is 1 µs to 2 µs.
4 GND Chip Ground Pin.
5 TIMER Timer Input Pin. An external capacitor, C
, sets the timing period for masking overcurrent conditions. This
TIMER
timing period should be sufficient to allow the inrush current to completely charge up the load without
tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
6 SCL I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
7 SDA I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
8 ADR I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C
addresses.
9 CLRB Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low.
10 ALERT Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition
is present. The level at which an overcurrent condition is detected depends on either the voltage on the SETV
pin or the value in the ALERT_TH register. The ALERT_EN register determines which is used in the comparison.
This pin has a latching function and must be cleared manually using the ALERT_EN register.
Rev. C | Page 6 of 20
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