ANALOG DEVICES ADM1192 Service Manual

with Clear Pin and ALERT Output

ADM1192

Rev. C

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Fax: [phone] ©2006–2012 Analog Devices, Inc. All rights reserved.

V

I

0

1

ADM1192

SENSE

SETV

VCC

MUX

I

2

C

ALERT

CLRB

CURRENT

SENSE

AMPLIFIER

A

SDA

SCL

ADR

ALERT

GND TIMER

05754-001

COMPARATOR

12-BIT

ADC

R

SENSE

P = VI

CONTROLLER

ADM1192

SENSEVCC

SDA
SCL

SDA
SCL

GND

ALERT

CLRB

CLRB

ADR

TIMER

3.15V TO 26V

SETV

INTERRUPT

05754-002

Data Sheet

FEATURES

Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
ALERT output allows basic P-channel FET hot swap up to 26 V
SETV input for setting overcurrent alert threshold
Programmable overcurrent filtering via TIMER pin
CLRB input pin

2

I

C fast mode-compliant interface (400 kHz maximum)

10-lead MSOP

APPLICATIONS

Power monitoring/power budgeting
Central office equipment
Telecommunications and data communications equipment
PCs/servers

Digital Power Monitor

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADM1192 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip
12-bit analog-to-digital converter (ADC), communicated
through an I

An internal current sense amplifier measures voltage across the
sense resistor in the power path via the VCC pin and the SENSE pin.

A 12-bit ADC can measure the current seen in the sense resistor
and in the supply voltage on the VCC pin. An industry-standard

2

I

C interface allows a controller to read current and voltage
data from the ADC. Measurements can be initiated by an I
command. Alternatively, the ADC can run continuously, and
the user can read the latest conversion data whenever it is
required. Up to four unique I
depending on the way the ADR pin is connected.

A SETV pin is also included. A voltage applied to this pin is
internally compared with the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier output exceeds the SETV voltage. This
event is detected at the ALERT block. The ALERT block then
charges up the external TIMER capacitor with a fixed current.
When this timing cycle is complete, the ALERT output asserts.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

2

C® interface.

2

C addresses can be created,

2

C

The ALERT output can be used as a flag to warn a micro­controller or field programmable gate array (FPGA) of an
overcurrent condition. ALERT outputs of multiple ADM1192
devices can be tied together and used as a combined alert.

A basic P-channel FET hot swap circuit can be implemented
with the ALERT output. The value of the TIMER capacitor
should be set so that the charging time of this capacitor is much
longer than the period during which a higher than nominal
inrush current may be flowing.

The ADM1192 is packaged in a 10-lead MSOP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

Figure 2. Applications Diagram

www.analog.com

ADM1192 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Voltage and Current Readback ..................................................... 10

Serial Bus Interface ..................................................................... 10

REVISION HISTORY

6/12—Rev. B to Rev. C

Changes to Low Level Input Voltage, V
Conditions/Comments Column, Table 1 and High Level Input
Voltage, V

Parameter, Test Conditions/Comments Column,

IH

Table 1 ................................................................................................ 3

Changes to SETV Pin Parameter, Rating Column, Table 2 ........ 5

Changes to Pin 3, Description Column, Table 4 and Pin 10

Description Column, Table 4 .......................................................... 6

Changes to Bit 2, Function Column, Table 9 .............................. 13

Changes to Overcurrent Flag Section .......................................... 16

Changes to Kelvin Sense Resistor Connection Section ............. 17

Deleted Figure 30; Renumbered Sequentially............................. 17

Updated Outline Dimensions ....................................................... 18

2/08—Rev. A to Rev. B

Changes to Figure 2 .......................................................................... 1

Changed V

to VCC Throughout ................................................. 3

VCC

Added ADC Conversion Time Parameter .................................... 3

Changes to Input Current for 00 Decode, I
Changes to Input Current for 11 Decode, I

Added Endnote 2 .............................................................................. 4

Changes to Figure 6 .......................................................................... 7

Parameter, Test

IL

, Parameter ... 4

ADRL OW

, Parameter ... 4

ADRHIGH

Identifying the ADM1192 on the I2C Bus ............................... 10

General I2C Timing .................................................................... 10

Write and Read Operations ........................................................... 12

Quick Command ........................................................................ 12

Write Command Byte ................................................................ 12

Write Extended Command Byte .............................................. 13

Read Voltage and/or Current Data Bytes ................................ 14

Applications Information .............................................................. 16

ALERT Output............................................................................ 16

SETV Pin ..................................................................................... 16

Kelvin Sense Resistor Connection ........................................... 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

Changes to Figure 17 ......................................................................... 9

Changes to General I

2

C Timing Section, Step 3 ......................... 10

Changes t o Table 5 .......................................................................... 10

Changes to Quick Command Section ......................................... 12

Changes to Figure 21 ...................................................................... 12

Changes to Table 7 .......................................................................... 12

Changes to Write Extended Command Byte Section ................ 13

Changes to Figure 23 ...................................................................... 13

Changes to Table 9 and Table 11 .................................................. 13

Changes to Converting ADC Codes to Voltage and

Current Readings Section .............................................................. 14

Changes to Figure 27 ...................................................................... 16

4/07—Rev. 0 to Rev. A

Changes to Table 5 .......................................................................... 10

Changes to Figure 18 and Figure 19 ............................................ 11

Changes to Figure 23 ...................................................................... 13

Changes to Figure 25 and Figure 26 ............................................ 14

Added Applications Information Heading ................................. 16

9/06—Revision 0: Initial Ve r si o n

Rev. C | Page 2 of 20

Data Sheet ADM1192

V

2 mA

%

−5.7 +5.7 % V

= 12.5 mV

−3.85

+3.85

%

V

= 25 mV

−6.7 +6.7 % V

= 12.5 mV

%

VCC for ADC Full Scale3

µA

Input Current, I

−1 +1

µA

V

= 0.9 V to 1.9 V

SPECIFICATIONS

VCC = 3.15 V to 26 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.

Table 1.

Parameter Min

VCC PIN

Operating Voltage Range, VCC 3.15
Supply Current, ICC 1.7
Undervoltage Lockout, V
Undervoltage Lockout Hysteresis, V

2.8

UVLO

80

UVLOHYST

MONITORING ACCURACY1

Current Sense Absolute Accuracy

0°C to +70°C −1.45

−1.8

−2.8

0°C to +85°C −1.5

−1.8

−2.95

−6.1

−40°C to +85°C −1.95

−2.45

V

for ADC Full Scale2 105.84

SENSE

Voltage Sense Accuracy

0°C to +70°C −0.85

−0.9 +0.9 % VCC = 10.8 V to 16.5 V (high range)
0°C to +85°C −0.85

Typ

Max

26

V
mV

+1.45 %

+1.8

+2.8 % V

+1.5 %

+1.8 %

+2.95 %

+6.1 %

+1.95 %

+2.45 % V

mV

+0.85

+0.85 %

Unit Test Conditions/Comments

VCC rising

V

= 75 mV

SENSE

V

= 50 mV

SENSE

= 25 mV

SENSE

SENSE

V

= 75 mV

SENSE

V

= 50 mV

SENSE

V

= 25 mV

SENSE

V

= 12.5 mV

SENSE

V

= 75 mV

SENSE

= 50 mV

SENSE

SENSE

SENSE

VCC = 3.0 V to 5.5 V (low range)

VCC = 3.0 V to 5.5 V (low range)

−0.9 +0.9 %

−40°C to +85°C −0.9

+0.9 %

−1.15 +1.15 %

Low Range (VRANGE = 1) 6.65
High Range (VRANGE = 0) 26.52

V
V

CLRB PIN

Logic Low Threshold, V
Input Current for Logic Low Input, I
Logic High Threshold, V
Input Current for Logic High Input, I

0.8 V

CLRBL

−40 −22 µA V

CLRBL

1.6 mV

CLRBH

3 6 µA V

CLRBH

ADC CONVERSION TIME4 150 µs

SENSE PIN

Input Current, I

−1

SENSE

+1
SETV PIN
Overcurrent Trip Threshold 98 100 102 mV V

49.5 50 50.5 mV V
Overcurrent Trip Gain, V

SETVLEAK

Glitch Filter, t

SETVGLITCH

SETV

/(VCC − V

) 18 V

SENSE

3 µs

Rev. C | Page 3 of 20

VCC = 10.8 V to 16.5 V (high range)

VCC = 3.0 V to 5.5 V (low range)

VCC = 10.8 V to 16.5 V (high range)

= 0 V to 0.8 V

CLRB

= 1.6 V to 5.5 V

CLRB

V

= VCC

SENSE

= 1.8 V

SETV

= 0.9 V

SETV

= 0.9 V to 1.9 V

SETV

SETV

ADM1192 Data Sheet

V

Set Address to 01, R

80

120

160

kΩ

Resistor to ground state, load pin with

µA

V

Input Current, II, on SDA/SCL When Not

−10 +10

µA

Setup Time for Repeated Start Condition, t

600

ns

Parameter Min

TIMER PIN

Pull-Up Current (Overcurrent Fault), I
Pull-Down Current, I
Pin Threshold High, V

100 µA Normal operation, V

TIMERDN

1.275 1.3 1.325 V TIMER rising

TIMERH

−46 −62 −78 µA (18.125 × V

TIMERU POC

ALERT PIN

Output Low Voltage, V

0.05 0.1 V I

ALERTOL

1 1.5 mA I
Input Current, I

ALERT

−1 +1 µA V

ADR PIN

Set Address to 00, V

Set Address to 10, I

Set Address to 11, V
Input Current for 00 Decode, I

Input Current for 11 Decode, I

0

ADR LOWV

ADR LOWZ

−0.3

ADRHIGHZ

2

ADRHIGHV

−40 −25

ADRLO W

ADRHIGH

I2C TIMING

Low Level Input Voltage, V
High Level Input Voltage, V
Low Level Output Voltage on SDA, V
Output Fall Time on SDA from V

IL

IH

OL

to V

IHMIN

ILMAX

Maximum Width of Spikes Suppressed by

Input Filtering on SDA Pin and SCL Pin

0.3 V

0.7 V

BUS

0.4 V IOL = 3 mA
20 + 0.1 C
50 250 ns

Typ

Max

Unit Test Conditions/Comments

0.8

+0.3

5.5

3

6 µA V

µA V

V V

BUS

V V

250 ns C

BUS

) > V

, V

SENSE

= −100 µA

ALERT

= −2 mA

ALERT

= VCC; ALERT asserted

ALERT

SETV

TIMER

TIMER

= 1 V

= 1 V

Low state

specified resistance for 01 decode
Open state, maximum load allowed on

ADR pin for 10 decode
High state

= 0 V to 0.8 V

ADR

= 2.0 V to 5.5 V

ADR

= 3.0 V to 5.5 V

BUS

= 3.0 V to 5.5 V

BUS

= bus capacitance from SDA to GND

BUS

Driving a Logic Low Output
Input Capacitance on SDA/SCL
SCL Clock Frequency, f

SCL

Low Period of the SCL Clock
High Period of the SCL Clock

SU;STA

SDA Output Data Hold Time, t
Setup Time for a Stop Condition, t

HD ;DAT

SU;STO

Bus Free Time Between a Stop and a Start

Condition, t

BUF

Capacitive Load for Each Bus Line

1

Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference error, ADC

error, and error in ADC full-scale code conversion factor.

2

This is an absolute value to be used when converting ADC codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see the

Specifications for the Current Sense Absolute Accuracy parameter).

3

These are absolute values to be used when converting ADC codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see the

Specifications for the Voltage Sense Accuracy parameter).

4

Time between the receipt of the command byte and the actual ADC result being placed in the register.

5 pF
400 kHz
600 ns
1300 ns

100 900 ns
600 ns
1300 ns

400 pF

Rev. C | Page 4 of 20

Data Sheet ADM1192

ADR Pin

−0.3 V to +6 V

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC Pin 30 V
SENSE Pin 30 V
TIMER Pin −0.3 V to +6 V
CLRB Pin −0.3 V to +6 V
SETV Pin 6 V
ALERT Pin 30 V
SDA Pin, SCL Pin −0.3 V to +6 V

Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

10-Lead MSOP 137.5 °C/W

ESD CAUTION

Rev. C | Page 5 of 20

ADM1192 Data Sheet

VCC

1

SENSE

2

SETV

3

GND

4

TIMER

5

ALERT

10

CLRB

9

ADR

8

SDA

7

SCL

6

ADM1192

TOP VIEW

(Not to Scale)

05754-003

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCC Positive Supply Input Pin. The operating supply voltage range is 3.15 V to 26 V. An undervoltage lockout (UVLO)

circuit resets the ADM1192 when a low supply voltage is detected.

2 SENSE Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across

a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.

3 SETV Input Pin. The voltage driven onto this pin is compared with the output of the internal current sense amplifier.

The lower the voltage on the SETV, the lower the current level that causes the ALERT output to assert. Typical

response time is 1 µs to 2 µs.
4 GND Chip Ground Pin.
5 TIMER Timer Input Pin. An external capacitor, C

, sets the timing period for masking overcurrent conditions. This

TIMER

timing period should be sufficient to allow the inrush current to completely charge up the load without

tripping an overcurrent fault. This makes the device robust against false triggering due to current transients.
6 SCL I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
7 SDA I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
8 ADR I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C

addresses.
9 CLRB Clear Pin. A latched overcurrent condition can be cleared by pulling this pin low.
10 ALERT Alert Output Pin. Active high, open-drain configuration. This pin asserts high when an overcurrent condition

is present. The level at which an overcurrent condition is detected depends on either the voltage on the SETV

pin or the value in the ALERT_TH register. The ALERT_EN register determines which is used in the comparison.

This pin has a latching function and must be cleared manually using the ALERT_EN register.

Rev. C | Page 6 of 20

Data Sheet ADM1192

05754-021

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0 4 8 12 16 20 24 28

I

CC

(mA)

VCC (V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–40 806040200–20

I

CC

(mA)

TEMPERATURE (°C)

05754-022

05754-026

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2
0

–35 –30 –25 –20 –15 –10 –5 0 5 10

V

ADR

I

ADR

(µA)

00 DECODE 01 DECODE 10 DECODE 11 DECODE

0

1000

900

800

700

600

500

400

300

200

100

HITS PER CODE (1000 READS)

CODE

05754-060

2047 2048 2049 20502046

0

1000

900

800

700

600

500

400

300

200

100

HITS PER CODE (1000 READS)

CODE

05754-061

780 781 782 783779

0

1000

900

800

700

600

500

400

300

200

100

HITS PER CODE (1000 READS)

CODE

05754-062

3079 3080 3081 30823078

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Supply Current vs. Supply Voltage

Figure 5. Supply Current vs. Temperature

Figure 7. ADC Noise with Current Channel, Midcode Input, and 1000 Reads

Figure 8. ADC Noise with 14:1 Voltage Channel, 5 V Input, and 1000 Reads

Figure 6. Address Pin Voltage vs. Address Pin Current

for Four Addressing Options on Each Address Pin

Figure 9. ADC Noise with 7:1 Voltage Channel, 5 V Input, and 1000 Reads

Rev. C | Page 7 of 20

ADM1192 Data Sheet

4

3

2

1

0

–1

–2

–3

–4

0 40002500 3000 3500200015001000500

INL (LSB)

CODE

05754-023

4

3

2

1

0

–1

–2

–3

–4

0 40002500 3000 3500200015001000500

DNL (LSB)

CODE

05754-024

0

100

80

90

70
60
50
40
30
20
10

0 2.01.81.61.41.21.00.80.60.40.2

V

LIM

(mV)

V

SETV

(V)

05754-046

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

–40 806040200–20

ALERT OUTPUT LOW (V)

TEMPERATURE (°C)

05754-047

05754-048

0

1.0

0.8

0.6

0.4

0.2

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28

ALERT OUTPUT LOW (V)

V

CC

(V)

0

2.0

1.6

1.2

0.8

0.4

1.8

1.4

1.0

0.6

0.2

0 3.02.82.62.42.22.01.81.61.41.21.00.80.60.40.2

ALERT OUTPUT LOW (V)

I

LOAD

(mA)

05754-049

Figure 10. INL for ADC

Figure 11. DNL for ADC

Figure 13. ALERT Output Low Voltage vs. Temperature at 1 mA

Figure 14. ALERT Output Low Voltage vs. Supply Voltage at 1 mA

Figure 12. Overcurrent Limit Threshold vs. SETV Pin Voltage

Figure 15. ALERT Output Low Voltage vs. Load Current

Rev. C | Page 8 of 20

Data Sheet ADM1192

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3 2523211917151311975

TIMER THRESHOLD (V)

V

CC

(V)

HIGH

05754-038

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–40 80

HIGH

6040200–20

TIMER THRESHOLD (V)

TEMPERATURE (°C)

05754-039

Figure 16. Timer Threshold vs. Supply Voltage

Figure 17. Timer Threshold vs. Temperature

Rev. C | Page 9 of 20

ADM1192 Data Sheet

High

11

0101111X

0x5E

VOLTAGE AND CURRENT READBACK

The ADM1192 contains the components to allow voltage and
current readback over an I

2

C bus. The voltage output of the
current sense amplifier and the voltage on the VCC pin are fed
into a 12-bit ADC via a multiplexer. The device can be instructed
to convert voltage and/or current at any time during operation

2

via an I

C command. When all conversions are complete, the
voltage and/or current values can be read back with 12-bit
accuracy in two or three bytes.

SERIAL BUS INTERFACE

Control of the ADM1192 is carried out via the serial system
management bus (I
fast mode (400 kHz maximum). The ADM1192 is connected to
this bus as a slave device, under the control of a master device.

2

C). This interface is compatible with the I2C

IDENTIFYING THE ADM1192 ON THE I2C BUS

The ADM1192 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The five MSBs of the address are set to 01011; the two LSBs are
determined by the state of the ADR pin. There are four config­urations available on the ADR pin that correspond to four I

2

C
addresses for the two LSBs (see Tab l e 5). This scheme allows four

ADM1192 devices to operate on a single I

2

C bus.

GENERAL I2C TIMING

Figure 18 and Figure 19 show timing diagrams for general write
and read operations using the I
conditions for different types of read and write operations, which
are discussed in the Write and Read Operations section. The
general I

2

C protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream is to follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7-bit
slave address (MSB first) plus an R/
direction of the data transfer, that is, whether data is written to
or read from the slave device (0 = write, 1 = read).

Table 5. Setting I

Base Address ADR Pin State ADR Pin Logic State Address in Binary1 Address in Hex

01011 Ground 00 0101100X 0x58
Resistor to ground 01 0101101X 0x5A
Floating 10 0101110X 0x5C

2

C Addresses via the ADR Pin

2

C. The I2C specification defines

W

bit that determines the

The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus now remain
idle while the selected device waits for data to be read from
it or written to it. If the R/

the slave device. If the R/

W

bit is 0, the master writes to

W

bit is 1, the master reads from

the slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period because a low-to-high transition
when the clock is high can be interpreted as a stop signal.

If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such as
telling the slave device to expect a block write, or it can be
a register address that tells the slave where subsequent data
is to be written.

Because data can flow in only one direction, as defined by

W

the R/

bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it may be necessary to first execute a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.

3. When all data bytes are read or written, stop conditions are

established. In write mode, the master pulls the data line
high during the 10

th

clock pulse to assert a stop condition.
In read mode, the master device releases the SDA line
during the SCL low period before the ninth clock pulse,
but the slave device does not pull it low. This is known as a
no acknowledge. The master then takes the data line low
during the SCL low period before the 10
then high during the 10

th

clock pulse to assert a stop

th

clock pulse, and

condition.

1

X = don’t care.

Rev. C | Page 10 of 20

Data Sheet ADM1192

SCL

SDA

START BY MASTER

1

9

1

9

ADRA ADRB

R/W

1

D7

D6

D5

D4

D3

D2 D1

D0

11

0

0

ACKNOWLEDGE BY

SLAVE

ACKNOWLEDGE BY

SLAVE

ACKNOWLEDGE BY

SLAVE

ACKNOWLEDGE BY

SLAVE

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND CODE

SCL

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1

9

1

9

STOP
BY
MASTER

SDA

(CONTINUED)

FRAME 3

DATA BYTE

FRAME N

DATA BYTE

05754-004

SCL

SDA

START BY MASTER

1

9

1

9

ADRA ADRB

R/W

1

D7

D6

D5

D4

D3

D2 D1

D0

11

0

0

ACKNOWLEDGE BY

SLAVE

ACKNOWLEDGE BY

MASTER

NO ACKNOWL E DGE

ACKNOWLEDGE BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 2

DATA BYTE

SCL

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

1

9

1

9

STOP
BY
MASTER

SDA

(CONTINUED)

FRAME 3

DATA BYTE

FRAME N

DATA BYTE

05754-005

SCLSCL

SDA

P

S

t

HD;STA

t

HD;DAT

t

HIGH

t

SU;DAT

t

SU;STA

t

HD;STA

t

F

t

R

t

LOW

t

BUF

t

SU;STO

P

S

05754-006

Figure 18. General I

2

C Write Timing Diagram

Figure 19. General I

2

C Read Timing Diagram

Figure 20. Serial Bus Timing Diagram

Rev. C | Page 11 of 20

ADM1192 Data Sheet

W

Write

05754-007

S

SLAVE

ADDRESS

W A

1 2 3

P

4

S

SLAVE

ADDRESS

W A

COMMAND

BYTE

A P

1 2 3 4 5 6

05754-008

LSB, set to convert voltage continuously. If readback is attempted before the first conversion is complete,

WRITE AND READ OPERATIONS

The I2C specification defines several protocols for different
types of read and write operations. The operations used in the

ADM1192 are discussed in this section. Table 6 shows the

abbreviations used in the command diagrams (see Figure 21
to Figure 26).

Table 6. I

2

C Abbreviations

Abbreviation Condition

S Start
P Stop
R Read

A Acknowledge
N No acknowledge

QUICK COMMAND

The quick command operation allows the master to check if the
slave is present on the bus, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master asserts a stop condition on SDA to end the

transaction.

WRITE COMMAND BYTE

In the write command byte operation, the master device sends
a command byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the command byte. The command byte

is identified by an MSB = 0. An MSB = 1 indicates an
extended register write (see the Write Extended Command
Byte section).

5. The slave asserts an acknowledge on SDA.

6. The master asserts a stop condition on SDA to end the

transaction.

Figure 22. Write Command Byte

The seven LSBs of the command byte are used to configure and
control the ADM1192. Tab l e 7 provides details of the function
of each bit.

Figure 21. Quick Command

Table 7. Command Byte Operations

Bit Default Name Function

C0 0 V_CONT

the ADM1192 asserts an acknowledge and returns all 0s in the returned data.

C1 0 V_ONCE Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC

conversion is complete.

C2 0 I_CONT Set to convert current continuously. If readback is attempted before the first conversion is complete, the

ADM1192 asserts an acknowledge and returns all 0s in the returned data.

C3 0 I_ONCE Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC

conversion is complete.

C4 0 VRANGE Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1

voltage divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the

VCC pin for an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
C5 0 Not applicable Unused.
C6 0 STATUS_RD Status Read. When this bit is set, the data byte read back from the ADM1192 is the status byte. This

contains the status of the device alerts. See Table 15 for full details of the status byte.

Rev. C | Page 12 of 20

Data Sheet ADM1192

S

SLAVE

ADDRESS

W A

REGISTER
ADDRESS

A P

EXTENDED

COMMAND

BYTE

A

1 2 3 4 5 6 7 8

05754-009

3 0 EN_OFF_ALERT

Enables an alert if the hot swap operation is turned off by an operation that writes the SWOFF bit high.

0

WRITE EXTENDED COMMAND BYTE

In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends the register address byte. The MSB of this

byte is set to 1 to indicate an extended register write. The two
LSBs indicate which of the three extended registers are to be
written to (see Tabl e 8). All other bits should be set to 0.

5. The slave asserts an acknowledge on SDA.

6. The master sends the extended command byte (refer to

Table 9, Table 10, and Table 11).

Table 9. ALERT_EN Register Operations

Bit Default Name Function

0 0 EN_ADC_OC1 LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
1 0 EN_ADC_OC4 Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the

ALERT_TH register.

2 1 EN_OC_ALERT Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold, and

the TIMER pin charges to 1.3 V, the OC_ALERT register captures and latches this condition.

7. The slave asserts an acknowledge on SDA.

8. The master asserts a stop condition on SDA to end the

transaction.

Figure 23. Write Extended Byte

Table 9, Table 10, and Table 11 provide the details of each
extended register.

Table 8. Extended Register Addresses

A6 A5 A4 A3 A2 A1 A0 Extended Register

0 0 0 0 0 0 1 ALERT_EN
0 0 0 0 0 1 0 ALERT_TH
0 0 0 0 0 1 1 CONTROL

This allows a software override of the ALERT output and turns on a P-channel FET controlled by ALERT.

4 0 CLEAR Clears the OC_ALERT and ADC_ALERT status bits in the status register. The value of these bits can

immediately change if the source of the alert is not cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits are cleared.

Table 10. ALERT_TH Register Operations

Bit Default Function

[7:0] FF The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit

value corresponds to the top eight bits of the current channel data.

Table 11. CONTROL Register Operations

Bit Default Name Function

0

SWOFF LSB, forces the ALERT pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Tab le 9).

Rev. C | Page 13 of 20

ADM1192 Data Sheet

3

LSBs

V3

V2

V1

V0

I3

I2

I1

I0

1

Voltage MSBs

V11

V10

V9

V8

V7

V6

V5

V4

S

SLAVE

ADDRESS

R A

DATA 1 DATA 2

N P

DATA 3AA

1 2 3 4 5 6 7 8 9 10

05754-010

S

SLAVE

ADDRESS

R A

DATA 1 N P

DATA 2A

1 2 3 4 5 6 7 8

05754-011

05754-012

S

SLAVE

ADDRESS

STATUS

BYTE

R A

A

1 2 3 4 5

READ VOLTAGE AND/OR CURRENT DATA BYTES

Depending on how the device is configured, the ADM1192 can
be set up to provide information in three ways after a conversion
(or conversions): voltage and current readback, voltage only
readback, and current only read back. See the Write Command
Byte section for more details.

Voltage and Current Readback

The ADM1192 digitizes both voltage and current. Three bytes
are read back in the format shown in Ta ble 12.

Table 12. Voltage and Current Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Voltage

MSBs

2 Current

MSBs

Voltage Readback

The ADM1192 digitizes voltage only. Two bytes are read back in
the format shown in Tab l e 13.

Table 13. Voltage Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

2 Voltage LSBs V3 V2 V1 V0 0 0 0 0

Current Readback

The ADM1192 digitizes current only. Two bytes are read back
in the format shown in Table 14.

Table 14. Current Only Readback Format

Byte Contents B7 B6 B5 B4 B3 B2 B1 B0

1 Current MSBs I11 I10 I9 I8 I7 I6 I5 I4
2 Current LSBs I3 I2 I1 I0 0 0 0 0

The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the first data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives the second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives the third data byte.

9. The master asserts a no acknowledge on SDA.

10. The master asserts a stop condition on SDA, and the

transaction ends.

V11 V10 V9 V8 V7 V6 V5 V4

I11 I10 I9 I8 I7 I6 I5 I4

For cases where the master is reading voltage only or current
only, two data bytes are read and Step 7 and Step 8 are not required.

Figure 24. Three-Byte Read from ADM1192

Figure 25. Two-Byte Read from ADM1192

Converting ADC Codes to Voltage and Current Readings

Equation 1 and Equation 2 can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.

Voltage = (V

/4096) × Code (1)

FULLSCALE

where:

V

= 6.65 V (7:2 range) or 26.52 V (14:1 range).

FULLSCALE

Code is the ADC voltage code read from the device

(Bit V11 to Bit V0).

Current = ((I

/4096) × Code)/Sense Resistor (2)

FULLSCALE

where:
I

FULLSCALE

= 105.84 mV.
Code is the ADC current code read from the device
(Bit I11 to Bit I0).

Read Status Register

A single register of status data can also be read from the

ADM1192 as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address, followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master receives the status byte.

5. The master asserts an acknowledge on SDA.

Figure 26. Status Read from ADM1192

Table 15 shows the ADM1192 STATUS registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 (the
CLEAR bit) of the ALERT_EN register.

Rev. C | Page 14 of 20

Data Sheet ADM1192

Table 15. Status Byte Operations

Bit Name Function

0 ADC_OC An ADC-based overcurrent comparison has been detected on the last three conversions.
1 ADC_ALERT An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register.
2 OC An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the

SETV input).

3 OC_ALERT An overcurrent condition has caused the ALERT block to latch a fault, and the ALERT output has asserted. Cleared by

writing to Bit 4 of the ALERT_EN register.
4 OFF_STATUS Set to 1 by writing to the SWOFF bit of the CONTROL register.
5 OFF_ALERT An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.

Rev. C | Page 15 of 20

ADM1192 Data Sheet

R

SENSE

P = VI

CONTROLLER

ADM1192

SENSEVCC

SDA

SCL

SDA
SCL

GND

ALERT

CLRB

CLRB

ADR

TIMER

3.15V TO 26V

SETV

INTERRUPT

05754-013

R

SENSE

P-CHANNEL FE T

P = VI

CONTROLLER

ADM1192

SENSEVCC

SDA

SCL

SDA
SCL

GND

ALERT

CLRB

CLRB

ADR

TIMER

3.15V TO 26V

SETV

05754-014

ADM1192

SETV

1.3V

ALERT

CURRENT

SENSE

AMPLIFIER

A

ALERT

60µA

R

SENSE

I

LOAD

APPLIED

VOLTAGE

SENSEVCC

TIMER

COMPARATOR

05754-015

APPLICATIONS INFORMATION

ALERT OUTPUT

The ALERT output is an open-drain pin with 30 V tolerance.
There are two uses for this output.

Overcurrent Flag

The ALERT pin can be connected to the general-purpose logic
input of a controller. During normal operation, the ADM1192
drives this output low. When an overcurrent condition occurs,
the output asserts high. An external pull-up resistor should be
used. This pin is configured by default to trigger the SETV
threshold at power-up.

SETV PIN

The SETV pin allows the user to adjust the current level that
trips the ALERT output. The output of the current sense amplifier
is compared with the voltage driven onto the SETV pin. If the
current sense amplifier output is higher than the SETV voltage,
the output of the comparator asserts. By driving a different voltage
onto the SETV pin, the ADM1192 detects an overcurrent condition
at a different current level, with a gain of 18. See Figure 12 for
an illustration of this relationship.

Figure 27. Using the ALERT Output as an Interrupt

Implementing a Basic Hot Swap Circuit

A basic P-channel FET hot swap circuit can be created. The
ALERT output should be connected to the GATE pin of a P­channel FET connected in series with the power path. A pull-up
from GATE to source ensures that the P-channel FET GATE is
pulled up and the device held off as soon as power is applied.
When the ADM1192 powers up, the GATE is pulled low by the
ALERT output. A capacitor on the TIMER pin determines the
slew rate of the GATE pin at startup. Note that if a current fault
occurs during the operation, the ALERT output asserts high,
turning off the P-channel FET.

Rev. C | Page 16 of 20

Figure 28. P-Channel FET Hot Swap Implementation

Figure 29. SETV Operation

When the output of the SETV comparator asserts, this tells the
ALERT block to begin charging the external TIMER capacitor
with a 60 μA charging current. When the voltage on the TIMER
capacitor reaches 1 V, the charging cycle is complete. The ALERT
output then asserts (goes high). Different values of TIMER
capacitor generate different time delays between current faults
occurring and the ALERT output asserting. When using the
ALERT output to implement a hot swap circuit, the TIMER
capacitor should be chosen to generate a large enough startup
delay to allow the maximum inrush current to completely
charge up the load without tripping an ALERT fault.

Data Sheet ADM1192

KELVIN SENSE RESISTOR CONNECTION

When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can arise.
The pad and solder resistance can be a substantial fraction of the
rated resistance, making the total resistance larger than expected.

This error problem can be largely avoided by using a Kelvin
sense connection. This type of connection separates the high
current path through the resistor and the voltage drop across the
resistor. A four pad resistor may be used or a split pad layout can be
used with a two pad sense resistor to achieve Kelvin sensing.

Rev. C | Page 17 of 20

ADM1192 Data Sheet

COMPLIANT TO JEDEC STANDARDS MO-187-BA

091709-A

6°
0°

0.70

0.55

0.40

5

10

1

6

0.50 BSC

0.30

0.15

1.10 MAX

3.10

3.00

2.90

COPLANARITY

0.10

0.23

0.13

3.10

3.00

2.90

5.15

4.90

4.65

PIN 1

IDENTIFIER

15° MAX

0.95

0.85

0.75

0.15

0.05

OUTLINE DIMENSIONS

Figure 30. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option Branding

ADM1192-1ARMZ-R7 −40°C to +85°C 10-Lead MSOP RM-10 M5M
EVAL-ADM1192EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. C | Page 18 of 20

Data Sheet ADM1192

NOTES

Rev. C | Page 19 of 20

ADM1192 Data Sheet

©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.
D05754-0-6/12(C)

Rev. C | Page 20 of 20