Analog Devices ADG1211 2 3 pre Datasheet

1 pF Off Capacitance, 1 pC Charge Injection,

±15 V/12 V

Preliminary Technical Data

FEATURES

2 pF off capacitance
1 pC charge injection
33 V supply range
150 Ω on resistance
Fully specified at +12 V, ±15 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP packages
Typical power consumption: <0.03 µW

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems

GENERAL DESCRIPTION

The ADG1211/ADG1212/ADG1213 are monolithic CMOS
devices containing four independently selectable switches
designed on an iCMOS process. iCMOS (industrial-CMOS) is a
modular manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc­esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.

i

CMOS™ Quad SPST Switches

ADG1211/ADG1212/ADG1213

FUNCTIONAL BLOCK DIAGRAM

IN1

IN2

IN3

IN4

ADG1211

S1

IN1

D1
S2

IN2

D2
S3

D3
S4

D4

SWITCHES SHOWN FOR A LOGIC 1 INPUT

ADG1212

IN3

IN4

Figure 1.

S1

IN1

D1
S2

IN2

D2
S3

D3
S4

D4

ADG1213

IN3

IN4

iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery­powered instruments.

The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on the
other two switches. Each switch conducts equally well in both
directions when on, and has an input signal range that extends
to the supplies. In the off condition, signal levels up to the
supplies are blocked.

The ADG1213 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.

PRODUCT HIGHLIGHTS

1. 2 pF off capacitance (±15 V supply).

2. 1 pC charge injection.

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <0.03 µW.

6. 16-lead TSSOP and 4 mm × 4 mm LFCSP packages.

= 2.0 V, VIL = 0.8 V.

IH

S1

D1
S2

D2
S3

D3
S4

D4

04778-0-001

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADG1211/ADG1212/ADG1213 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Te r m in o l o g y .......................................................................................8

Single Supply ................................................................................. 3

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

REVISION HISTORY

11/04—Revision PrE: Preliminary Version

Typical Perfor m a n c e Charac t e r ist i c s ..............................................9

Tes t Ci rc ui ts ..................................................................................... 12

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. PrE | Page 2 of 16

Preliminary Technical Data ADADG1211/ADG1212/ADG1213

SPECIFICATIONS

SINGLE SUPPLY

VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance (RON) 120 160 180

Ω typ
Ω max
On Resistance Match between

Channels (∆R

)

ON

5 Ω typ V

Ω max

On Resistance Flatness (R

) 25 Ω typ VS = −5 V/0 V/+5 V; IS = −10 mA

FLAT(ON)

50 Ω max
LEAKAGE CURRENTS VDD = +10 V, VSS = −10 V

Source Off Leakage, IS (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 21
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01

±0.5

Channel On Leakage, ID, IS (On) ±0.04

±1

±1 ±5

±2 ±5

nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 21

nA max

nA typ VS = VD = 0 V or 10 V; Figure 22

nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

INH

0.005 ±2.5 µA typ VIN = V
±0.5 µA max
Digital Input Capacitance, C

IN

5 pF typ

DYNAMIC CHARACTERISTICS2

tON 50 ns typ RL = 300 Ω, CL = 35 pF
ns max V
t

15 ns typ RL = 300 Ω, CL = 35 pF

OFF

ns max V
Break-before-Make Time Delay, tD15 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 10 V; Figure 24
Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Total Harmonic Distortion + Noise 0.002 % typ RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
CS (Off) 2 pF typ
CD (Off) 2 pF typ
CD, CS (On) 4 pF typ

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 µA typ Digital Inputs = 0 V or VDD

5.0 µA max
IDD 0.001 µA typ Digital Inputs = 5 V

5.0 µA max
ISS 0.001 µA typ Digital Inputs = 0 V or VDD

5.0 µA max

VS = ±10 V, IS = −10 mA; Figure 20

= ±10 V , IS = −10 mA

S

or V

INH

INL

= ±10 V; Figure 23

S

= ±10 V; Figure 23

S

Rev. PrE | Page 3 of 16

ADG1211/ADG1212/ADG1213 Preliminary Technical Data

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

I

0.001 µA typ Digital Inputs = 0 V or VDD

GND

5.0 µA max
I

GND

5.0 µA max

1

Temperature range for Y Version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

= 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

V

DD

Table 2.

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (RON) 220 250 Ω typ VS = +10 V, IS = −10 mA; Figure 20
Ω max
On Resistance Match between

Channels (∆R

)

ON

Ω max

On -Resistance Flatness (R

FLAT(ON)

LEAKAGE CURRENTS VDD = 12 V

Source Off Leakage, IS (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/0 V; Figure 21
±0.5 ±2.5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/0 V; Figure 21
±0.5 ±2.5 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V; Figure 22
±1 ±5 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

Input Current, I

2.0 V min

INH

0.8 V max

INL

or I

INL

INH

±0.5 µA max

Digital Input Capacitance, C

IN

DYNAMIC CHARACTERISTICS2

t

ON

ns max V
t

15 ns typ RL = 300 Ω, CL = 35 pF

OFF

ns max V
Break-before-Make Time Delay, tD 15 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 8 V; Figure 24
Charge Injection 5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 267
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27

−3 dB Bandwidth 100 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
CS (Off) 2 pF typ
CD (Off) 2 pF typ
CD, CS (On) 4 pF typ

0.001 µA typ Digital Inputs = 5 V

V

DD

1 Ω typ V

= +10 V, IS = −10 mA

S

) 12 Ω typ VS = −5 V/0 V/+5 V, IS = −10 mA

0.001 µA typ VIN = V

INL

or V

INH

5 pF typ

50 ns typ RL = 300 Ω, CL = 35 pF

= 8 V; Figure 23

S

= 8 V; Figure 23

S

Rev. PrE | Page 4 of 16

Preliminary Technical Data ADADG1211/ADG1212/ADG1213

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = 13.2 V

I

DD

5.0 µA max
IDD 0.001 µA typ Digital Inputs = 5 V

5.0 µA max

1

Temperature range for Y Version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

0.001 µA typ Digital Inputs = 0 V or VDD

Rev. PrE | Page 5 of 16