Analog Devices ADG1204 prd Datasheet

2 pF Off Capacitance, 1 pC Charge Injection,

S

Preliminary Technical Data

FEATURES

2 pF off capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 12-lead LFCSP
Typical power consumption: <0.03 µW

APPLICATIONS

Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems

±15 V/12 V 4:1 iCMOS™ Multiplexer

ADG1204

FUNCTIONAL BLOCK DIAGRAM

S1

2

S3

S4

ADG1204

1 OF 4

DECODER

Figure 1.

D

ENA1A0

04779-0-001

GENERAL DESCRIPTION

The ADG1204 is a CMOS analog multiplexer, comprising four
single channels designed on an iCMOS process. iCMOS
(industrial-CMOS) is a modular manufacturing process that
combines high voltage CMOS (complementary metal-oxide
semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 30-V operation in a footprint that no other genera­tion of high voltage parts has been able to achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages, while providing
increased performance, dramatically lower power consumption,
and reduced package size.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching. iCMOS construc­tion ensures ultralow power dissipation, making the parts
ideally suited for portable and battery powered instruments.

The ADG1204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on, and has an
input signal range that extends to the supplies. In the off condi­tion, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.

PRODUCT HIGHLIGHTS

1. 2 pF off capacitance (±15 V supply).

2. 1 pC charge injection.

3. 3 V logic-compatible digital inputs:

= 2.0 V, VIL = 0.8 V

V

IH

4. No V

5. Ultralow power dissipation: <0.03 µW.

6. 14-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP package.

logic power supply required.

L

Rev. PrD

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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADG1204 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Pin Configurations and Function Descriptions ............................8

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 5

Absolute Maximum Ratings............................................................ 7

Truth Tab l e .................................................................................... 7

ESD Caution.................................................................................. 7

REVISION HISTORY

11/04—Revision PrD: Preliminary Version

Te r m in o l o g y .......................................................................................9

Typical Perfor m a n c e Charac t e r ist i c s ........................................... 10

Tes t Ci rc ui ts ..................................................................................... 13

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. PrD | Page 2 of 16

Preliminary Technical Data ADG1204

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted.

Table 1.

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range VDD to VSS V
On Resistance (RON) 120 160 180 Ω typ VS = ±10 V, IS = −10 mA; Figure 21

Ω max

On Resistance Match between

Channels (∆R

)

ON

5

Ω typ

Ω max
On Resistance Flatness (R

) 25 Ω typ VS = −5 V, 0 V, +5 V; IS = −10 mA

FLAT(ON)

50 Ω max
LEAKAGE CURRENTS VDD = +10 V, VSS = −10 V

Source Off Leakage, IS (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
±0.5 ±1 ±5 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 0 V or 10 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

NH

0.005 µA typ VIN = V
±0.5 µA max
Digital Input Capacitance, C

DYNAMIC CHARACTERISTICS

Transition Time, t

40 ns typ RL = 50 Ω, CL = 35 pF

TRANS

IN

2

5 pF typ

ns max V

tON (EN) 40 ns typ RL = 50 Ω, CL = 35 pF

90 ns max VS = ±10 V; Figure 24

t

(EN) 20 ns typ RL = 50 Ω, CL = 35 pF

OFF

40 ns max VS = ±10 V; Figure 24

Break-before-Make Time Delay, tD 15 ns typ RL = 50 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 10 V; Figure 25
Charge Injection 1 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
Total Harmonic Distortion + Noise 0.002 % typ RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 2 pF typ
CD (Off) 7 pF typ
CD, CS (On) 4 pF typ

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 µA typ Digital Inputs = 0 V or VDD

5.0 µA max
IDD 150 µA typ Digital Inputs = 5 V
300 µA max
ISS 0.001 µA typ Digital Inputs = 0 V or VDD

5.0 µA max

= ±10 V, IS = −10 mA

V

S

or V

INH

INL

= ±10 V; Figure 24

S

Rev. PrD | Page 3 of 16

ADG1204 Preliminary Technical Data

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

I

0.001 µA typ Digital Inputs = 0 V or VDD

GND

5.0 µA max
I

150 µA typ Digital Inputs = 5 V

GND

300 µA max

1

Y Version temperature range is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

= +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.

V

DD

Table 2.

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance (RON) 220 Ω typ VS = ±3.3 V, IS = −10 mA; Figure 21
Ω max
On Resistance Match between

Channels (∆R

)

ON

10 Ω typ

Ω max V

On Resistance Flatness (R

) 30 Ω typ VS = ±3.3 V, IS = −10 mA

FLAT(ON)

Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = −5.5 V

Source Off Leakage, IS (Off) ±0.01 nA typ VD = ±4.5 V, VS = ±4.5 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VD = ±4.5 V, VS = ±4.5 V; Figure 22

±0.5 ±1 ±5 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ VD = VS = ±4.5 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

INH

0.005 µA typ VIN = V

±0.5 µA max

Digital Input Capacitance, C

IN

5 pF typ

DYNAMIC CHARACTERISTICS2

t

ON

160 ns typ RL = 300 Ω, CL = 35 pF
ns max V
t

OFF

60 ns typ RL = 300 Ω, CL = 35 pF
ns max V
Break-before-Make Time Delay, tD50 ns typ RL = 300 Ω, CL = 35 pF
1 ns min VS1 = VS2 = 3 V; Figure 25
Charge Injection 20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
pC max
Off Isolation 56

Channel-to-Channel Crosstalk 60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28

−3 dB Bandwidth 20 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29
CS (Off) 15 pF typ f = 1 MHz
CD (Off) pF typ f = 1 MHz
CD, CS (On) 100 pF typ f = 1 MHz

VSS to VDD V

dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27

= ±3.3 V, IS = −10 mA

S

or V

INL

INH

= 3 V; Figure 24

S

= 3 V; Figure 24

S

Rev. PrD | Page 4 of 16

Preliminary Technical Data ADG1204

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V

I

DD

5.0 µA max
I

SS

5.0 µA max

1

Y Version temperature range is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter 25°C 85°C Y Version1Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range
On Resistance (RON) 220 Ω typ VS = 10 V, IS = −10 mA; Figure 21
Ω max
On Resistance Match between 1 Ω typ VS = 10 V, IS = −10 mA

Channels (∆RON) Ω max

On Resistance Flatness (R

LEAKAGE CURRENTS VDD = 12 V

Source Off Leakage, IS (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
±0.5 ±1 ±5 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
±0.5 ±1 ±5 nA max

Channel On Leakage, ID, IS (On) ±0.04 nA typ VS = VD = 1 V or 10 V; Figure 23
±1 ±2 ±5 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

or I

INL

±0.5 µA max

Digital Input Capacitance, C
DYNAMIC CHARACTERISTICS

Transition Time, t

TRANS

ns max VS = ±10 V; Figure 24

tON (EN) 50 ns typ RL = 50 Ω, CL = 35 pF

ns max VS = 8 V; Figure 24

t

(EN) 15 ns typ RL = 50 Ω, CL = 35 pF

OFF

ns max VS = 8 V; Figure 24

Break-before-Make Time Delay, tD 15 ns typ RL = 50 Ω, CL = 35 pF

1 ns min VS1 = VS2 = 8 V; Figure 25

Charge Injection 5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26

Off Isolation 75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27

Channel-to-Channel Crosstalk 85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28

−3 dB Bandwidth 700 MHz typ RL = 50 Ω, CL = 5 pF; Figure 29

CS (Off) 2 pF typ

CD (Off) 2 pF typ

CD, CS (On) 4 pF typ

FLAT(ON)

2.0 V min

INH

0.8 V max

INL

0.001 µA typ VIN = V

INH

IN

2

40 ns typ RL = 50 Ω, CL = 35 pF

0.001 µA typ Digital Inputs = 0 V or 5.5 V

0.001 µA typ Digital Inputs = 0 V or 5.5 V

0 V to V

V

DD

) 12 Ω typ VS = 3 V, 6 V, 9 V; IS = −10 mA

or V

INH

INL

5 pF typ

Rev. PrD | Page 5 of 16