Analog Devices ADF7901 Datasheet

High Performance ISM Band

FEATURES

Single-chip low power UHF transmitter

369.5 MHz to 395.9 MHz frequency operation using
fractional-N PLL and fully-integrated VCO

3.0 V supply voltage

Data rates up to 50 kbps supported
Low current consumption

26 mA at 12 dBm output at 384 MHz

Power-down mode (< 1 µA)
24-lead TSSOP package

GENERAL DESCRIPTION

The ADF7901 is a low power OOK/FSK UHF transmitter
designed for use in RF remote control devices. This device
is capable of frequency shift keying (FSK) modulation on eight

FUNCTIONAL BLOCK DIAGRAM

OOK/FSK Transmitter IC

ADF7901

different channels, selectable by three external control lines.
OOK modulation is performed by modulating the PA control
line.

The on-chip VCO operates at 2× the output frequency. The
division by 2 at the output of the VCO reduces the amount of
PA feedthrough. As a result, OOK modulation depths of greater
than 50 dB are easily achievable.

The FSK_ADJ and ASK_ADJ resistors can be adjusted in the
system to optimize output power for each modulation scheme.
An additional 1.5 dB of output power is provided for the lower
bank of channels to adjust for antenna performance. The CE
line allows the transmitter to be powered down completely.
In this mode, the leakage current is typically 0.1 µA.

C

REG2

DV

TXDATA

OSC1

DD

OSC2

R = 1

FSK

CE D

GND

PDF

CHARGE

PUMP

÷ FRACTIONAL N

CHANNEL SELECT

FSK1

Σ-∆

FSK2 FSK3

OOK_SEL

VCO

RSET_FSK

PA_EN

PA

REGULATOR

REGULATOR

LDO

1

LDO

2

RSET_OOK

C

VCO

V

DD

RF

OUT

RF

GND

C

REG1

C

2

REG

R

SET

01975-001

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF7901

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Circuit Description........................................................................... 9

Loop Filter..................................................................................... 9

REVISION HISTORY

3/05—Revision 0: Initial Version

Layout Guidelines ...................................................................... 10

Decoupling.............................................................................. 10

Regulator Stability.................................................................. 10

Grounding............................................................................... 10

Supply ...................................................................................... 10

Digital Lines............................................................................ 10

Outline Dimensions ....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. 0 | Page 2 of 12

ADF7901

SPECIFICATIONS

VDD =3.0 V; GND = 0 V; TA = T

Table 1.

Parameter1 Min Typ Max Unit Comments/Conditions

RF CHARACTERISTICS

Output Frequency Ranges

Channel 1 369.5 MHz
Channel 2 371.1 MHz
Channel 3 375.3 MHz
Channel 4 376.9 MHz
Channel 5 384.0 MHz
Channel 6 388.3 MHz
Channel 7 391.5 MHz
Channel 8 394.3 MHz
Channel 9 395.9 MHz

Phase Frequency Detector Frequency 9.8304 MHz

TRANSMISSION PARAMETERS

Transmit Rate

FSK 50 kbps
OOK 50 kbps

Frequency Shift Keying

FSK Separation

2

+34.8 kHz Data = 0
On/Off Keying

Modulation Depth

3

Output Power

Min/Max Range
f

≤ 384 MHz 10 12 dBm

OUT

f

> 384 MHz 7 10.5 dBm

OUT

4

Occupied 20 dB BW

OOK at 1 kbit/s ±28 ±461.9 kHz
FSK (PA Off/On) at10 Hz5 ±26 ±461.9 kHz

LOGIC INPUTS

V

, Input High Voltage 2.124 V

INH

V

, Input Low Voltage 0.2 × V

INL

I

, Input Current ±1 µA

INH/IINL

CIN, Input Capacitance 10 pF

POWER SUPPLIES

Voltage Supply

DV

DD

Transmit Current Consumption

369.5 MHz to 376.9 MHz at 12 dBm 26 mA
384 MHz at +12 dBm 26 mA

388.3 MHz to 395.9 MHz at 10.5 dBm 21 mA
384 MHz at 5 dBm 17 mA
Power-Down Mode

Low Power Sleep Mode6 0.2 1 µA

MIN

to T

, unless otherwise noted. Typical specifications, TA = 25°C.

MAX

−34.8 kHz Data = 1

83 dB Output power = 12 dBm

15 dBm

DD

3.0 V

V

Rev. 0 | Page 3 of 12

ADF7901

Parameter1 Min Typ Max Unit Comments/Conditions

PHASE-LOCKED LOOP

VCO Gain 30 MHz/V At 384 MHz

Spurious

Harmonics3

REFERENCE INPUT

Crystal Reference 9.8304 MHz
POWER AMPLIFIER

PA Output Impedance 97 Ω + 6.4 pF At 384 MHz
TIMING INFORMATION

Crystal Oscillator to PLL Lock3 2 3 ms

PA Enable to PA Ready–PLL Settle
TEMPERATURE RANGE (TA) 0 50 °C

1

Operating temperature range is as follows: 0°C to 50°C.

2

Frequency Deviation = 34 × (9.8304 MHz)/214. Error in the crystal is reflected in variation in the desired deviation.

3

Not production tested; based on characterization.

4

The output power can be varied in both ASK/FSK mode by altering the relevant external resistor.

5

Measured using spectrum analyzer, 1 MHz span, 100 kHz RBW, max hold enabled.

6

Maximum power-down current specification applies for the OSC2 pin grounded.

7

Measured > 461.9 kHz away from channel.

8

This specification refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the

correct frequency.

, 7

3

100 kHz loop BW
Integer Boundary –45 −23 dBc
Reference −70 −23 dBc

Second Harmonic VDD = 3.0 V −24 −21 dBc
Third Harmonic VDD = 3.0 V −14 −11 dBc
All Other Harmonics −18 dBc

8

100 250 µs

Rev. 0 | Page 4 of 12

ADF7901

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter

VDD to GND
RFVDD to GND −0.3 V to +4.0 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) 0°C to 50°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 125°C
TSSOP θJA Thermal Impedance 150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 235°C
Infrared (15 sec) 240°C

1

This device is a high performance RF-integrated circuit with an ESD rating

of <1 kV. It is ESD sensitive. Take proper precautions for handling and
assembly.

2

GND = RFGND = DGND = 0 V.

1

2

Value

−0.3 V to +4.0 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 12

ADF7901

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DV

C

REG1

CP

OUT

TxDATA

D

GND

NC

D

GND

OSC1
OSC2

OOK_SEL

FSK1
FSK2

DD

1
2
3
4
5

ADF7901

6

TOPVIEW

7

(Not to Scale)

8

9
10
11
12

C

24
23

R

PA_EN

22

DV

21
20

RF

19

RF

18

VCO

C

17
16

RSET_FSK

15

RSET_OOK

14

CE

13

FSK3

REG2
SET

DD

OUT
GND

VCO

IN

01975-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 DVDD

Positive Supply for the Digital Circuitry. This must be 3.0 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin.

2 C

REG1

A 2.2 µF capacitor should be added at C

to reduce regulator noise and improve stability. A reduced capacitor

REG1

will improve regulator power-on time but may cause higher spurious.

3 CP

OUT

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated

current changes the control voltage on the input to the VCO.
4 TxDATA Digital FSK data to be transmitted is inputted on this pin.
5 D

Ground for Digital Section.

GND

6 NC No Connect.
7 D
8 OSC1

Ground for Digital Section.

GND

The reference crystal should be connected between this pin and the OSC2 pin. The necessary crystal load

capacitor should be tied between this pin and ground.
9 OSC2

The reference crystal should be connected between this pin and the OSC1 pin. The necessary crystal load

capacitor should be tied between this pin and ground.

When not using an external regulator, a 1 MΩ resistor can be tied between the OSC2 pin and ground to meet the

power-down current specification of 1 µA.
10 OOK_SEL A high on this pin selects operation in OOK mode at 384 MHz when CE is high.
11 FSK1 FSK Channel Select Pin. This represents the LSB of the channel select pins.
12 FSK2 FSK Channel Select Pin.
13 FSK3 FSK Channel Select Pin.
14 CE Bringing CE low puts the ADF7901 into power-down drawing < 1 µA of current.
15 RSET_OOK

The value of this resistor sets the output power for data = 1 in OOK mode. A resistor of 3.6 kΩ provides the

maximum output power. Increasing the resistor reduces the power and the current consumption. A lower resistor

value than 3.6 kΩ can be used to increase the power to a maximum of 14 dBm. The PA does not operate

efficiently in this mode.
16 RSET_FSK

The value of this resistor sets the output power in FSK mode. A resistor of 3.6 kΩ provides maximum output

power. Increasing the resistor reduces the power and the current consumption. A resistor value lower than 3.6 kΩ

can be used to increase the power to a maximum of 14 dBm. The PA does not operate efficiently in this mode.
17 C

VCO

A 22 nF capacitor should be tied between the C

VCO

and C

pins. This line should run underneath the ADF7901.

REG2

The capacitor is necessary to ensure stable VCO operation.
18 VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).

The higher the tuning voltage the higher the output frequency. The output of the loop filter is connected here.
19 RF
20 RF

Ground for Output Stage of Transmitter.

GND

OUT

The modulated signal is available at this pin. Output power levels are from –5 dBm to +12 dBm. The output

should be impedance matched using suitable components to the desired load.

Rev. 0 | Page 6 of 12

ADF7901

Pin No. Mnemonic Function

21 DVDD

22 PA_EN

23 R
24 C

SET

REG2

Voltage Supply for VCO and PA Section. It should be supplied with 3.0 V. Decoupling capacitors to the ground
plane should be placed as close as possible to this pin.

This pin is used to enable the power amplifier. It should be modulated with the OOK data in OOK mode. In
FSK mode, it should be enabled when the PLL is locked.

External resistor to set charge pump current and some internal bias currents. Use 3.6 kΩ as default.
A 2.2 µF capacitor should be added at C

to reduce regulator noise and improve stability. A reduced capacitor

REG2

will improve regulator power-on time but may cause higher spurs.

Rev. 0 | Page 7 of 12

ADF7901

W

TYPICAL PERFORMANCE CHARACTERISTICS

16

12

8

OUTPUT POWER (dBm)

4

0

2

35 9710468

Figure 3. Output Power vs. R

RSET

FSK, Upper FSK Channels,

SET

Measured into 50 Ω

01975-004

Avg
Log
10
dB/

PAvg

S2

1

FS

S3

AA

£(f):
f<50k
Swp

Center 395.948 29MHz
#Res BW 300Hz VBW 300Hz

Atten 30dB

RBW

300.0000000Hz

1R

Figure 5. Phase Noise at Channel 9

Mkr1 10.00kHz

Noise –89.55dB/HzRef 15dBm

1

Sweep 2.118 s (601 pts)

Span 50kHz

01975-006

35

30

25

(mA)

DD

I

20

15

10

5971468

OUTPUT POWER (dBm)

Figure 4. Current Consumption vs. Output Power, Upper FSK Channels,

Measured into 50 Ω

Peak
Log
10
dB/

LgAv

0

01975-005

Center 5.50GHz
#Res BW 1MHz VBW 1MHz

X Axis
400MHz
800MHz

1.19GHz

1.59GHz

Mkr4 1.59GHz

–21.30dBRef 15dBm

Amplitude
–25.56dB
–13.89dB
–34.53dB
–21.30dB

Span 10.5GHz

Atten 30dB

Marker

Trace

4R

2

1

3

1
2

4

3
4

Type

(1)

Freq

(1)

Freq

(1)

Freq

(1)

Freq

Sweep 17.52 ms (601 pts)

Figure 6. Harmonic Levels—Up to Fourth Harmonic,

Measured at Channel 9 into 50 Ω

01975-007

Rev. 0 | Page 8 of 12

ADF7901

CIRCUIT DESCRIPTION

Table 4.

Frequency MHz FSK3 FSK2 FSK1 OOK_SEL

369.5 0 0 0 0

371.1 0 0 1 0

375.3 0 1 0 0

376.9 0 1 0 0

384.0 X X X 1

388.3 1 0 0 0

391.5 1 0 1 0

394.3 1 1 0 0

395.9 1 1 1 0

Improved spurious performance in FSK mode can be achieved
by using a narrower loop bandwidth. For a data rate of 20 kbps,
a loop bandwidth of roughly 50 kHz would be suitable. The
following components give a loop bandwidth of 51.1 kHz:

C1 = 680 pF

C2 = 15 nF

C3 = 180 pF

R1 = 510 Ω

R2 = 6.2 kΩ

LOOP FILTER

The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. The recommended loop filter design for this circuit is
297 kHz. This is based on the trade-off between attenuation of
beat note spurs and the need to minimize chirp when the PA is
turned on.

R2 = 6.2k

CHARGE
PUMP OUT

R1 = 3k

Figure 7.

Ω

VCO

Ω

C3 = 10pFC1 = 33pF C2 = 390pF

01975-008

ADIsimPLL is a free software tool offered by Analog Devices
for assistance in designing with ADI’s frequency synthesizers
and ISM band transmitters. To select the correct loop filter
components for use with the ADF7901, open a project for the
ADF7012 device. Then, enter the desired output carrier
frequency and loop bandwidth, and use the 870 µA charge
pump current setting.

ADIsimPLL can be downloaded from the Analog Devices
website,

www.analog.com.

Rev. 0 | Page 9 of 12

ADF7901

VCO

C

REG1

ADF7901

2.2µF

RSET_FSK

RSET_OOK

MATCHING RFOUT TO 50Ω

27nH

5.6pF

3.6kΩ

3.6kΩ

9.8304MHz

33pF33pF

NOTES

1. DECOUPLING CAPACITORS HAVE
BEEN OMITTED FOR CLARITY.

RF

VCO

OSC2

OSC1

GND

DV

DD

OUT

IN

5TH ORDER LOW PASS FILTER

22nH

3pF

22nH

8pF

1.5pF

3pF

MATCHING 50Ω
TO ANTENNA

ANTENNA

36nH

01975-003

C

REG2

VCO

R

SET

CP

OUT

TxDATA

FSK1
FSK2
FSK3
OOK_SEL
PA_EN

CE

2.2µF

220nF

C

3.6kΩ

IN

Figure 8. Applications Diagram for the ADF7901 in a Remote Control System

LAYOUT GUIDELINES

The layout of the board is crucial to ensuring low levels of
spurious and harmonics.

Decoupling

Decoupling capacitors (high frequency 22 pF, low frequency
100 nF) should be placed as close as possible to the supply pins
on the part. Low size 0402 and 0603 components are recom­mended for the high frequency rejection on the supply.

Regulator Stability

A minimum of 1 µF is needed on both C
stability. An additional 22 pF capacitor can be added to reject
higher frequency noise. Since many of the internal blocks run
off the regulator, it is critical to reduce its noise. Low size 0402
and 0603 components are recommended for the high frequency
rejection on the supply.

REG1

and C

to ensure

REG2

Grounding

Emphasis should be placed on the grounding once the decoup­ling capacitors have been added. The PA stage switches currents
of 15 mA in maximum power mode. This causes changes in the
ground resulting in large return currents that can radiate to
other parts of the board. The shortest and least obstructed
ground from RFGND back to the ground of the battery should
be ensured. A 4-layer board will help, as well as flooding the top
layer. The ground paths should not have any vias and should be
wide tracks.

Supply

The supply tracks can be routed through vias, since they act as
free inductors on the board and make layout easier on a 2-layer
board (see the Decoupling section). Tracks should be wide.

Digital Lines

Digital lines should contain a large resistor in series. This
impedance blocks signals of many frequencies including
harmonics and the carrier frequency. Long control lines can
act as antennae. It can be useful to add capacitance to ground.
There is some capacitance to ground provided by the lines and
at the input of the digital pins.

Rev. 0 | Page 10 of 12

ADF7901

OUTLINE DIMENSIONS

7.90

7.80

7.70

24

PIN 1

0.15

0.05

0.10 COPLANARITY

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AD

13

121

1.20

MAX

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8°
0°

0.75

0.60

0.45

Figure 9. 24-Lead Thin Shrink Small Outline Package [ TSSOP]

(RU-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF7901BRU 0°C to 50°C 24-Lead Thin Shrink Small Outline Pacakage (TSSOP) RU-24
ADF7901BRU-REEL 0°C to 50°C 24-Lead Thin Shrink Small Outline Pacakage (TSSOP) RU-24
ADF7901BRU-REEL7 0°C to 50°C 24-Lead Thin Shrink Small Outline Pacakage (TSSOP) RU-24
EVAL-ADF7901EB Evaluation Board

Rev. 0 | Page 11 of 12

ADF7901

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks
and

registered trademarks are the property of their respective owners.

D05349–0–3/05(0)

Rev. 0 | Page 12 of 12