ANALOG DEVICES ADF7241 Service Manual

Low Power IEEE 802.15.4 Zero-IF 2.4 GHz

FEATURES

Frequency range (global ISM band)

2400 MHz to 2483.5 MHz IEEE 802.15.4-2006-compatible (250 kbps) Low power consumption

19 mA (typical) in receive mode

21.5 mA (typical) in transmit mode (P

1.7 μA, 32 kHz crystal oscillator wake-up mode

High sensitivity

−95 dBm at 250 kbps

Programmable output power

−20 dBm to +4.8 dBm in 2 dB steps

Integrated voltage regulators

1.8 V to 3.6 V input voltage range

Excellent receiver selectivity and blocking resilience

Zero-IF architecture

Complies with EN300 440 Class 2, EN300 328, FCC CFR47

Part 15, ARIB STD-T66 Digital RSSI measurement Fast automatic VCO calibration Automatic RF synthesizer bandwidth optimization

= 3 dBm)

O

Transceiver IC

ADF7241

On-chip low power processor performs

Radio control Packet management

Packet management support

Insertion/detection of preamble address/SFD/FCS IEEEE 802.15.4-2006 frame filtering

IEEEE 802.15.4-2006 CSMA/CA unslotted modes Flexible 256-byte transmit/receive data buffer SPORT mode Flexible multiple RF port interface

External PA/LNA support hardware

Switched antenna diversity support Wake -up timer Very few external components

Integrated PLL loop filter, receive/transmit switch, battery

monitor, temperature sensor, 32 kHz RC and crystal

oscillators Flexible SPI control interface with block read/write access Small form factor 5 mm × 5 mm 32-lead LFCSP package

APPLICATIONS

Wireless sensor networks Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee

FUNCTIONAL BLOCK DIAGRAM

ADF7241

LNA1

LNA2

PA

LDO × 4 BIAS

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her

responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No

rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Trademarks and registered trademarks are the property of their respective owners.

FRACTIONAL-N

RF SYNTHES IZER

BATTERY MONITOR

DAC

ADC

DAC

PRE-EMPHASIS FILTER

TEMPERATURE

SENSOR

4kB

PROGRAM

ROM

2kB

PROGRAM

RAM

256-BYTE

PACKET

RAM

64-BYTE

BBRAM

256-BYTE

MCR

SPIWAKE-UP CTRL

GPIO

SPORT

IRQ

09322-001

26MHz

OSC

DSSS

DEMOD

AGC

OCL

CDR

32kHz

RC

OSC

8-BIT

PROCESSOR

RADIO

CONTROLLER

PACKET

MANAGER

32kHz

XTAL

OSC

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

ADF7241

REVISION HISTORY

1/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 72

ADF7241

GENERAL DESCRIPTION

The ADF7241 is a highly integrated, low power, and high performance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.42006 2.4 GHz PHY requirements in both packet and data streaming modes. With a minimum number of external components, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards.

The ADF7241 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSSOQPSK modulation. The transmitter path of the ADF7241 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve best phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from −20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs.

The receive path is based on a zero-IF architecture enabling very high blocking resilience and selectivity performance, which are critical performance metrics in interference dominated environments such as the 2.4 GHz band. In addition, the architecture does not suffer from any degradation of blocker rejection in the image channel, which is typically found in low IF receivers. The IC can operate with a supply voltage between 1.8 V and 3.6 V with very low power consumption in receive and transmit modes while maintaining its excellent RF performance, making it especially suitable for battery-powered systems.

The ADF7241 features a flexible dual-port RF interface that can be used with an external LNA and/or PA in addition to supporting switched antenna diversity.

The ADF7241 incorporates a very low power custom 8-bit processor that supports a number of transceiver management functions. These functions are handled by the two main modules of the processor: the radio controller and the packet manager.

The radio controller manages the state of the IC in various operating modes and configurations. The host MCU can use single byte commands to interface to the radio controller. In transmit mode, the packet manager can be configured to add preamble and SFD to the payload data stored in the on-chip packet RAM. In receive mode, the packet manager can detect and generate an interrupt to the MCU upon receiving a valid SFD, and store the received data payload in the packet RAM. A total of 256 bytes of transmit and receive packet RAM space is provided to decouple the over-the-air data rate from the host MCU processing speed. Thus, the ADF7241 packet manager eases the processing burden on the host MCU and saves the overall system power consumption.

In addition, for applications that require data streaming, a synchronous bidirectional serial port (SPORT) provides bitlevel input/output data, and has been designed to directly interface to a wide range of DSPs, such as ADSP-21xx, SHARC®, TigerSHARC®, and Blackfin®. The SPORT interface can optionally be used.

The processor also permits the download and execution of a set of firmware modules, which include IEEE 802.15.4 automatic modes, such as node address filtering, as well as unslotted CSMA/CA. Execution code for these firmware modules is available from Analog Devices, Inc.

To further optimize the system power consumption, the ADF7241 features an integrated low power 32 kHz RC wake-up oscillator, which is calibrated from the 26 MHz crystal oscillator while the transceiver is active. Alternatively, an integrated 32 kHz crystal oscillator can be used as a wake-up timer for applications requiring very accurate wake-up timing. A battery backed-up RAM (BBRAM) is available on the IC where IEEE 802.15.42006 network node addresses can be retained when the IC is in the sleep state.

The ADF7241 also features a very flexible interrupt controller, which provides MAC-level and PHY-level interrupts to the host MCU. The IC is equipped with a SPI interface, which allows burst mode data transfer for high data throughput efficiency. The IC also integrates a temperature sensor with digital readback and a battery monitor.

Rev. 0 | Page 3 of 72

ADF7241

4kB

PROGRAM

ROM

2kB

PROGRAM

RAM

256- BYTE

PACKET

RAM

64-BYTE

BBRAM

256-BYTE

MCR

SPI

EXT LNA/PA

ENABLE

GPIO

SPORT

IRQ

CS MOSI SCLK MISO

RXEN_GP6 TXEN_GP5

TRCLK_CKO_GP3 DT_GP1 DR_GP0 IRQ1_GP4 IRQ2_TRFS_GP2

RFIO1P

RFIO1N RFIO2P

RFIO2N

PABIAOP_ATB4

PAVSUP_ATB3

ADF7241

EXT PA

INTERFACE

PA

RAMP

LNA1

LNA2

PA

BATTERY MONITOR

DIV2 DIVIDER

CHARGE-

PUMP

LOOP FILTER

TEMPERATURE

SENSOR

LDO3LDO2LDO1 BIAS

LDO4

SDM

PFD

ANALOG

TEST

DAC

ADC

DAC

PRE-EMPHASIS

FILTER

26MHz

OSC

DSSS

DEMOD

AGC OCL CDR

DSSS MOD

RC

CAL

8-BIT

PROCESSOR

RADIO

CONTROLLER

PACKET

MANAGER

WAKE-UP CTRL

TIMER UNIT

32kHz

RC

OSC

32kHz

XTAL

OSC

CREGRF1, CREGRF2, CREGRF3

CREGDIG1, CREGDIG2

XOSC32KP_GP7_ATB1XOSC32KN_ATB2XOSC26NXOSC26PRBIASCREGSYNTHCREGVCO

09322-011

Figure 2. Detailed Functional Block Diagram

Rev. 0 | Page 4 of 72

ADF7241

SPECIFICATIONS

VDD_BAT = 1.8 V to 3.6 V, GND = 0 V, TA = T f

= 2450 MHz. All measurements are performed using the ADF7241 reference design, RFIO2 port, unless otherwise noted.

CHANNEL

GENERAL SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit Test Conditions

GENERAL PARAMETERS

Voltage Supply Range

VDD_BAT Input 1.8 3.6 V Frequency Range 2400 2483.5 MHz Operating Temperature Range −40 +85 °C Data Rate 250 kbps

RF FREQUENCY SYNTHESIZER SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Test Conditions

CHANNEL FREQUENCY RESOLUTION 10 kHz PHASE ERROR 3 Degrees

1.5 Degrees

VCO CALIBRATION TIME 52 μs Applies to all modes SYNTHESIZER SETTLING TIME

53 μs Receive mode 80 μs Transmit mode PHASE NOISE Receive mode

−135 dBc/Hz 10 MHz frequency offset

−145 dBc/Hz ≥50 MHz frequency offset REFERENCE AND CLOCK-RELATED

SPURIOUS

INTEGER BOUNDARY SPURS 60 dBc

CRYSTAL OSCILLATOR

Crystal Frequency 26 MHz Parallel load resonant crystal Maximum Parallel Load Capacitance 18 pF Minimum Parallel Load Capacitance 7 pF Maximum Crystal ESR 365.3 Ω

Sleep-to-Idle Wake-Up Time 300 μs 15 pF load on XOSC26N and XOSC26P

to T

MIN

70 dBc

, unless otherwise noted. Typical specifications are at VDD_BAT = 3.6 V, TA = 25°C,

MAX

Receive mode; integration bandwidth from 10 kHz to 400 kHz

Transmit mode; integration bandwidth from 10 kHz to 1800 kHz

Frequency synthesizer settled to <±5 ppm of the target frequency within this time following a VCO calibration

Receive mode; f 2480 MHz

Receive mode; measured at 400 kHz offset from f

= 2405 MHz, 2418 MHz, 2431 MHz,

CHANNEL

2444 MHz, 2457 MHz, 2470 MHz

Guarantees maximum crystal frequency error of

0.2 ppm; 33 pF on XOSC26P and XOSC26N

= 2405 MHz, 2450 MHz, and

CHANNEL

Rev. 0 | Page 5 of 72

ADF7241

TRANSMITTER SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit Test Conditions

TRANSMITTER SPECIFICATIONS

Maximum Transmit Power 3 dBm Minimum Transmit Power −25 dBm Maximum Transmit Power (High Power

Mode)

Minimum Transmit Power (High Power

Mode)

Transmit Power Variation 2 dB

Transmit Power Control Resolution 2 dB Transmit power = 3 dBm Optimum PA Matching Impedance 43.7 + 35.2j Ω For maximum transmit power = 3 dBm Harmonics and Spurious Emissions

Compliance with ETSI EN 300 440

25 MHz to 30 MHz −36 dBm Unmodulated carrier, 10 kHz RBW1 30 MHz to 1 GHz −36 dBm Unmodulated carrier, 100 kHz RBW1 47 MHz to 74 MHz, 87.5 MHz to

118 MHz, 174 MHz to 230 MHz, 470 MHz to 862 MHz

Otherwise Above 1 GHz −30 dBm Unmodulated carrier, 1 MHz RBW1

Compliance with ETSI EN 300 328

1800 MHz to 1900 MHz −47 dBm Unmodulated carrier 5150 MHz to 5300 MHz −97 dBm/Hz

Compliance with FCC CFR47, Part15

4.5 GHz to 5.15 GHz −41 dBm 1 MHz RBW1

7.25 GHz to 7.75 GHz −41 dBm 1 MHz RBW1

Transmit EVM 2 %

Transmit EVM Variation 1 %

Transmit PSD Mask −56 dBm RBW = 100 kHz; |f – f Transmit 20 dB Bandwidth 2252 MHz

1

RBW = resolution bandwidth.

4.8 dBm

Refer to Power Amplifier section for details on how to enable this mode

−22 dBm

Transmit power = 3 dBm, f

2483.5 MHz, T

= −40°C to +85°C, VDD_BAT = 1.8 V

A

= 2400 MHz to

CHANNEL

to 3.6 V

−54 dBm Unmodulated carrier, 100 kHz RBW

Measured using Rohde & Schwarz FSU vector analyzer with Zigbee™ option

= 2405 MHz to 2480 MHz, TA= −40°C to

f

CHANNEL

+85°C, VDD_BAT = 1.8 V to 3.6 V

| > 3.5 MHz

CHANNEL

1

RECEIVER SPECIFICATIONS

Table 4.

Parameter Min Typ Max Unit Test Conditions

GENERAL RECEIVER SPECIFICATIONS

RF Front-End LNA and Mixer IIP3 −13.6 dBm

−12.6 dBm

−10.5 dBm

Rev. 0 | Page 6 of 72

At maximum gain, f

= 10.1 MHz, P

f

BLOCKER2

At maximum gain, f

= 40.1 MHz,

f

BLOCKER2

= −35 dBm

P

RF,IN

At maximum gain, f

= 80.1 MHz,

f

BLOCKER2

P

= −35 dBm

RF,IN

BLOCKER1

= −35 dBm

RF,IN

BLOCKER1

= 5 MHz,

= 20 MHz,

= 40 MHz,

ADF7241

Parameter Min Typ Max Unit Test Conditions

RF Front-End LNA and Mixer IIP2 24.7 dBm

RF Front-End LNA and Mixer 1 dB

−20.5 dBm At maximum gain

At maximum gain, f f

= 5.5 MHz, P

BLOCKER2

Compression Point Receiver LO Level at RFIO2 Port −100 dBm IEEE 802.15.4 packet mode LNA Input Impedance at RFIO1x Port 50.2 − 52.2j Ω Measured in RX state LNA Input Impedance at RFIO2x Port 74.3 − 10.7j Ω Measured in RX state Receive Spurious Emissions Compliant with EN 300 440

30 MHz to 1000 MHz −57 dBm 1 GHz to 12.75 GHz −47 dBm

RECEIVE PATH IEEE 802.15.4-2006 MODE

Sensitivity (P

, IEEE 802.15.4) −95 dBm

rf,in,min

1% PER with PSDU length of 20 bytes according to the IEEE 802.15.4-2006 standard

Saturation Level −15 dBm 1% PER with PSDU length of 20 bytes

CW Blocker Rejection P

RF,IN

= P

, IEEE 802.15.4 + 3 dB

RF,IN,MIN

±5 MHz 55 dB ±10 MHz 60 dB ±20 MHz 63 dB ±30 MHz 64 dB

Modulated Blocker Rejection P

RF,IN

= P

, IEEE 802.15.4 + 3 dB

RF,IN,MIN

±5 MHz 48 dB ±10 MHz 61 dB ±15 MHz 62.5 dB ±20 MHz 65 dB

±30 MHz 65 dB Co-Channel Rejection −6 dB P Out-of Band Blocker Rejection

= P

RF,IN

RF,IN,MIN

= P

P

RF,IN

RF,IN,MIN

measured at f

+ 10 dB modulated blocker , IEEE 802.15.4 + 3 dB,

CHANNEL

−5 MHz −34.2 dBm

−10 MHz −30.7 dBm

−20 MHz −29.7 dBm

−30 MHz −25.7 dBm

−60 MHz −24.2 dBm = P

P

RF,IN

RF,IN,MIN

measured at f

, IEEE 802.15.4 + 3 dB,

CHANNEL

+5 MHz −33.4 dBm +10 MHz −29.9 dBm +20 MHz −28.2 dBm +30 MHz −23.7 dBm +60 MHz −29.9 dBm

Receiver Channel Bandwidth 2252 kHz

Two-sided bandwidth; cascaded analog and

digital channel filtering Frequency Error Tolerance −80 +80 ppm P RSSI

RF,IN

= P

RF,IN,MIN

+ 3 dB

Measured using IEEE 802.15.4-2006 packet

mode

Dynamic range 85 dB Accuracy ±3 dB Averaging Time 128 μs Minimum Sensitivity −95 dBm

Rev. 0 | Page 7 of 72

= 5 MHz,

BLOCKER1

= −50 dBm

RF,IN

= 2405 MHz

= 2480 MHz

ADF7241

AUXILIARY SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit Test Conditions

32 kHz RC OSCILLATOR

Frequency 32.768 kHz After calibration Frequency Accuracy 1 % After calibration at 25°C Frequency Drift

Temperature Coefficient 0.14 %/°C Voltage Coefficient 4 %/V

Calibration Time 1 ms

32 kHz CRYSTAL OSCILLATOR

Frequency 32.768 kHz Maximum ESR 319.8 kΩ 10 pF on XOSC32KP and XOSC32KN Start-Up Time 2000 ms

WAKE-UP TIMER

Prescaler Tick Period 0.0305 20,000 ms Wake-Up Period 61 × 10−6 1.31 × 105 sec

TEMPERATURE SENSOR

Range −40 +85 °C Resolution 4.7 °C Accuracy ±6.4 °C

BATTERY MONITOR

Trigger Voltage 1.7 3.6 V Trigger Voltage Step Size 62 mV Start-Up Time 5 μs Current Consumption 30 μA

EXTERNAL PA INTERFACE

RON, PAVSUP_ATB3 to VDD_BAT 5 Ω extpa_bias_mode = 0, 1, 2, 5, 6 R

, PAVSUP_ATB3 to GND 10 MΩ extpa_bias_mode = 3, 4, power-down

OFF

R

, PABIASOP_ATB4 to GND 10 MΩ extpa_bias_mode = 0, power-down

OFF

PABIASOP_ATB4 Source Current, Maximum 80 μA expta_bias_mode = 1, 3 PABIASOP_ATB4 Sink Current, Minimum −80 μA extpa_bias_mode = 2, 4 PABIASOP_ATB4 Current Control Resolution 6 Bits extpa_bias_mode = 1, 2, 3, 4, 5 PABIASOP_ATB4 Compliance Voltage 150 mV extpa_bias_mode = 2, 4 PABIASOP_ATB4 Compliance Voltage 3.45 V extpa_bias_mode = 1, 3 Servo Loop Bias Current 22 mA extpa_bias_mode = 5, 6 Servo Loop Bias Current Control Step 0.349 mA extpa_bias_mode = 5, 6

12.5 pF load capacitors on XOSC32KP and XOSC32KN

Average of 1000 ADC readbacks, after using linear fitting, with correction at known temperature

Rev. 0 | Page 8 of 72

ADF7241

CURRENT CONSUMPTION SPECIFICATIONS

Table 6.

Parameter Min Typ Max Unit Test Conditions

CURRENT CONSUMPTION

TX Mode Current Consumption

−20 dBm 16.5 mA IEEE 802.15.4-2006 continuous packet transmission mode

−10 dBm 17.4 mA IEEE 802.15.4-2006 continuous packet transmission mode 0 dBm 19.6 mA IEEE 802.15.4-2006 continuous packet transmission mode +3 dBm 21.5 mA IEEE 802.15.4-2006 continuous packet transmission mode

+4 dBm 25 mA IEEE 802.15.4-2006 continuous packet transmission mode Idle Mode 1.8 mA XTO26M + digital active PHY_RDY Mode 10 mA RX Mode Current Consumption 19 mA IEEE 802.15.4-2006 packet mode MEAS State 3 mA SLEEP_BBRAM 0.3 μA BBRAM contents retained SLEEP_BBRAM_RCO 1 μA

SLEEP_BBRAM_XTO 1.7 μA

TIMING AND DIGITAL SPECIFICATIONS

32 kHz RC oscillator running, some BBRAM contents retained, wake-up time enabled

32 kHz crystal oscillator running, some BBRAM contents retained, wake-up time enabled

Table 7. Logic Levels

Parameter Min Typ Max Unit Test Conditions

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH VDD_BAT − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA Output Rise/Fall 5 ns Output Load 7 pF

INH/IINL

0.7 × VDD_BAT V

INH

0.2 × VDD V

INL

±1 μA

Table 8. GPIOs

Parameter Min Typ Max Unit Test Conditions

GPIO OUTPUTS

Output Drive Level 5 mA All GPIOs in logic high state Output Drive Level 5 mA All GPIOs in logic low state

Table 9. SPI Interface Timing

Parameter Min Typ Max Unit Description

t1 15 ns t2 40 ns t3 40 ns SCLK high time

t4 40 ns SCLK low time t5 80 ns SCLK period t6 10 ns SCLK falling edge to MISO delay t7 5 ns MOSI to SCLK rising edge setup time t8 5 ns MOSI to SCLK rising edge hold time

falling edge to MISO setup time (TRX active)

CS

to SCLK setup time

CS

Rev. 0 | Page 9 of 72

ADF7241

Parameter Min Typ Max Unit Description

t9 40 ns t10 10 ns t11 270 ns t12 300 400 μs t13 20 ns SCLK rise time t14 20 ns SCLK fall time t15, t16 2 ms

SCLK to CS

high to SCLK wait time

CS

high time

CS

low to MISO high wake-up time, 26 MHz crystal with 10 pF load capacitance, TA = 25°C

CS

high time on wake-up after RC_RESET or RC_SLEEP command (see and

CS Figure 31

Table 10. IEEE 802.15.4 State Transition Timing

Parameter Min Typ Max Unit Test Conditions

Idle to PHY_RDY State 142 μs PHY_RDY to Idle State 13.5 μs PHY_RDY or TX to RX State (Different Channel) 192 μs VCO calibration performed PHY_RDY or RX to TX State (Different Channel) 192 μs VCO calibration performed PHY_RDY or TX to RX State (Same Channel) 140 μs VCO calibration skipped RX or PHY_RDY to TX State (Same Channel) 140 μs VCO calibration skipped RX Channel Change 192 μs VCO calibration performed TX Channel Change 192 μs VCO calibration performed TX to PHY_RDY State 23 μs PHY_RDY to CCA State 192 μs CCA to PHY_RDY State 14.5 μs RX to Idle State 5.5 μs TX to Idle State 30.5 μs Idle to MEAS State 19 μs MEAS to Idle State 6 μs CCA to Idle State 14.5 μs RX to CCA State 18 μs CCA to RX State 205 μs

hold time

Figure 5

) 26 MHz crystal with 10 pF load

Table 11. Timing IEEE 802.15.4-2006 SPORT Mode

Parameter Min Typ Max Unit Test Conditions/Comments

t21 18 μs SFD detect to TRCLK_CKO_GP3 (data bit clock) active delay t22 2 μs TRCLK_CKO_GP3 bit period t23 0.51 μs DR_GP0 to TRCLK_CKO_GP3 falling edge setup time t24 16 μs TRCLK_CKO_GP3 symbol burst period t35 1.3 6.2 μs PA nominal power to TRCLK_CKO_GP3 activity/entry into TX state t36 14 μs RC_PHY_RDY to TRCLK_CKO_GP3 off t37 10 μs RC_PHY_RDY to PA power shutdown

Table 12. MAC Timing

Parameter Min Typ Max Unit Test Conditions/Comments

t26 38 μs Time from frame received to rx_pkt_rcvd interrupt generation t27 150 μs

t28 150 μs

t

RX_MAC_DELAY

192 μs IEEE 802.15.4 mode as defined by the standard

Time allowed, from issuing a RC_TX command, to update Register delaycfg2, Bit mac_delay_ext (0x10B[7:0])

Time allowed, from issuing a RC_TX command, to cancel the RC_TX command

Rev. 0 | Page 10 of 72

ADF7241

SCLK

TIMING DIAGRAMS

SPI Interface Timing Diagram

CS

t4t

t

MISO

MOSI

t

3

2

t

1

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X BIT 7

t

7

7 765432107

5

t

6

t

8

Figure 3. SPI Interface Timing

Additional description and timing diagrams are available in the Serial Peripheral interface section.

Sleep-to-Idle SPI Timing Diagrams

CS

SCLK

MISO

t

12

t

1

76543210

t

6

Figure 4. Sleep-to-Idle State Timing

t

16

t

11

t10t

9

09322-002

t

9

X

09322-003

CS

SPI COMMAND

TO ADF7242

DEVICE STATUS

RC_RESET OR

RC_SLEEP

IDLEIDLE, PHY_RDY, RX SLEEP

09322-064

Figure 5. Wake-Up After an RC_RESET or RC_SLEEP Command

Rev. 0 | Page 11 of 72

ADF7241

MAC Delay Timing Diagram

PACKET

TRANSMITTED

PACKET

RECEIVED

RC_STATUS

REGIST E R irq_src0, FIELD rc_ready

REGISTER irq_sr c1, FIELD rx_pkt_rcvd

REGISTER irq_src1, FIELD tx_pkt_sent

VALID IEEE802.15.4-2006 FRAME

RX TX

tx_mac_dela y +

mac_delay_ext

t

26

t

27,t28

FRAME IN TX_BUFFER

PHY_RDY

09322-016

Figure 6. IEEE 802.15.4 MAC Timing

Rev. 0 | Page 12 of 72

ADF7241

5

IEEE 802.15.4 RX SPORT Mode Timing Diagrams

Table 13. IEEE 802.15.4 RX SPORT Modes Configurations

Register rc_cfg, Field rc_mode (0x13E[7:0])

2 1 Bit clock and data available (see Figure 7) 0 7 Symbol clock and data available (see Figure 8)

COMMAND

RC_STATUS

PREVIOUS STATE

t

RX_MAC_DELAY

TRCLK_CKO_GP3

DR_GP0

PREAMBLE SFD PHR PSDU

Register gp_cfg, Field gpio_config (0x32C[7:0]) Functionality

RC_PHY_RDYRC_RX

RX PHY_RDY

t

29

t

21

t

24

.....

t

21

DATA

INVALID

COMMAND

RC_STATUS

TRCLK_CKO_GP3

GP6, GP5, GP1, GP0

1

GP6 = RXEN_GP6 GP5 = TXEN _G P GP1 = DT_GP1 GP0 = DR_GP0

TRCLK_CKO_GP3

PREVIOUS STATE

t

RX_MAC_DELAY

1

.....

DR_GP0

.....

t

23

t

22

Figure 7. IEEE 802.15.4 RX SPORT Mode: Bit Clock and Data Available

RX PHY_RDY

PREAMBLE SFD PHR PSDU

SYMBOL

t

21

[3:0]

t

[3:0]

26

Figure 8. IEEE 802.15.4 RX SPORT Mode: Symbol Clock Output

RC_PHY_RDYRC_RX

t

21

[3:0] [3:0]

09322-004

t

29

09322-009

Rev. 0 | Page 13 of 72

ADF7241

IEEE 802.15.4 TX SPORT Mode Timing Diagram

Table 14. IEE 802.15.4 TX SPORT Mode Configurations

Register rc_cfg, Field rc_mode (0x13E[7:0])

3 1 or 4 Transmission starts after PA ramp up (see Figure 9)

Register gp_cfg, Field gpio_config (0x32C[7:0]) Functionality

gpio_config = 1: data clocked in on rising edge of clock gpio_config = 4: data clocked in on falling edge of clock

RC_TX

RC_PHY_RDY

RC STATE

PA POWER

PACKET

COMPONENT

PHY_RDY

TRCLK_CKO_GP3

DT_GP1

TRCLK_CKO_GP3

DT_GP1 SAM P LE

t

35

PREAMBLE SFD

REGISTER gp_cfg, FIELD gpio_config = 1 DATA CLOCKED IN ON RISING EDGE

DT_GP1

t

32

t

33

Figure 9. IEEE 802.15.4-2006 TX SPORT Mode

Refer to the SPORT Interface section for further details.

TX

PHR

TRCLK_CKO_GP3

DT_GP1 SAM P LE

t

34

PSDU

.....

PACKET DATA

.....

REGISTER gp_cfg, FIELD gpio_config = 4 DATA CLOCKED IN ON FALLING EDG E

DT_GP1

t

32

t

33

PHY_RDY

t

37

t

36

t

34

09322-122

Rev. 0 | Page 14 of 72

ADF7241

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 15.

Parameter Rating

VDD_BAT to GND −0.3 V to +3.9 V Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance 26°C/W Reflow Soldering

Peak Temperature 260°C Time at Peak Temperature 40 sec

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The exposed paddle of the LFCSP package should be connected to ground.

This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

ESD CAUTION

Rev. 0 | Page 15 of 72

ADF7241

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PABIAOP_ATB4

PAVSUP_ATB3

VDD_BAT

XOSC32KN_ATB2

XOSC32KP_GP7_ATB1

CREGDIG1

RXEN_GP6

32313029282726

RBIAS

RFIO1P RFIO1N RFIO2P RFIO2N

1 2 3 4 5 6 7 8

ADF7241

TOP VIEW

(Not to Scale)

9

10111213141516

XOSC26P

CREGVCO

VCOGUARD

CREGSYNTH

CREGRF1

CREGRF2

CREGRF3

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED TO GRO UND.

Figure 10. Pin Configuration

Table 16. Pin Function Descriptions

Pin No. Mnemonic Description

1 CREGRF1

Regulated Supply Terminal for RF Section. Connect a 220 nF decoupling capacitor from this pin to

GND. 2 RBIAS Bias Resistor 27 kΩ to Ground. 3 CREGRF2 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor to ground. 4 RFIO1P Differential RF Input Port 1 (Positive Terminal). A 10 nF coupling capacitor is required. 5 RFIO1N Differential RF Input Port 1 (Negative Terminal). A 10 nF coupling capacitor is required. 6 RFIO2P Differential RF Input/Output Port 2 (Positive Terminal). A 10 nF coupling capacitor required. 7 RFIO2N Differential RF Input/Output Port 2 (Negative Terminal). A 10 nF coupling capacitor required. 8 CREGRF3 Regulated Supply for RF Section. Connect a 100 pF decoupling capacitor from this pin to GND. 9 CREGVCO Regulated Supply for VCO Section. Connect a 220 nF decoupling capacitor from this pin to GND. 10 VCOGUARD Guard Trench for VCO Section. Connect to Pin 9 (CREGVCO). 11 CREGSYNTH Regulated Supply for PLL Section. Connect a 220 nF decoupling capacitor from this pin to GND. 12 XOSC26P

Terminal 1 of External Crystal and Loading Capacitor. This pin is no connect (NC) when an external

oscillator is used. 13 XOSC26N Terminal 2 of External Crystal and Loading Capacitor. Input for external oscillator. 14 DGUARD Guard Trench for Digital Section. Connect to Pin 15 (CREGDIG2). 15 CREGDIG2 Regulated Supply for Digital Section. Connect a 220 nF decoupling capacitor to ground. 16 DR_GP0 SPORT Receive Data Output/General-Purpose IO Port. 17 DT_GP1 SPORT Transmit Data Input/General-Purpose IO Port. 18 IRQ2_TRFS_GP2 Interrupt Request Output 2/IEEE 802.15.4-2006 Symbol Clock/General-Purpose IO Port. 19 TRCLK_CKO_GP3 SPORT Clock Output/General-Purpose IO Port. 20 IRQ1_GP4 Interrupt Request Output 1/General-Purpose IO Port. 21 MISO SPI Interface Serial Data Output. 22 SCLK SPI Interface Data Clock Input. 23 MOSI SPI Interface Serial Data Input. 24

CS

SPI Interface Chip Select Input (and Wake-Up Signal). 25 TXEN_GP5 External PA Enable Signal/General-Purpose IO Port. 26 RXEN_GP6 External LNA Enable Signal/General-Purpose IO Port. 27 CREGDIG1 Regulated Supply for Digital Section. Connect a 1 nF decoupling capacitor from this pin to ground. 28 XOSC32KP_GP7_ATB1 Terminal 1 of 32 kHz Crystal Oscillator/General-Purpose IO Port/Analog Test Bus 1. 29 XOSC32KN_ATB2 Terminal 2 of 32 kHz Crystal Oscillator/Analog Test Bus 2.

TXEN_GP5 25

CS

24 23

MOSI SCLK

22

MISO

21 20

IRQ1_GP4

19

TRCLK_CKO_GP3

18

IRQ2_TRFS_GP2 DT_GP1

17

DR_GP0

DGUARD

XOSC26N

CREGDIG2

09322-010

Rev. 0 | Page 16 of 72

ADF7241

Pin No. Mnemonic Description

30 VDD_BAT Unregulated Supply Input from Battery. 31 PAVSUP_ATB3 External PA Supply Terminal/Analog Test Bus 3. 32 PABIAOP_ATB4 External PA Bias Voltage Output/Analog Test Bus 4. 33 (EPAD) GND Common Ground Terminal. The exposed paddle must be connected to ground.

Rev. 0 | Page 17 of 72

ADF7241

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

PACKET ERROR RATE (%)

0.4

0.2

0

–100 –90 –80 –70 –60 –50 –40 –30 –20

–96 –93

RF INPUT POWER LEVEL (dBm)

2.405GHz, 1.8V, + 25°C

2.48GHz, 1.8V, +25°C

2.405GHz, 3.6V, + 25°C

2.48GHz, 3.6V, +25°C

2.405GHz, 1.8V, –40°C

2.48GHz, 1.8V, –40°C

2.405GHz, 3.6V, –40°C

2.48GHz, 3.6V, –40°C

2.405GHz, 1.8V, + 85°C

2.48GHz, 1.8V, +85°C

2.405GHz, 3.6V, + 85°C

2.48GHz, 3.6V, +85°C

09322-095

Figure 11. IEEE 802.15.4-2006 Packet Mode Sensitivity vs. Temperature and

VDD_BAT, f

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

PACKET ERROR RATE (%)

0.4

0.2

0

–100 –90 –80 –70 –60 –50 –40 –30 –20 –96.5 –95

= 2.405 GHz, 2.45 GHz, 2.48 GHz, RFIO2x

CHANNEL

RF INPUT POWER LEVEL (dBm)

3.6V, +25°C

1.8V, +25°C

3.6V, –40°C

1.8V, –40°C

3.6V, +85°C

1.8V, +85°C

09322-046

Figure 12. IEEE 802.15.4-2006 Packet Mode PER vs. RF Input Power Level vs.

Temperature and VDD_BAT, f

= 2.45 GHz, RFIO2x

CHANNEL

80

70

60

50

40

30

20

REJECTION LE V EL (d B)

10

0

–10

–45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30

BLOCKER FREQ UE NCY OFFSET (MHz)

1.8V, +25°C

3.6V, +25°C

1.8V, –40° C

3.6V, –40° C

1.8V, +85°C

3.6V, +85°C

09322-048

Figure 14. IEEE 802.15.4-2006 Packet Mode Blocker Rejection vs. Temperature

and VDD_BAT, Modulated Blocker, P

f

= 2.45 GHz, RFIO2x

CHANNEL

80

70

60

50

40 30

20

10

0

BLOCKER REJECTION LEVEL (dB)

–10

–20

–110 –90 –70 –50 –30 –10 10 50 70 90 110

BLOCKER FRE QUENCY OFFSET (MHz )

= −85 dBm + 3 dB,

WANTED

VDD_BAT = 3.6V TEMPERAT URE = 25°C

09322-049

Figure 15. IEEE 802.15.4-2006 Packet Mode Wide-Band Blocker Rejection,

CW Blocker, P

= −95 dBm + 3 dB, f

WANTED

= 2.45 GHz, RFIO2x

CHANNEL

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

PACKET ERROR RATE (%)

0.4

0.2

0 –100 –98 –96

–94 –92 –90 –88 –86 –84 –82 –80

–96 –93

RF INPUT POWER LEVEL (dBm)

2.405GHz, 1.8V, +25°C

2.450GHz, 1.8V, +25°C

2.475GHz, 1.8V, +25°C

2.405GHz, 3.6V, +25°C

2.450GHz, 3.6V, +25°C

2.475GHz, 3.6V, +25°C

2.405GHz, 1.8V, –40°C

2.450GHz, 1.8V, –40°C

2.475GHz, 1.8V, –40°C

2.405GHz, 3.6V, –40°C

2.450GHz, 3.6V, –40°C

2.475GHz, 3.6V, –40°C

2.405GHz, 1.8V, +85°C

2.450GHz, 1.8V, +85°C

2.475GHz, 1.8V, +85°C

2.405GHz, 3.6V, +85°C

2.450GHz, 3.6V, +85°C

2.475GHz, 3.6V, +85°C

Figure 13. IEEE 802.15.4 Packet Mode Sensitivity vs. Temperature and

VDD_BAT, f

= 2.405 GHz, 2.45 GHz, 2.475 GHz, RFIO1x

CHANNEL

09322-047

Rev. 0 | Page 18 of 72

80

70

60

50

40 30

20

10

0

BLOCKER REJECTION LEVE L (dB)

–10

–20

–20 –16 –12 –8 –4 0 4 8 12 16 20

BLOCKER FREQ UE NCY OFFSET (MHz)

VDD_BAT = 3.6V TEMPERATURE = 2 5° C

Figure 16. IEEE 802.15.4 Packet Mode Narrow-Band Blocker Rejection,

CW Blocker, P

= −95 dBm + 3 dB, f

WANTED

= 2.45 GHz, RFIO2x

CHANNEL

09322-050

ADF7241

–

80

70

60

50

40

30

20

1.8V, +25° C

3.6V, +25° C

10

1.8V, –40°C

BLOCKER REJECT ION LEVE L (dB)

3.6V, –40°C

1.8V, +85° C

0

3.6V, +85° C

–10

–45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30

BLOCKER FREQ UE NCY OFFSET (MHz)

Figure 17. IEEE 802.15.4 Packet Mode Wide-Band Blocker Rejection vs.

Temperature and VDD_BAT, Modulated Blocker, P

= 2.45 GHz, RFIO2x

f

CHANNEL

80

70

60

50

40

30

20

REJECTION LEVEL (dB)

1.8V, +25°C

3.6V, +25°C

10

1.8V, –40° C

3.6V, –40° C

1.8V, +85°C

0

3.6V, +85°C

–10

–20 –16 –12 –8 –4 0 4 8 12 16 20

INTERFERER FREQUENCY OFFSET (MHz)

= −95 dBm + 3 dB,

WANTED

Figure 18. IEEE 802.15.4 Packet Mode Narrow-Band Blocker Rejection vs.

Temperature and VDD_BAT, Modulated Blocker, P

= 2.45 GHz, RFIO2x

f

CHANNEL

20

CHANNEL 2.405G Hz CHANNEL 2.48G Hz

–22

–24

–26

–28

–30

–32

BLOCKER REJE CTION L E VEL (dBm)

–34

–36

–110 –90 –70 –50 –30 –10 10 30 50 70 90 110

BLOCKER FREQUENCY OF FSET (MHz )

= −95 dBm + 3 dB,

WANTED

Figure 19. IEEE 802.15.4 Packet Mode Out-of-Band Blocker Rejection,

CW Blocker, P

= −95 dBm + 3 dB, f

WANTED

= 2.405 GHz and 2.48 GHz,

CHANNEL

RFIO2x, VDD_BAT = 3.6 V, Temperature = 25°C

09322-099

09322-100

09322-101

6

MAX 1.8V, + 25°C

5

MIN 1.8V, + 25°C MAX 3.6V, + 25°C

4

MIN 3.6V, + 25°C

3 2 1

0 –1 –2

RSSI ERROR (dB)

–3 –4 –5 –6

–95 –90 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20

RF INPUT LEVEL (dBm)

MAX 1.8V, –40° C MIN 1.8V, –40°C MAX 3.6V, –40° C MIN 3.6V, –40°C

MAX 1.8V, +85° C MIN 1.8V, + 85°C MAX 3.6V, +85° C MIN 3.6V, + 85°C

09322-112

Figure 20. IEEE 802.15.4 Packet Mode RSSI Error vs. RF Input Power Level vs.

Temperature and VDD_BAT, f

275 250 225 200 175 150 125 100

75

SQI READBACK VALUE

50 25

0

–95–100 –90 –85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25–20

MAX 1.8V, +25°C MAX 3.6V, +25°C MAX 1.8V, –4 0°C MAX 3.6V, –4 0°C MAX 1.8V, +85°C MAX 3.6V, +85°C

RF INPUT LEVEL (dBm)

= 2.45 GHz, RFIO2x

CHANNEL

MIN 1.8V, + 25°C MIN 3.6V, + 25°C MIN 1.8V, –40°C MIN 3.6V, –40°C MIN 1.8V, + 85°C MIN 3.6V, + 85°C

09322-113

Figure 21. IEEE 802.15.4 Packet Mode SQI vs. RF Input Power Level vs.

Temperature and VDD_BAT, f

110 100

90 80 70 60 50 40 30

CCA DETECTION RATE (%)

20 10

0

–90 –15–85 –80 –75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20

–80 dBm

–90 dBm

–70 dBm

THRESHOLD =

–50

–60

dBm

RF INPUT POWER LEVE L (dBm)

= 2.45 GHz, RFIO2x

CHANNEL

–30

–40

dBm

–20 dBm

09322-114

Figure 22. IEEE 802.15.4-2006 CCA Operation vs. RSSI Threshold,

= 2.45 GHz, VDD_BAT = 3.6 V, Temperature = 25°C, RFIO2x

f

CHANNEL

Rev. 0 | Page 19 of 72

ADF7241

0

–10

–20

–30

–40

–50

–60

TRANSMITTER RF OUTPUT P OWER (dBm)

–70

–5 –4 –3 –2 –1 0 1 2 3 4 5

FREQUENCY ERROR (kHz)

1.8V, +25° C

3.6V, +25° C

1.8V, –40°C

3.6V, –40°C

1.8V, +85° C

3.6V, +85° C

09322-104

Figure 23. IEEE 802.15.4-2006 Transmitter Spectrum vs. Temperature and

VDD_BAT, f

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

TRANSMIT T E R E RRO R VE CT OR MAGNIT UDE (%)

1.0 2405 2415 2425 2435 2445 2455 2465 2475

= 2.45 GHz, Output Power = 3 dBm

CHANNEL

CHANNEL FREQUENCY (MHz)

EVM 1.8V , +25°C EVM 3.6V , +25°C EVM 1.8V , –40°C EVM 3.6V , –40°C EVM 1.8V , +85°C EVM 3.6V , +85°C

09322-105

Figure 24. IEEE 802.15.4-2006 Transmitter EVM vs. Temperature and

VDD_BAT at All Channels, Output Power = 3 dBm

4.0

3.5

3.0

2.5

2.0

1.5

1.0

PA OUTPUT POWER LEVEL (dBm)

0.5

0

2.40 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48 FREQUENCY (GHz )

3.6V, +85°C

3.6V, +25°C

3.6V, –40° C

1.8V, –40° C

1.8V, +25°C

1.8V, +80°C

09322-110

Figure 25. PA Output Power vs. RF Carrier Frequency, Temperature, and VDD_BAT

(A discrete matching network and a harmonic filter are used as per the

ADF7241 reference design.)

4 2 0

–2 –4 –6

–8 –10 –12

–14 –16 –18

–20 –22

PA OUTPUT POWER LEVEL (dBm)

–24 –26

–28

3 4 5 6 7 8 9 101112131415

PA LEVEL SETTING

3.6V, +85°C

3.6V, +25°C

3.6V, –40° C

1.8V, –40° C

1.8V, +25°C

1.8V, +80°C

09322-111

Figure 26. PA Output Power vs. Control Word, Temperature, and VDD_BAT,

= 2.44 GHz (A discrete matching network and a harmonic filter are

f

CHANNEL

used as per the ADF7241 reference design.)

5.0

2.5 0

–2.5 –5.0

–7.5 –10.0 –12.5 –15.0 –17.5 –20.0 –22.5

TRANSMITTER OUTPUT POWER (dBm)

–25.0 –27.5

345678910111213141516

POWER AMPLIF I E R CONT RO L W O RD

HIGH POWER MODE DEFAULT MODE

09322-119

Figure 27. Transmitter Output Power vs. Control Word for Default and High

Power Modes, f

= 2.45 GHz, VDD_BAT = 3.6 V, Temperature = 25°C,

CHANNEL

RF Carrier Frequency, Temperature, and VDD_BAT

(A discrete matching network and a harmonic filter are used as per the

ADF7241 reference design.)

26.0

25.5

25.0

24.5

24.0

23.5

23.0

22.5

22.0

21.5

21.0

20.5

20.0

19.5

19.0

18.5

18.0

17.5

17.0

16.5

TRANSMI T TER CURRENT CONSUMPT ION (mA)

16.0 3 4 5 6 7 8 9 10 11 12 13 14 15

HIGH POWER MO DE DEFAULT MODE

POWER AMPLIFIER CONTROL WORD

09322-120

Figure 28. Transmitter Current Consumption vs. Control Word, for Default

and High Power Modes, f

= 2.45 GHz, VDD_BAT = 3.6 V,

CHANNEL

Temperature = 25°C

Rev. 0 | Page 20 of 72

ADF7241

85

3-SIGMA TEMPERATURE E RROR

80 75

TEMPERAT URE READING (L INEAR FIT TING)

70

TEMPERAT URE READING

65

(POLYNOMIAL FITTING)

60 55 50 45 40 35 30 25 20 15 10

5 0

–5

FROM ADC READING (°C)

–10

TEMPERAT URE CAL CUL ATED

–15 –20 –25 –30 –35 –40

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATUR E (°C)

Figure 29. Temperature Sensor Performance

(Average of 1000 ADC Readbacks) and 3-∑ Error vs. Temperature,

VDD_BAT = 3.6 V

09322-116

Rev. 0 | Page 21 of 72

ADF7241

TERMINOLOGY

ACK

IEEE 802.15.4-2006 acknowledgment frame

ADC

Analog-to-digital converter

AGC

Automatic gain control

Battmon

Battery monitor

CCA

Clear channel assessment

BBRAM

Backup battery random access memory

CSMA/CA

Carrier-sense-multiple-access with collision avoidance

DR

Data rate

DSSS

Direct sequence spread spectrum

FCS

Frame check sequence

FHSS

Frequency hopping spread spectrum

FCF

Frame control field

LQI

Link quality indicator

MCR

Modem configuration register

MCU

Microcontroller unit

NC

Not connected

OCL

Offset correction loop

OQPSK

Offset-quadrature phase shift keying

PA

Power amplifier

PHR

PHY header

PHY

Physical layer

POR

Power-on reset

PSDU

PHY service data unit

RC

Radio controller

RCO32K

32 kHz RC oscillator

RSSI

Receive signal strength indicator

RTC

Real-time clock

SFD

Start-of-frame delimiter

SQI

Signal quality indicator

VCO

Voltage-controlled oscillator

WUC

Wak e -u p co nt r ol le r

XTO26M

26 MHz crystal oscillator

XTO32K

32 kHz crystal oscillator

Rev. 0 | Page 22 of 72

ANALOG DEVICES ADF7241 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

GENERAL SPECIFICATIONS

RF FREQUENCY SYNTHESIZER SPECIFICATIONS

TRANSMITTER SPECIFICATIONS

RECEIVER SPECIFICATIONS

AUXILIARY SPECIFICATIONS

CURRENT CONSUMPTION SPECIFICATIONS

TIMING AND DIGITAL SPECIFICATIONS

TIMING DIAGRAMS

SPI Interface Timing Diagram

Sleep-to-Idle SPI Timing Diagrams

MAC Delay Timing Diagram

IEEE 802.15.4 RX SPORT Mode Timing Diagrams

IEEE 802.15.4 TX SPORT Mode Timing Diagram

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY