ANALOG DEVICES ADF7025 Service Manual

High Performance

A

www.BDTIC.com/ADI

FEATURES

Low power, zero-IF RF transceiver
Frequency bands

431 MHz to 464 MHz
862 MHz to 870 MHz
902 MHz to 928 MHz

Data rates supported

9.6 kbps to 384 kbps, FSK

2.3 V to 3.6 V power supply
Programmable output power

−16 dBm to +13 dBm in 63 steps

Receiver sensitivity

−104.2 dBm at 38.4 kbps, FSK

−100 dBm at 172.8 kbps, FSK

−95.8 dBm at 384 kbps, FSK

Low power consumption

19 mA in receive mode
28 mA in transmit mode (10 dBm output)

ISM Band Transceiver IC

ADF7025

On-chip VCO and Fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Digital RSSI
Integrated TRx switch
Leakage current < 1 µA in power-down mode

APPLICATIONS

Wireless audio/video
Remote control/security systems
Wireless metering
Keyless entry
Home automation

R

LNA

R

FIN

R

FINB

RFOUT

BIAS LDO(1:4)

LNA

GAIN

DIVIDERS/

MUXING

LP FILTER

VCO

VCOIN CPOUT

FUNCTIONAL BLOCK DIAGRAM

DCINRSET CREG(1:4)

MODULATOR

N/N+1DIV P

PFD

TEMP

SENSOR

MUX

Σ-∆

DIV R

Figure 1.

7-BIT ADC

RING OSC

OSC1

DEMODUL ATOR

OSC2

OFFSET

CORRECTION

RSSI

OFFSET

CORRECTION

FSK MOD

CONTROL

CP

MUXOUT

TEST MUX

FSK

AGC

CONTROL

CLK

DIV

SYNCHRONIZER

CONTROL

CLKOUT

DATA

Tx/Rx

SERIAL

PORT

CE

DATA CLK

DATA I/O

INT/LOCK

SLE

SDATA

SREAD

SCLK

05542-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADF7025

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TABLE OF CONTENTS

Features .............................................................................................. 1

Automatic Sync Word Recognition ......................................... 22

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 7

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Frequency Synthesizer ................................................................... 15

Reference Input Section............................................................. 15

Choosing Channels for Best System Performance................. 17

Tr an sm it t er ...................................................................................... 18

Applications Section....................................................................... 23

LNA/PA Matching...................................................................... 23

Transmit Protocol and Coding Considerations ..................... 24

Device Programming after Initial Power-Up............................. 24

Interfacing to Microcontroller/DSP ........................................ 24

Serial Interface................................................................................ 27

Readback Format........................................................................ 27

Registers........................................................................................... 28

Register 0—N Register............................................................... 28

Register 1—Oscillator/Filter Register...................................... 29

Register 2—Transmit Modulation Register ............................ 30

Register 3—Receiver Clock Register ....................................... 31

Register 4—Demodulator Setup Register............................... 32

Register 5—Sync Byte Register................................................. 33

Register 6—Correlator/Demodulator Register ...................... 34

RF Output Stage.......................................................................... 18

Modulation Scheme ................................................................... 18

Receiver............................................................................................ 19

RF Front End............................................................................... 19

RSSI/AGC.................................................................................... 20

FSK Demodulators on the ADF7025....................................... 20

FSK Correlator/Demodulator................................................... 20

Linear FSK Demodulator.......................................................... 22

REVISION HISTORY

2/06—Rev. 0 to Rev. A

Replaced Figure 40 ................................................................Page 29

1/06—Revision 0: Initial Version

Register 7—Readback Setup Register...................................... 35

Register 8—Power-Down Test Register .................................. 36

Register 9—AGC Register......................................................... 37

Register 10—AGC 2 Register.................................................... 38

Register 12—Test Register......................................................... 39

Register 13—Offset Removal and Signal Gain Register ....... 40

Outline Dimensions ....................................................................... 41

Ordering Guide .......................................................................... 41

Rev. A | Page 2 of 44

ADF7025

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GENERAL DESCRIPTION

The ADF7025 is a low power, highly integrated FSK transceiver.
It is designed for operation in the license–free ISM bands of
433 MHz, 863 MHz to 870 MHz, and 902 MHz to 928 MHz.
The ADF7025 can be used for applications operating under the
European ETSI EN300-220 or the North American FCC (Part 15)
regulatory standards. The ADF7025 is intended for wideband,
high data rate applications with deviation frequencies from
100 kHz to 750 kHz and data rates from 9.6 kbps to 384 kbps.
A complete transceiver can be built using a small number of
external discrete components, making the ADF7025 very
suitable for price-sensitive and area-sensitive applications.

The transmit section contains a VCO and low noise

ractional-N PLL with output resolution of <1 ppm. The VCO

F
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.

The transmitter output power is programmable in 0.3 dB steps
f

rom −16 dBm to +13 dBm. The transceiver RF frequency, channel
spacing, and modulation are programmable using a simple 3-wire
interface. The device operates with a power supply range of 2.3 V
to 3.6 V and can be powered down when not in use.

A zero-IF architecture is used in the receiver, minimizing power
co

nsumption and the external component count, while avoiding
the need for image rejection. The baseband filter (low-pass) has
programmable bandwidths of ±300 kHz, ±450 kHz, and ±600 kHz.
A high-pass pole at ~60 kHz eliminates the problem of dc offsets
that is characteristic of zero-IF architecture.

The ADF7025 supports a wide variety of programmable
fe

atures, including Rx linearity, sensitivity, and filter bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.

An on-chip ADC provides readback of an i
ture sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±10°C over
the full operating temperature range of −40°C to +85°C. This
accuracy can be improved by doing a 1-point calibration at
room temperature and storing the result in memory.

ntegrated tempera-

Rev. A | Page 3 of 44

ADF7025

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SPECIFICATIONS

VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T
All measurements are performed using the EVAL-ADF7025DB1 using PN9 data sequence, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions

RF CHARACTERISTICS

Frequency Ranges (Direct Output) 862 870 MHz VCO adjust = 0, VCO bias = 10
902 928 VCO adjust = 3, VCO bias = 12
Frequency Ranges (Divide-by-2 Mode) 431 464 MHz See conditions for direct output
Phase Frequency Detector Frequency RF/256 24 MHz

TRANSMISSION PARAMETERS

Data Rate

FSK 9.6 384 kbps

FSK Frequency Deviation 100 311.89 kHz PFD = 10 MHz, direct output

100 748.54 kHz PFD = 24 MHz, direct output
100 374.27 kHz PFD =24MHz, divide-by-2 mode
Deviation Frequency Resolution 221 Hz PFD = 3.625 MHz

Gaussian Filter BT 0.5
Transmit Power1 −20 +13 dBm VDD = 3.0 V, TA = 25°C
Transmit Power Variation vs. Temperature ±1 dB From −40°C to +85°C
Transmit Power Variation vs. V
Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz, 3 V, TA = 25°C
Programmable Step Size

−20 dBm to +13 dBm 0.3125 dB

Spurious Emissions

Integer Boundary −55 dBc 50 kHz loop B/W

Reference −65 dBc
Harmonics

Second Harmonic −27 dBc Unfiltered conductive

Third Harmonic −21 dBc

All Other Harmonics −35 dBc
VCO Frequency Pulling 30 kHz rms DR = 9.6 kbps
Optimum PA Load Impedance 39 + j61 Ω FRF = 915 MHz
48 + j54 Ω FRF = 868 MHz
54 + j94 Ω FRF = 433 MHz

RECEIVER PARAMETERS

FSK Input Sensitivity

Sensitivity at 38.4 kbps −104.2 dBm FDEV = 200 kHz, LPF B/W = ±300kHz

Sensitivity at 172.8 kbps −100 dBm FDEV = 200 kHz, LPF B/W = ±450kHz

Sensitivity at 384 kbps −95.8 dBm FDEV = 450kHz, LPF B/W = ±600kHz
Baseband Filter (Low-Pass) Bandwidths Programmable

±300 kHz

±450 kHz

±600 kHz
LNA and Mixer, Input IP3

Enhanced Linearity Mode +6.8 dBm

Low Current Mode −3.2 dBm

High Sensitivity Mode −35 dBm
Rx Spurious Emissions

−47 dBm >1 GHz at antenna input

DD

3

MIN

to T

, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.

MAX

±1 dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C

At BER = 1E − 3, FRF = 915 MHz,

LNA and P

Pin = −20 dBm, 2 CW interferers
FRF = 915 MHz, f1 = FRF + 3 MHz
F2 = FRF + 6 MHz, maximum gain

−57 dBm <1 GHz at antenna input

A matched separately

2

Rev. A | Page 4 of 44

ADF7025

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Parameter Min Typ Max Unit Test Conditions

CHANNEL FILTERING

Adjacent Channel Rejection

27 dB

(Offset = ±1 × LP Filter BW Setting)

Second Adjacent Channel Rejection

40 dB

(Offset = ±2 × LP Filter BW Setting)

Third Adjacent Channel Rejection

43 dB

(Offset = ±3 × LP Filter BW Setting)

Co-Channel Rejection −2 +24 dB

Wideband Interference Rejection 70 dB

BLOCKING

±1 MHz

42

dB
±2 MHz 51 dB
±10 MHz 64 dB
Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10
LNA Input Impedance

24 − j60

26 − j63

71 − j128

Ω FRF = 915 MHz, RFIN to GND

Ω FRF = 868 MHz

Ω FRF = 433 MHz

RSSI

Range at Input

−100 to

dBm

−36
Linearity ±2 dB
Absolute Accuracy ±3 dB
Response Time 150 µs

PHASE-LOCKED LOOP

VCO Gain 65 MHz/V

83 MHz/V

Phase Noise (In-Band) −89 dBc/Hz

Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset
Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868MHz
PLL Settling Time 40 µs

REFERENCE INPUT

Crystal Reference 3.625 24 MHz
External Oscillator 3.625 24 MHz
Load Capacitance 33 pF
Crystal Start-Up Time 1.0 ms Using 33 pF load capacitors
Input Level

CMOS

els

lev

TIMING INFORMATION

Chip Enabled to Regulator Ready 10 µs C
Crystal Oscillator Startup Time 1 ms With 19.2 MHz XTAL
Tx to Rx Turnaround Time

150 µs +

T

(5 ×

)

BIT

Desired signal (38.4 kbps DR, 200 kHz FDEV,

±300 KH
input sensitivity level, CW interferer power
level increased until BER = 10

z LP filter B/W) 6 dB above the

−3

Maximum rejection measured with CW

terferer at center of channel

in

Swept from 100 MHz to 2 GHz,

ed as channel rejection

measur

Desired signal (38.4 kbps DR, 200 kHz FDEV,

±300 KH
input sensitivity level, CW interferer power
level increased until BER = 10

z LP filter B/W) 6 dB above the

−3

−3

902 MHz to 928 MHz band,

O adjust = 3, VCO_BIAS_SETTING = 12

VC

862 MHz to 870 MHz band,

O adjust = 0, VCO_BIAS_SETTING = 10

VC

PA = 0 dB m , V

= 3.0 V, PFD = 10 MHz,

DD

FRF = 868 MHz, VCO_BIAS_SETTING = 10

Measured for a 10 MHz frequency step

hin 5 ppm accuracy,

to wit
PFD = 20 MHz, LBW = 50kHz

= 100 nF

REG

Time to synchronized data,

includes A

GC settling

Rev. A | Page 5 of 44

ADF7025

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Parameter Min Typ Max Unit Test Conditions

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INH

INL

INH/IINL

IN

Control Clock Input 50 MHz

LOGIC OUTPUTS

Output High Voltage, V
Output Low Voltage, V
CLK

Rise/Fall 5 ns

OUT

CLK

Load 10 pF

OUT

OH

OL

TEMPERATURE RANGE, TA −40 +85 °C
POWER SUPPLIES

Voltage Supply

V

DD

Transmit Current Consumption

−20 dBm 14.6 mA

−10 dBm 15.8 mA
0 dBm 19.3 mA
10 dBm 28 mA

Receive Current Consumption

Low Current Mode 19 mA
High Sensitivity Mode 21 mA

Power-Down Mode

Low Power Sleep Mode

1

Measured as maximum unmodulated power. Output power varies with both supply and temperature.

2

Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.

3

Follow the matching and layout guidelines in the LN section to achieve the relevant FCC/ETSI specifications. A/PA Matching

0.7 × V

V

DD

0.2 × VDDV
±1 µA
10 pF

DVDD − 0.4

V IOH = 500 µA

0.4 V IOL = 500 µA

2.3 3.6 V All VDD pins must be tied together
FRF = 915 MHz, V

= 3.0 V,

DD

PA is matched in to 50 Ω

0.1 1 µA

Rev. A | Page 6 of 44

ADF7025

S

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TIMING CHARACTERISTICS

VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.

Table 2.

SCLK

1

Limit at T

MIN

to T

MAX

Unit Test Conditions/Comments

<10 ns SDATA to SCLK setup time

<25 ns SCLK to SREAD data valid, readback

<25 ns SREAD hold time after SCLK, readback

<10 ns SCLK to SLE disable time, readback

t

3

t

4

Parameter

t

1

t2 <10 ns SDATA to SCLK hold time

t3 <25 ns SCLK high duration

t4 <25 ns SCLK low duration

t5 <10 ns SCLK to SLE setup time

t6 <20 ns SLE pulse width

t

8

t

9

t

10

1

Guaranteed by design, not production tested.

TIMING DIAGRAMS

DATA

SLE

SCLK

SDATA

SLE

SREAD

t

1

DB31 (MSB) DB30 DB2

t

2

Figure 2. Serial Interface Timing Diagram

t

1

REG7 DB0

(CONTROL BIT C1)

t

2

t

3

X RV16 RV15 RV2 RV1

t

8

t

9

Figure 3. Readback Timing Diagram

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

10

t

6

05542-002

05542-003

Rev. A | Page 7 of 44

ADF7025

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±1 × DATA RATE/32 1/DATA RATE

RxCLK

RxDATA

DATA

Figure 4. RxData/RxCLK Timing Diagram

05542-004

Rev. A | Page 8 of 44

ADF7025

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 125°C
MLF θJA Thermal Impedance
Lead Temperature Soldering

Vapor Phase (60 sec) 235°C

Infrared (15 sec) 240°C

1

GND = CPGND = RFGND = DGND = AGND = 0 V.

1

−0.3 V to +5 V

26°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance, RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. A | Page 9 of 44

ADF7025

K

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D
N
G

1

O

D

D

C
V
C

8
4

O

N

N

C

G

G

V

7

6

5

4

4

4

T

3

U

3
D
N

G

4
4

G

D

O

E

D

P

D

R

V

3
4

D

C

V

V

1

0

2

4

4

4

T
U
O

2

1

X

C

C

U

S

S

M

O

O

8

7

9

3

3

3

VCOIN

VREG1

VDD1

RFOUT

RFGND

RFIN

RFINB

R

LNA

VDD4

RSET

VREG4

GND4

1

PIN 1
INDICATO R

2

3

4

5

6

7

8

9

10

11

12

3
1

I
_
X

I
M

4
1

I
_
X

I
M

ADF7025

(Not to Sca le)

5

6

1

1

Q

Q
_

_

X

X

I

I

M

M

TOP VIEW

8

9

7

1

1

1
I

I

4

_

_

D

T

T

N

L

L

I

I

G

F

F

0
2

Q
_
T
L

I
F

3

1

2

2

2

2
4

A

Q

_

D

_

T

T

N

S

L

G

I

E

F

CLKOUT

36

DATA CL

35

DATA I/O

34

INT/LOCK

33

VDD2

32

VREG2

31

ADCIN

30

GND2

29

SCLK

28

SREAD

27

SDATA

26

SLE

25

4
2

E
C

5542-006

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCOIN

The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.

2 VREG1

Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin
and ground for regulator stability and noise rejection.

3 VDD1

Voltage Supply for PA Block. Decoupling capacitors of 0.1 µF and 10 pF should be placed as close as possible
to this pin. All VDD pins should be tied together.

4 RFOUT

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output

should be impedance-matched to the desired load using suitable components. See the Transmitter section.
5 RFGND Ground for Output Stage of Transmitter.
6 RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 R

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

LNA

9 VDD4 Voltage supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
11 VREG4

Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND

for regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER Block.
13 to 18 MIX/FILT Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
19, 22 GND4 Ground for LNA/MIXER Block.
20, 21, 23 FILT/TEST_A Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected.
24 CE

Chip Enable. Bringing CE low puts the ADF7025 into complete power-down. Register values are lost

when CE is low, and the part must be reprogrammed once CE is brought high.
25 SLE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches. A latch is selected using the control bits.
26 SDATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is

a high impedance CMOS input.
27 SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7025 to the microcontroller.

The SCLK input is used to clock each readback bit (ADC readback) from the SREAD pin.
28 SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. A | Page 10 of 44

ADF7025

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Pin No. Mnemonic Description

29 GND2 Ground for Digital Section.
30 ADCIN

31 VREG2

32 VDD2

33 INT/LOCK

34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
35 DATA CLK

36 CLKOUT

37 MUXOUT

38 OSC2

39 OSC1 The reference crystal should be connected between this pin and OSC2.
40 VDD3

41 VREG3

42 CPOUT

43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
44 to 47 GND Grounds for VCO Block.
48 CVCO A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be ac
Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin.

Regulator Voltage for Digital Block. A 100 nF in paralle
between this pin and ground for regulator stability and noise rejection.

Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible

his pin.

to t
Bidirectional Pin. In output mode (interrupt mod

it has found a match for the preamble sequence.
In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold

when a valid
In this mode, a demodulator lock can be asserted with minimum delay.

In receive mode, the pin outputs the synchronized data clock
center of the received data.

A Divided-Down Version of the Crystal Reference with O
to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.

This pin provides the lock_detect signal, which is used t
frequency. Other signals include regulator_ready, which is an indicator of the status of the serial interface
regulator.

The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by

riving this pin with CMOS levels and disabling the crystal oscillator.

d

Voltage Supply for the Charge Pump and PLL Dividers
with a 0.01 µF capacitor.

Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor
should be pl

Charge Pump Output. This output generates current pul
The integrated current changes the control voltage on the input to the VCO.

preamble has been detected. Once the threshold is locked, NRZ data can be reliably received.

aced between this pin and ground for regulator stability and noise rejection.

l with a 5.1 pF capacitor should be placed

e), the ADF7025 asserts the INT/LOCK pin when

utput Driver. The digital clock output can be used

o determine if the PLL is locked to the correct

. This pin should be decoupled to ground

ses that are integrated in the loop filter.

cessed through this pin.

. The positive clock edge is matched to the

Rev. A | Page 11 of 44

ADF7025

A

m

G

A

R

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TYPICAL PERFORMANCE CHARACTERISTICS

CARRIER POWER 6.11dBm
REF –60dBc/Hz 10.00dB/

ATTEN 2.00d B MKR1 10.00KHz

1

–88.46dBc/Hz

REF 10dB
PEAK
LO
10dB/

1

REF LEVEL

10.00dBm

ATTEN 20dB

3

4

MKR4 3.482GHz

SWEEP 16.52ms (601pts)

100Hz 10Hz

FREQUENCY OFFSET

05542-007

Figure 6. Phase Noise Response at 915 MHz, VDD = 3.0 V, ICP = 0.867 mA

REF 10dBm
NORM LO G 10d B/

CENTER 915.00MHz
#RES BW 10kHz

ATTEN 20dB

1R

1

VBW 10kHz S PAN 5MHz

SWEEP 60. 32ms (601pts)

MKR1 400Hz

0.69dB

05542-008

Figure 7. Output Spectrum in FSK Modulation (915 MHz,

172.8 kbps Data Rate, 200 kHz Frequency Deviation)

0

–5

±600KHz

–10

FILTER B/W

–15

±450KHz

–20

FILTER B/W

–25

TION LEVEL (dB)

–30

–35

ATTENU

–40

–45

–50

–1500 –1200 –600 –300 300 600 1200 1500

–1800 –900 0 900 1800

±300KHz
FILTER B/W

FREQUENCY (KHz)

Figure 8. Baseba nd Filter R esponse

START 100MHz
RES BW 3MHz

VBW 3MHz

STOP 10.000GHz

SWEEP 16.52ms (601pts)

05542-010

Figure 9. Harmonic Response, RFOUT Matched to 50 Ω, No Filter

REF 15dBm ATTEN 30d B

1R

NORM

LOG

10dB/

MARKER ∆

1.834000000GHz
–62.57dB

LgAv

W1S2

S3FC

AA
£(f):
FTun
Swp

START 800MHz
#RES BW 30kHz

1

VBW 30kHz

∆ Mkr1 1.834GHz

–62.57dB

STOP 5.000GHz

SWEEP 5.627s ( 601pts)

05542-011

Figure 10. Harmonic Response, Murata Dielectric Filter

20

11µA

9µA

PA SE T T I NG

5µA

7µA

05542-053

15

10

5

0

–5

OUTPUT POWE

–10

P

–15

–20

–25

05542-009

1 5 9 13172125293337414549535761

Figure 11. PA Output Power vs. Setting

Rev. A | Page 12 of 44

ADF7025

C

d

–

–

www.BDTIC.com/ADI

20

RSSI LEVEL (d B)

0

–20

–40

–60

–80

–100

–120

ACTUAL INPUT LEVEL

RSSI READBACK LEVE L

RF I/P (dB)

Figure 12. Digital RSSI Readback

70

60

50

40

TION (dB)

30

20

10

LEVEL OF REJE

0

–

10

–12 –6 0 6 12

OFFSET OF INTERFERER FROM WANTED SIGNAL (MHz)

Figure 13. Wideband Interference Rejection;

Wanted Signal (901 MHz, 38.4 kbps Data Rate, 200 kHz Frequency

Deviation) at 6 dB Above Sensitivity Point; Interferer = CW Jammer

20–120 –100 –80 –60 –40 –20 0

05542-014

05542-013

0

–1

–2

–3

–4

LOG (BER)

–5

–6

–7

–8

–116 –108 –100 –90 –78

RF I/P LEVEL (dBm)

DATA RATE = 384k, FDEV = 450k
DATA RATE = 172k, FDEV = 200k
DATA RATE = 38.4k, FDEV = 200k

Figure 15. BER vs. Data Rate (Combined Matching Network)

50

= CORRELATOR
= LINEAR

0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800

DEVIATION F REQUENCY (kHz )

Bm)

SENSITIVITY POINT (

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

Figure 16. Sensitivity vs. Mod Index (Data Rate = 384 kbps, Baseband

Filter Bandwidth = ±600 kHz), for Both Demodulator Types

05542-016

05542-017

0

–1

–2

–3

–4

BER

2.3V, +25°C
3V, +25°C

–5

3.6V, +25°C

2.3V, –40°C

–6

3V, –40°C

3.6V, –40°C

2.3V, +85°C

–7

3V, +85°C

3.6V, +85°C

–8

–115 –110 –105 –100 –95 –90 –85

Figure 14. Sensitivity vs. V

RF I/P LEVEL (dBm)

and Temperature

DD

05542-015

(172.8 kbps Data Rate, 200 kHz Frequency Deviation,

Baseband Bandwidth ±600 kHz)

Rev. A | Page 13 of 44

60

= CORRELAT OR

–65

–70

–75

–80

–85

–90

SENSITIVITY POI NT (dBm)

–95

–100

–105

= CORRELAT OR
=LINEAR

=LINEAR

BB BW = ±450kHz BB BW = ±600kHz

0 50 100 150 200 250 300 350 400 450 500 550 600

DEVIATION FREQUENCY (kHz)

05542-018

Figure 17. Sensitivity vs. Mod Index (Data Rate = 172.8 kbps),

for Both Demodulator Types

ADF7025

–

d

www.BDTIC.com/ADI

60

–65

–70

–75

Bm)

–80

–85

–90

–95

SENSITIVITY POINT (

–100

–105

–110

Figure 18. Sensitivity vs. Mod Index (Data Rate = 38.4 kbps),

= CORRELATOR
=LINEAR

BB BW =

±300kHz

0 5 0 100 15 0 200 250 300 350 400 450 500 550 600

DEVIATION F REQUENCY (kHz )

BB BW =

±450kHz

BB BW =

±600kHz

for both Demodulator Types

05542-052

Rev. A | Page 14 of 44