ANALOG DEVICES ADF7023-J Service Manual

High Performance, Low Power, ISM Band

FSK/GFSK/MSK/GMSK Transceiver IC

ADF7023-J

Rev. A

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Data Sheet

FEATURES

Ultralow power, high performance transceiver Frequency bands: 902 MHz to 958 MHz Data rates supported: 1 kbps to 300 kbps

2.2 V to 3.6 V power supply Single-ended and differential power amplifiers (PAs) Low IF receiver with programmable IF bandwidths

100 kHz, 150 kHz, 200 kHz, 300 kHz

Receiver sensitivity (BER)

−116 dBm at 1.0 kbps, 2FSK, GFSK

−107.5 dBm at 38.4 kbps, 2FSK, GFSK

−106.5 dBm at 50 kbps, 2FSK, GFSK

−105 dBm at 100 kbps, 2FSK, GFSK

−104 dBm at 150 kbps, GFSK, GMSK

−103 dBm at 200 kbps, GFSK, GMSK

−100.5 dBm at 300 kbps, GFSK, GMSK

Very low power consumption

12.8 mA in PHY_RX mode (maximum front-end gain)

11.9 mA in PHY_RX mode (AGC off, ADC off)

24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)

0.75 µA in PHY_SLEEP mode (32 kHz RC oscillator active)

1.28 µA in PHY_SLEEP mode (32 kHz XTAL oscillator active)

0.33 µA in PHY_SLEEP mode (Deep Sleep Mode 1) RF output power of −20 dBm to +13.5 dBm (single-ended PA) RF output power of −20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) Digital received signal strength indication (RSSI) Integrated PLL loop filter and Tx/Rx switch Fast automatic voltage controlled oscillator ( VCO) calibration Automatic synthesizer bandwidth optimization On-chip, low power, custom 8-bit processor

Radio control Packet management Smart wake mode

SPORT mode support

High speed synchronous serial interface to Tx and Rx Data

for direct interfacing to processors and DSPs

Packet management support

Highly flexible for a wide range of packet formats Insertion/detection of preamble/sync word/CRC/address Manchester and 8b/10b data encoding and decoding Data whitening

Smart wake mode

Current saving low power mode with autonomous receiver

wake up, carrier sense, and packet reception

Downloadable firmware modules

Image rejection calibration, fully automated (patent

pending)

128-bit AES encryption/decryption with hardware

acceleration and key sizes of 128 bits, 192 bits, and 256 bits

Reed-Solomon error correction with hardware acceleration 240-byte packet buffer for Tx/Rx data Efficient SPI control interface with block read/write access Integrated battery alarm and temperature sensor Integrated RC and 32.768 kHz crystal oscillator On-chip, 8-bit ADC 5 mm × 5 mm, 32-lead, LFCSP package

APPLICATIONS

Smart metering IEEE 802.15.4g Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without n otice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADF7023-J Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

General Description ......................................................................... 4

Specifications ..................................................................................... 6

RF and Synthesizer Specifications .............................................. 6

Transmitter Specifications ........................................................... 7

Receiver Specifications ................................................................ 9

Timing and Digital Specifications ............................................ 12

Auxilary Block Specifications ................................................... 13

General Specifications ............................................................... 14

Timing Specifications ................................................................ 15

Absolute Maximum Ratings .......................................................... 16

ESD Caution ................................................................................ 16

Pin Configuration and Function Descriptions ........................... 17

Typical Performance Characteristics ........................................... 19

Terminology .................................................................................... 26

Radio Control .................................................................................. 27

Radio States ................................................................................. 27

Initialization ................................................................................ 29

Commands .................................................................................. 30

Automatic State Transitions ...................................................... 32

State Transition and Command Timing .................................. 33

Sport Mode ...................................................................................... 37

Packet Structure in Sport Mode ............................................... 37

Sport Mode in Transmit ............................................................ 37

Sport Mode in Receive ............................................................... 37

Transmit Bit Latencies in Sport Mode ..................................... 37

Packet Mode .................................................................................... 40

Preamble ...................................................................................... 40

Sync Word ................................................................................... 41

Payload ......................................................................................... 42

CRC .............................................................................................. 43

Postamble..................................................................................... 44

Transmit Packet Timing ............................................................ 44

Data Whitening .......................................................................... 45

Manchester Encoding ................................................................ 45

8b/10b Encoding ........................................................................ 45

Interrupt Generation ...................................................................... 46

Rev. A | Page 2 of 104

Interrupts in Sport Mode .......................................................... 48

ADF7023-J Memory Map ............................................................. 49

BBRAM ........................................................................................ 49

Modem Configuration RAM (MCR) ...................................... 49

Program ROM ............................................................................ 49

Program RAM ............................................................................ 49

Packet RAM ................................................................................ 50

SPI Interface .................................................................................... 51

General Characteristics ............................................................. 51

Command Access ....................................................................... 51

Sta t u s Wor d ................................................................................. 51

Command Queuing ................................................................... 52

Memory Access ........................................................................... 53

Low Power Modes .......................................................................... 56

Example Low Power Modes ...................................................... 59

Low Power Mode Timing Diagrams ........................................ 61

WUC Setup ................................................................................. 62

Firmware Timer Setup ............................................................... 63

Calibrating the RC Oscillator ................................................... 63

Downloadable Firmware Modules ............................................... 65

Writing a Module to Program RAM ........................................ 65

Image Rejection Calibration Module ...................................... 65

AES Encryption and Decryption Module............................... 65

Reed-Solomon Coding Module ............................................... 65

Radio Blocks .................................................................................... 67

Frequency Synthesizer ............................................................... 67

Crystal Oscillator ........................................................................ 68

Modulation .................................................................................. 68

RF Output Stage.......................................................................... 69

PA/LNA Interface ....................................................................... 69

Receive Channel Filter ............................................................... 69

Image Channel Rejection .......................................................... 69

Automatic Gain Control (AGC) ............................................... 69

RSSI .............................................................................................. 70

2FSK/GFSK/MSK/GMSK Demodulation ............................... 72

Clock Recovery ........................................................................... 73

Recommended Receiver Settings for

2FSK/GFSK/MSK/GMSK ......................................................... 73

Peripheral Features ......................................................................... 76

Analog-to-Digital Converter .................................................... 76

Data Sheet ADF7023-J

Temperature Sensor .................................................................... 76

Tes t DA C ...................................................................................... 76

Transmit Test Modes .................................................................. 76

Silicon Revision Readback ......................................................... 76

Applications Information ............................................................... 77

Application Circuit ..................................................................... 77

Host Processor Interface ............................................................ 77

PA/LNA Matching ...................................................................... 78

REVISION HISTORY

6/12—Rev. 0 to Rev. A

Changes to General Descriptions Section ...................................... 4

Changes to Calibration Time and to ADC Parameter

in Table 5 ........................................................................................... 13

Changes to Table 7 and to table summary statement and

changes to Figure 2 and Figure 3 ................................................... 15

Changes to Figure 5 and Figure 7 .................................................. 19

Changes to Figure 43 ...................................................................... 25

Changes to PHY_SLEEP Section .................................................. 27

Changes to State Transition and Command Timing Section

and changes to Ta b l e 11 .................................................................. 33

Changes to Table 12 ........................................................................ 34

Changes to Figure 49 and Figure 50 ............................................. 38

Changes to Figure 51 and Figure 52 ............................................. 39

Changes to Figure 53 ...................................................................... 41

Changes to Addressing Section ..................................................... 42

Changes to Table 20 and changes to CRC Section ...................... 43

Changes to Figure 56 ...................................................................... 44

Changes to Command Access Section ......................................... 51

Changes to Table 28 ........................................................................ 57

Changes to Figure 69 ...................................................................... 58

Changes to Table 29 ........................................................................ 62

Added Calibrating the RC Oscillator Section..............................

Command Reference ...................................................................... 80

BBRAM Register Description ................................................... 83

MCR Register Description ......................................................... 94

Packet RAM Register Description .......................................... 101

Outline Dimensions ...................................................................... 102

Ordering Guide ......................................................................... 102

Added Figure 75; Renumbered Sequentially ............................... 64

Changes to Automatic PA Ramp Section and changes to

Image Channel Rejection Section ................................................. 69

Changes to Temperature Sensor Section and changes to

Table 42 ............................................................................................. 76

Changes to Support for External PA and LNA Control

Section and changes to Table 44 .................................................... 79

Changes to Table 47 ........................................................................ 81

Changes to Table 48 ........................................................................ 82

Changes to Table 69 ........................................................................ 86

Changes to Table 70 ........................................................................ 86

Changes to Table 76 ........................................................................ 88

Changes to Table 77 and to Table 78 ............................................ 89

Changes to Table 83 and to Table 85 910Changes to Table 93 and added Table 94; Renumbered

Sequentially ...................................................................................... 92

Added Table 95 and Table 96 ........................................................ 93

Changes to Table 100 ...................................................................... 94

Changes to Table 110 ...................................................................... 96

Added Tabl e 123 and Table 124 ..................................................... 98

Changes to Table 144 .................................................................... 101

5/11—Revision 0: Initial Version

Rev. A | Page 3 of 104

ADF7023-J Data Sheet

RSSI/

LOGAMP

LNA

ADCIN_ATB3

SCLK MOSI

GPIO RE FERS TO PINS 17, 18, 19, 20, 25, AND 27.

MISO

IRQ_GP3

RFIO_1P RFIO_1N

RFO2

SPI

IRQ

CTRL

FSK ASK

DEMOD

CDR AFC AGC

4kB ROM

MAC

256 BYTE

PACKET

RAM

2kB RAM

8-BIT RIS C

PROCESSOR

BIAS

26MHz

OSC

LDO4

LDO3

LDO2

LDO1

WAKE-UP CONTROL

TIMER UNI T

64 BYTE

BBRAM

TEMP

SENSOR

BATTERY MONITOR

CLOCK

DIVIDER

GPIO

TEST

DAC

ANALOG

TEST

PA RAMP PROFILE

MUX

8-BIT

ADC

LOOP

FILTER

CHARGE

PUMP

PFD

26MHz OSC

DIVIDER

Σ-Δ

MODULATOR

GAUSSIAN

FILTER

DEV

32kHz

RCOSC

32kHz

OSC

ADF7023-J

256 BYTE

MCR RAM

GPIO

DIVIDER

XOSC26N XOSC26PXOSC32KP_GP5_ATB1XOSC32KN_ATB2RBIAS

CREGRFx

CREGVCO CREGSYNTH

CREGDIGx

09555-001

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported.

The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity.

The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the image rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the

Rev. A | Page 4 of 104

Figure 1.

calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.

The ADF7023-J operates with a power supply range of 2.2 V to

3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter a low power sleep mode in which the configuration settings are retained in the battery backup random access memory (BBRAM).

The ADF7023-J features an ultralow power, on-chip, communications processor. The communications processor, which is an 8-bit RISC processor, performs the radio control, packet management, and smart wake mode (SWM) functionality. The communications processor eases the processing burden of the companion processor by integrating the lower layers of a typical communication protocol stack. The communications processor also permits the download and execution of firmware modules. Available modules include image rejection (IR) calibration, advanced encryption standard (AES) encryption, and Reed-Solomon coding. These firmware modules are available online at ftp://ftp.analog.com/pub/RFL/FirmwareModules.

The communications processor provides a simple command-based radio control interface for the host processor. A single-byte command transitions the radio between states or performs a radio function.

The communications processor provides support for generic packet formats. The packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet profiles. In transmit mode, the communications processor can be configured to add preamble, sync word, and CRC to the payload data stored in packet RAM. In receive mode, the

Data Sheet ADF7023-J

communications processor can detect and interrupt the host processor on reception of preamble, sync word, address, and CRC and store the received payload to packet RAM. The ADF7023-J uses an efficient interrupt system comprising MAC level interrupts and PHY level interrupts that can be individually set. The payload data plus the 16-bit CRC can be encoded/decoded using Manchester or 8b/10b encoding. Alternatively, data whitening and dewhitening can be applied.

The SWM allows the ADF7023-J to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. After wake-up, the ADF7023-J is controlled by the communications processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The smart wake mode can wake the host processor on an interrupt condition. These interrupt conditions can be configured to include the reception of valid preamble, sync word, CRC, or address match. Wake -up from sleep mode can also be triggered by the host processor. For systems requiring

very accurate wake-up timing, a 32 kHz oscillator can be used to drive the wake-up timer. Alternatively, the internal RC oscillator can be used, which gives lower current consumption in sleep.

The ADF7023-J features an AES engine with hardware acceleration that provides 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits. Both electronic code book (ECB) and Cipher Block Chaining Mode 1 (CBC Mode 1) are supported. The AES engine can be used to encrypt/decrypt packet data and can be used as a standalone engine for encryption/decryption by the host processor. The AES engine is enabled on the ADF7023-J by downloading the AES firmware module to program RAM.

An on-chip, 8-bit ADC provides readback of an external analog input, the RSSI signal, or an integrated temperature sensor. An integrated battery voltage monitor raises an interrupt flag to the host processor whenever the battery voltage drops below a userdefined threshold.

Rev. A | Page 5 of 104

ADF7023-J Data Sheet

600 kHz

−116.3

dBc/Hz

130 kHz closed-loop bandwidth1

transmit, and receive, 2FSK/GFSK/MSK/GMSK

Integer Boundary Spurious3

N = 35 or 36

SPECIFICATIONS

VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, TA = T V

= 3 V and TA = 25°C.

RF AND SYNTHESIZER SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS

Frequency Range 902 958 MHz

PHASE-LOCKED LOOP

Channel Frequency Resolution 396.7 Hz Phase Noise at Offset of PA output power = 10 dBm, RF frequency = 950 MHz

800 kHz −119.4 dBc/Hz 130 kHz closed-loop bandwidth 600 kHz −113.8 dBc/Hz 223 kHz closed-loop bandwidth2 800 kHz −117.2 dBc/Hz 223 kHz closed-loop bandwidth 1 MHz −126 dBc/Hz 2 MHz −131 dBc/Hz

10 MHz −142 dBc/Hz VCO Calibration Time 142 µs Synthesizer Settling Time 56 µs Frequency synthesizer settles to within ±5 ppm of the target

to T

MIN

, unless otherwise noted. Typical specifications are at

MAX

frequency within this time following the VCO calibration,

(26 MHz × N) + 0.1 MHz −39 dBc Using 130 kHz synthesizer bandwidth, integer boundary spur at

910 MHz (26 MHz × 35), inside synthesizer loop bandwidth

(26 MHz × N) + 1.0 MHz −79 dBc Using 130 kHz synthesizer bandwidth, integer boundary spur at

910 MHz (26 MHz × 35), outside synthesizer loop bandwidth

CRYSTAL OSCILLATOR

Crystal Frequency 26 MHz Parallel load resonant crystal Recommended Load Capacitance 7 18 pF Maximum Crystal ESR 1800 Ω 26 MHz crystal with 18 pF load capacitance Pin Capacitance 2.1 pF Capacitance for XOSC26P and XOSC26N Start-Up Time 310 µs 26 MHz crystal with 7 pF load capacitance 388 µs 26 MHz crystal with 18 pF load capacitance

130 kHz closed-loop bandwidth recommended for T96/15.4 g, 50 kbps and 100 kbps data rates (see Table 31).

223 kHz closed-loop bandwidth recommended for T96/15.4 g, 200 kbps data rate (see Table 31).

As the 26 MHz XTAL is fixed, integer boundary spurs occur at 910 MHz and 936 MHz (N = 35 and N = 36).

Rev. A | Page 6 of 104

Data Sheet ADF7023-J

DATA RATE

100 kbps

28.9 dB

Modulation index = 1

Minimum Power

−20 dBm

TRANSMITTER SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

2FSK/GFSK/MSK/GMSK 1 300 kbps Data Rate Resolution 100 bps

MODULATION ERROR RATIO (MER)1 RF frequency = 957.2 MHz, GFSK

10 kbps to 49.5 kbps 25.4 dB Modulation index = 1

49.6 kbps to 129.5 kbps 25.3 dB Modulation index = 1

129.6 kbps to 179.1 kbps 23.9 dB Modulation index = 0.5

179.2 kbps to 239.9 kbps 23.3 dB Modulation index = 0.5 240 kbps to 300 kbps 23 dB Modulation index = 0.5

MODULATION ERROR RATIO 15.4 g DATA RAT ES With T96 look-up table (LUT)2

50 kbps 25.4 dB Modulation index = 1

200 kbps 25.9 dB Modulation index = 1 100 kbps 24.3 dB Modulation index = 0.5

MODULATION

2FSK/GFSK/MSK/GMSK Frequency Deviation 0.1 409.5 kHz Deviation Frequency Resolution 100 Hz Gaussian Filter Bandwidth-Time (BT) Product 0.5

SINGLE-ENDED PA

Maximum Power

Minimum Power −20 dBm Transmit Power Variation vs. Temperature ±0.5 dB From −40°C to +85°C, RF frequency =

Transmit Power Variation vs. VDD ±1 dB From 2.2 V to 3.6 V, RF frequency = 958.0 MHz Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz and 950 MHz to

Programmable Step Size

−20 dBm to +13.5 dBm 0.5 dB Programmable in 63 steps

DIFFERENTIAL PA

Maximum Power

13.5 dBm Programmable, separate PA and LNA

match

958.0 MHz

958 MHz

10 dBm Programmable

Transmit Power Variation vs. Temp erature ±1 dB From −40°C to +85°C, RF frequency =

Transmit Power Variation vs. VDD ±2 dB From 2.2 V to 3.6 V, RF frequency = 958.0 MHz Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz and 950 MHz to

Programmable Step Size

−20 dBm to +10 dBm 0.5 dB Programmable in 63 steps

958.0 MHz

958 MHz

Rev. A | Page 7 of 104

ADF7023-J Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

SPURIOUS EMISSIONS Measured as per TELEC T-245 for T96

compliance, 950 MHz to 958 MHz band, single-ended PA with combined output. For spurious emissions compliance in the

1.8845 GHz to 1.9196 GHz frequency band, a seventh-order PA harmonic filter is used.

This has an insertion loss of up to 1.5 dB. 30 MHz to 710 MHz −65 dBm/100 kHz 710 MHz to 945 MHz −63 dBm/1 MHz 945 MHz to 950 MHz −66 dBm/100 kHz 958 MHz to 960 MHz −60.7 dBm/100 kHz DR = 100 kbps, MI = 1, n = 2, fC = 957.3 MHz 960 MHz to 1 GHz −64 dBm/100 kHz 1 GHz to 1.215 GHz −72 dBm/1 MHz

1.215 GHz to 1.8845 GHz −76 dBm/1 MHz

1.8845 GHz to 1.9196 GHz5 −69 dBm/1 MHz

1.9196 GHz to 3 GHz −66 dBm/1 MHz 3 GHz to 5 GHz −69 dBm/1 MHz

OPTIMUM PA LOAD IMPEDANCE

Single-Ended PA in Transmit Mode

fRF = 915 MHz 50.8 + j10.2 Ω fRF = 954MHz 38.5 + j5.9 Ω

Single-Ended PA in Receive Mode PA Impedance in Rx mode

fRF = 915 MHz 9.4 − j124 Ω fRF = 954 MHz 8.8 − j118.5 Ω

Differential PA in Transmit Mode Load impedance between RFIO_1P and

RFIO_1N to ensure maximum output power

fRF = 915 MHz 20.5 + j36.4 Ω fRF = 954 MHz 28.1 + j17.3 Ω

MER is a measure of signal to noise ratio at optimal eye sampling point.

Optimized PLL bandwidth settings vs. data rate defined in Table 31.

Measured as the maximum unmodulated power.

A combined single-ended PA and LNA match can reduce the maximum achievable output power by up to 1 dB.

This includes the second harmonic.

Rev. A | Page 8 of 104

Data Sheet ADF7023-J

2FSK/MSK INPUT SENSITIVITY, BIT ERROR RATE (BER)

At BER = 1E − 3, RF frequency = 915 MHz,

50 kbps

−107.4

dBm

Frequency deviation = 25 kHz,

200 kbps

−99.1

dBm

Frequency deviation = 50 kHz,

RECEIVER SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LNA and PA matched separately1

1.0 kbps −116 dBm Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz

10 kbps −111 dBm Frequency deviation = 9.6 kHz,

IF filter bandwidth = 100 kHz

38.4 kbps −107.5 dBm Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz

50 kbps −106.5 dBm Frequency deviation = 12.5 kHz,

IF filter bandwidth = 100 kHz

100 kbps −105 dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

150 kbps −104 dBm Frequency deviation = 37.5 kHz,

IF filter bandwidth = 150 kHz

200 kbps −103 dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 200 kHz

300 kbps −100.5 dBm Frequency deviation = 75 kHz,

IF filter bandwidth = 300 kHz

GFSK/GMSK INPUT SENSITIVITY, BER At BER = 1E − 3, RF frequency = 954 MHz,

LNA and PA matched separately

IF filter bandwidth = 100 kHz

100 kbps −105 dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 100 kHz

100 kbps −106 dBm Frequency deviation = 40 kHz,

IF filter bandwidth = 100 kHz

200 kbps −102 dBm Frequency deviation = 100 kHz,

IF filter bandwidth = 200 kHz

200 kbps −103.3 dBm Frequency deviation = 80 kHz,

IF filter bandwidth = 200 kHz

2FSK/MSK INPUT SENSITIVITY, PACKET ERROR RATE (PER) At PER = 1%, RF frequency = 915 MHz,

LNA and PA matched separately, packet length = 128 bits, packet mode

1.0 kbps −115.5 dBm Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz

9.6 kbps −110.6 dBm Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz

38.4 kbps −106 dBm Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz

50 kbps −104.3 dBm Frequency deviation = 12.5 kHz,

IF filter bandwidth = 100 kHz

100 kbps −102.6 dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

150 kbps −101 dBm Frequency deviation = 37.5 kHz,

IF filter bandwidth = 150 kHz

IF filter bandwidth = 200 kHz

300 kbps −97.9 dBm Frequency deviation = 75 kHz,

IF filter bandwidth = 300 kHz

Rev. A | Page 9 of 104

ADF7023-J Data Sheet

SOURCE1

SOURCE2

SOURCE1

SOURCE2

DEV

Parameter Min Typ Max Unit Test Conditions/Comments

GFSK/GMSK INPUT SENSITIVITY, PER At PER = 1%, RF frequency = 954 MHz,

LNA and PA matched separately, packet length = 20 octets, packet mode

50 kbps −104.1 dBm Frequency deviation = 25 kHz,

IF filter bandwidth = 100 kHz

100 kbps −101.1 dBm Frequency deviation = 50 kHz,

IF filter bandwidth = 100 kHz

100 kbps −102.2 dBm Frequency deviation = 40 kHz,

IF filter bandwidth = 100 kHz

200 kbps −98.5 dBm Frequency deviation = 100 kHz,

IF filter bandwidth = 200 kHz

200 kbps −99.5 dBm Frequency deviation = 80 kHz,

IF filter bandwidth = 200 kHz

LNA AND MIXER, INPUT IP3 Receiver LO frequency (fLO) = 914.8 MHz,

= fLO + 0.4 MHz, f Minimum LNA Gain −11.5 dBm Maximum LNA Gain −12.2 dBm

LNA AND MIXER, INPUT IP2 Receiver LO frequency (fLO) = 920.8 MHz,

= fLO + 1.1 MHz, f Maximum LNA Gain, Maximum Mixer Gain 18.5 dBm Minimum LNA Gain, Minimum Mixer Gain 27 dBm

LNA AND MIXER, 1 dB COMPRESSION POINT RF frequency = 915 MHz

Maximum LNA Gain, Maximum Mixer Gain −21.9 dBm Minimum LNA Gain, Minimum Mixer Gain −21 dBm

ADJACENT CHANNEL REJECTION

CW Interferer Desired signal at −87 dBm, CW interferer

power level increased until BER = 62−6, image calibrated

±200 kHz Offset 38 dB IF BW = 100 kHz, wanted signal:

= 25 kHz, DR = 50 kbps

+400 kHz Offset 51 dB

−400 kHz Offset 33/39 dB Uncalibrated/internal calibration; using an IF of 200 kHz, −400 kHz is the image frequency

CO-CHANNEL REJECTION −6 dB Desired signal at −87 dBm,

data rate = 50 kbps, frequency deviation = 25 kHz, RF frequency = 954 MHz

BLOCKING

RF Frequency = 954 MHz Desired signal 3 dB above the input

sensitivity level, data rate = 50 kbps, CW interferer power level increased until BER = 10

−3

(see the Typical Performance Characteristics section for blocking at other offsets and IF bandwidths), image calibrated

±2 MHz 65 dB ±10 MHz 72 dB ±60 MHz 76 dB

IMAGE CHANNEL ATTENUATION Measured as image attenuation at the

IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth

954 MHz 36/43.8 dB Uncalibrated/calibrated

= fLO + 0.7 MHz

= fLO + 1.3 MHz

Rev. A | Page 10 of 104

Data Sheet ADF7023-J

300 kbps

24 Bits

Sync word tolerance = 1

100 kbps

52 Bits

SATURATION (MAXIMUM INPUT LEVEL)

Parameter Min Typ Max Unit Test Conditions/Comments

AFC

Accuracy 1 kHz Maximum Pull-In Range Achievable pull-in range dependent on

discriminator bandwidth and modulation 300 kHz IF Filter Bandwidth ±150 kHz 200 kHz IF Filter Bandwidth ±100 kHz 150 kHz IF Filter Bandwidth ±75 kHz 100 kHz IF Filter Bandwidth ±50 kHz

PREAMBLE LENGTH Minimum number of preamble bits to

ensure the minimum PER across the full

input power range (see Table 41)

AFC Off, AGC Lock on Sync Word Detection Sync word length 24 bits

38.4 kbps 8 Bits Sync word tolerance = 0

AFC On, AFC and AGC Lock on Preamble Detection

9.6 kbps 46 Bits

38.4 kbps 44 Bits 50 kbps 50 Bits

150 kbps 54 Bits 200 kbps 58 Bits 300 kbps 64 Bits

AFC On, AFC and AGC Lock on Sync Word Detection Sync word length 24 bits

38.4 kbps 14 Bits Sync word tolerance = 0 300 kbps 32 Bits Sync word tolerance = 1

RSSI

Range at Input −97 to −26 dBm Linearity ±2 dB Absolute Accuracy ±3 dB

2FSK/GFSK/MSK/GMSK 12 dBm

LNA INPUT IMPEDANCE

Receive Mode

fRF = 915 MHz 75.9 −

Ω

j32.3

fRF = 954 MHz 74.6 −

Ω

j32.5

Transmit Mode

fRF = 915 MHz 7.7 + j8.6 Ω fRF = 954 MHz 7.7 + j8.9 Ω

Rx SPURIOUS EMISSIONS2

Maximum < 1 GHz −66 dBm At antenna input, unfiltered conductive Maximum > 1 GHz −62 dBm At antenna input, unfiltered conductive

Sensitivity for combined matching network case is typically 1 dB less than separate matching networks.

Follow the matching and layout guidelines to achieve the relevant ARIB-T96/TELEC T-245 specifications.

Rev. A | Page 11 of 104

ADF7023-J Data Sheet

Rx AND Tx TIMING PARAMETERS

See the State Transition and Command

INH

INL

INH/IINL

LOGIC OUTPUTS

Output Low Voltage, VOL

0.1 V

Maximum Output Current

TIMING AND DIGITAL SPECIFICATIONS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

Timing section for more details

PHY_ON to PHY_RX (on CMD_PHY_RX) 300 µs Includes VCO calibration and synthesizer

settling

PHY_ON to PHY_TX (on CMD_PHY_TX) 296 µs Includes VCO calibration and synthesizer

settling, does not include PA ramp-up

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, CIN 10 pF

Output High Voltage, VOH VDD − 0.4 V IOH = 500 µA Output Low Voltage, VOL 0.4 V IOL = 500 µA GPIO Rise/Fall 5 ns GPIO Load 10 pF Maximum Output Current 5 mA

ATB OUTPUTS Used for external PA and LNA control

ADCIN_ATB3 and ATB4

Output High Voltage, VOH 1.8 V

0.7 × VDD V

0.2 × V

±1 µA

Maximum Output Current 0.5 mA

XOSC32KP_GP5_ATB1 and XOSC32KN_ATB2

Output High Voltage, VOH VDD V Output Low Voltage, VOL 0.1 V

Rev. A | Page 12 of 104

Data Sheet ADF7023-J

32 kHz RC OSCILLATOR

Hardware Timer

(calibrated at +25°C)

±3 °C

Overtemperature range −12°C to +79°C

AUXILARY BLOCK SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

Frequency 32.768 kHz After calibration Frequency Accuracy 1.5 % After calibration at 25°C Frequency Drift

Temperature Coefficient 0.14 %/°C Voltage Coefficient 4 %/V

Calibration Time 1.25 ms

32 kHz XTAL OSCILLATOR

Frequency 32.768 kHz Start-Up Time 630 ms 32.768 kHz crystal with 7 pF load capacitance

WAKE UP CONTROLLER (WUC)

Wake-Up Period 61 × 10−6 1.31 × 105 sec

Firmware Timer

Wake-Up Period 1 216 Hardware

periods

ADC Maximum input voltage at ADCIN_ATB3 is 1.8 V

Resolution 8 Bits DNL ±1 LSB VDD from 2.2 V to 3.6 V, TA = 25°C INL ±1 LSB VDD from 2.2 V to 3.6 V, TA = 25°C Conversion Time 1 Input Capacitance 12.4 pF

BATTERY MONITOR

Absolute Accuracy ±45 mV Alarm Voltage Setpoint 1.7 2.7 V Alarm Voltage Step Size 62 mV 5-bit resolution Start-Up Time 100 µs

Current Consumption 30 µA When enabled

TEMPERATURE SENSOR

Range −40 +85 °C Resolution 0.3 °C With averaging

Accuracy of Single Temperature

Readback

±4 °C Overtemperature range −36°C to +84°C

+7/−4 °C Overtemperature range −40°C to +85°C

µs

Firmware counter counts of the number of hardware wake-ups, resolution of 16 bits

(calibrated at +25°C)

Rev. A | Page 13 of 104

ADF7023-J Data Sheet

TEMPERATURE RANGE, TA

−40 +85

°C

Differential PA, 915 MHz

PHY_OFF

Device in PHY_OFF state, 26 MHz oscillator running, digital

GENERAL SPECIFICATIONS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

VOLTAGE SUPPLY

VDD 2.2 3.6 V Applied to VDDBAT1 and VDDBAT2

TRANSMIT CURRENT CONSUMPTION

Single-Ended PA, 915 MHz

−10 dBm 10.3 mA 0 dBm 13.3 mA 10 dBm 24.1 mA

13.5 dBm 32.1 mA

−10 dBm 9.3 mA 0 dBm 12 mA 5 dBm 16.7 mA 10 dBm 28 mA

POWER MODES

PHY_SLEEP (Deep Sleep Mode 2) 0.18 µA Sleep mode, wake-up configuration values (BBRAM) not

PHY_SLEEP (Deep Sleep Mode 1) 0.33 µA Sleep mode, wake-up configuration values (BBRAM)

PHY_SLEEP (RCO Wake Mode)

PHY_SLEEP (XTO Wake Mode) 1.28 µA WUC active, 32 kHz crystal running, wake-up configuration

0.75 µA WUC active, RC oscillator running, wake-up configuration

In the PHY_TX state, single-ended PA matched to 50 Ω,

differential PA matched to 100 Ω, separate single-ended PA and LNA match, combined differential PA and LNA match

retained

values retained (BBRAM)

and synthesizer regulators active, all register values retained

PHY_ON 1 mA Device in PHY_ON state, 26 MHz oscillator running, digital,

synthesizer, VCO, and RF regulators active, baseband filter

calibration performed, all register values retained PHY_RX (ADC, AGC Off ) 11.9 mA Device in PHY_Rx state, ADC off, manual AGC gain PHY_RX (ADC, AGC On) 12.8 mA Device in PHY_RX state

SMART WAKE MODE Average current consumption

21.78 µA Autonomous reception every 1 sec, with receive dwell time of 1.25 ms, using RC oscillator, data rate = 38.4 kbps

11.75 µA Autonomous reception every 1 sec, with receive dwell time of 0.5 ms, using RC oscillator, data rate = 300 kbps

Rev. A | Page 14 of 104

Data Sheet ADF7023-J

t7 5 ns min

MOSI to SCLK rising edge setup time

t13

ns max

SCLK rise time

t4t

SCLK

MISO

MOSI

7 76 5 4 3 2 1 0 7

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X BIT 7

09555-002

SPI STATE

SCLK

MISO

SLEEP WAKE UP SPI READY

012345

09555-003

TIMING SPECIFICATIONS

VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, V

Table 7. SPI Interface Timing

Parameter Limit Unit Test Conditions/Comments

t2 85 ns min t3 85 ns min SCLK high time t4 85 ns min SCLK low time

t5 170 ns min SCLK period t6 10 ns max SCLK falling edge to MISO delay

t8 5 ns min MOSI to SCLK rising edge hold time t9 85 ns min SCLK falling edge to CS hold time

t11 270 ns min t12 310 µs typ

t14 20 ns max SCLK fall time

Timing Diagrams

= GND = 0 V, TA = T

GND

low to SCLK setup time

high time

low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, T

MIN

to T

, unless otherwise noted.

MAX

= 25°C

Figure 2. SPI Interface Timing

Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of

Rev. A | Page 15 of 104

)

ADF7023-J Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Connect the exposed paddle of the LFCSP package to ground.

Table 8.

Parameter Rating

VDDBAT1, VDDBAT2 to GND −0.3 V to +3.96 V Operating Temperature Range

Industrial −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance 26°C/W Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance, RF integrated circuit with an ESD rating of <2 kV; it is ESD sensitive. Take proper precautions for handling and assembly.

ESD CAUTION

Rev. A | Page 16 of 104

Data Sheet ADF7023-J

NOTES

1. NC = NO CONNECT. DO NOT CONNECT T O THIS PIN.

2. CONNECT E X P OSED PAD TO GND.

MOSI

SCLK

MISO

IRQ_GP3

GP2

GP1

1 2 3 4 5 6 7 8

CREGRF1

RBIAS

CREGRF2

RFIO_1P RFIO_1N

RFO2

VDDBAT2

10111213141516

CREGVCO

VCOGUARD

CREGSYNTH

CWAKEUP

XOSC26P

XOSC26N

DGUARD

CREGDIG1

32313029282726

ADCVREF

ATB4

ADCIN_ATB3

VDDBAT1

XOSC32KN_ATB2

XOSC32KP_GP5_ATB1

CREGDIG2

GP4

TOP VIEW

(Not to S cale)

ADF7023-J

EPAD

09555-004

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Description

1 CREGRF1 Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 2 RBIAS External Bias Resistor. A 36 kΩ resistor with 2% tolerance should be used. 3 CREGRF2 Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 4 RFIO_1P LNA Positive Input in Receive Mode. PA p ositive output in transmit mode with differential PA. 5 RFIO_1N LNA Negative Input in Receive Mode. PA negative output in transmit mode with differential PA. 6 RFO2 Single-Ended PA Output. 7 VDDBAT2 Power Supply Pin Two. Decoupling capacitors to the ground plane should be placed as close as

possible to this pin. 8 NC No Connect. 9 CREGVCO Regulator Voltage for the VCO. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 10 VCOGUARD Guard/Screen for VCO. This pin should be connected to Pin 9. 11 CREGSYNTH Regulator Voltage for the Synthesizer. A 220 nF capacitor should be placed between this pin and

ground for regulator stability and noise rejection. 12 CWAKEUP External Capacitor for Wake-Up Control. A 150 nF capacitor should be placed between this pin and

ground. 13 XOSC26P The 26 MHz reference crystal should be connected between this pin and XOSC26N. 14 XOSC26N The 26 MHz reference crystal should be connected between this pin and XOSC26P. 15 DGUARD Internal Guard/Screen for the Digital Circuitry. A 220 nF capacitor should be placed between this pin

and ground. 16 CREGDIG1 Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

17 GP0 Digital GPIO Pin 0. 18 GP1 Digital GPIO Pin 1. 19 GP2 Digital GPIO Pin 2. 20 IRQ_GP3 Interrupt Request, Digital GPIO Test Pin 3. An RC filter should be placed between this pin and the

pin and ground for regulator stability and noise rejection. This can be achieved by shorting it to

Pin 15 and sharing the capacitor to ground.

host processor. Recommended values are R = 1.1 kΩ and C = 1.5 nF.

Rev. A | Page 17 of 104

ADF7023-J Data Sheet

Pin No. Mnemonic Description

21 MISO Serial Port Master In/Slave Out. 22 SCLK Serial Port Clock. 23 MOSI Serial Port Master Out/Slave In. 24

25 GP4 Digital GPIO Test Pin 4. 26 CREGDIG2 Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

27 XOSC32KP_GP5_ATB1 Digital GPIO Test Pin 5. A 32 kHz watch crystal can be connected between this pin and

28 XOSC32KN_ATB2 A 32 kHz watch crystal can be connected between this pin and XOSC32KP_GP5_ATB1. Analog Test

29 VDDBAT1 Digital Power Supply Pin One. Decoupling capacitors to the ground plane should be placed as close

30 ADCIN_ATB3 Analog-to-Digital Converter Input. Can be configured as an external PA enable signal. Analog Test

31 ATB4 Analog Test Pin 4. Can be configured as an external LNA enable signal. 32 ADCVREF ADC Reference Output. A 220 nF capacitor should be placed between this pin and ground for

EPAD The exposed package paddle must be connected to GND.

Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host

processor from inadvertently waking the ADF7023-J from sleep.

pin and ground for regulator stability and noise rejection.

XOSC32KN_ATB2. Analog Test Pin 1.

Pin 2.

as possible to this pin.

Pin 3.

adequate noise rejection.

Rev. A | Page 18 of 104

Data Sheet ADF7023-J

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64

OUTPUT P OWER (dBm)

PA_LEVEL_MCR

09555-205

–20

–16

–12

–8

–4

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V –40°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V

–18

–16

–14

–12

–10

–8–6–4

–2

02468

101214

UPPLY CURRENT ( mA)

OUTPUT P OWER (dBm)

–40°C, 3.6V –40°C, 1.8V +85°C, 3.6V +85°C, 1.8V

09555-206

–20

–18

–16

–14

–12

–10

–8

–6

–4

–2

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64

OUTPUT P OWER (dBm)

PA_LEVEL_MCR

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V –40°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V

09555-209

–18

–16

–14

–12

–10

–8–6–4

–2

SUPPLY CURRENT (mA)

OUTPUT P OWER (dBm)

–40°C, 3.6V –40°C, 1.8V +85°C, 3.6V +85°C, 1.8V

09555-210

–60

–50

–40

–30

–20

–10

0 50 100 150 200 250 300 350 400 450 500

PA OUTPUT P OWER (dBm)

TIME (µs)

PA RAMP = 1 PA RAMP = 2 PA RAMP = 3 PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

09555-211

–60

–50

–40

–30

–20

–10

0 50 100 150 200 250 300 350 400 450 500

PA OUTPUT P OWER (dBm)

TIME (µs)

PA RAMP = 1 PA RAMP = 2 PA RAMP = 3 PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

09555-212

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Single-Ended PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

1.8 V Operation Shown for Robustness)

(Minimum Recommended VDD = 2.2 V,

Figure 8. Differential PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V

(Minimum Recommended VDD = 2.2 V, 1.8 V Operation

Shown for Robustness)

Figure 6. Single-Ended PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V

Figure 7. Differential PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

(Minimum Recommended VDD = 2.2 V, 1.8 V Operation

Shown for Robustness)

1.8 V Operation Shown for Robustness)

(Minimum Recommended VDD = 2.2 V,

Figure 9. PA Ramp-Up at Data Rate = 38.4 kbps for

Each PA_RAMP Setting, Differential PA

Figure 10. PA Ramp-Down at Data Rate = 38.4 kbps for

Each PA_RAMP Setting, Differential PA

Rev. A | Page 19 of 104

ADF7023-J Data Sheet

–60

–50

–40

–30

–20

–10

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

PA OUTPUT P OWER (dBm)

TIME (µs)

PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

09555-213

–60

–50

–40

–30

–20

–10

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

PA OUTPUT P OWER (dBm)

TIME (µs)

PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

09555-214

–45

–40

–35

–30

–25

–20

–15

–10

–5

–1000

–900

–800

–700

–600

–500

–400

–300

–200

–100

100

200

300

400

500

600

700

800

900

1000

POWER (dBm)

FREQUENCY OFFSET (kHz)

3.6V, +25° C

1.8V, +85° C

3.6V, –40°C

1.8V, –40°C

3.6V, +85° C

1.8V, +25° C

09555-217

–40

–35

–30

–25

–20

–15

–10

–5

–40 –35 –30 –25 –20 –15

MIXER OUTPUT POWER (dBm)

LNA INPUT P OWER (dBm)

OUTPUT P OWER (FUNDAME NTAL) OUTPUT P OWER IDEAL P1dB

P1dB = –21dBm

09555-225

OUTPUT P OWER (FUNDAME NTAL) OUTPUT P OWER IDEAL P1dB

–10

–5

–40 –35 –30 –25 –20 –15

MIXER OUTPUT POWER (dBm)

LNA INPUT P OWER (dBm)

P1dB = –21.9dBm

09555-226

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

–50 –45 –40 –35 –30 –25 –20 –15 –10

MIXER OUTPUT POWER (dBm)

LNA INPUT P OWER (dBm)

FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT IM3 3/1 SLOPE FIT

IIP3 = –11.5dBm

09555-227

Figure 11. PA Ramp-Up at Data Rate = 300 kbps for

Each PA_RAMP Setting, Differential PA

Figure 12. PA Ramp-Down at Data Rate = 300 kbps for

Each PA_RAMP Setting, Differential PA

Figure 14. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature =

25°C, RF Frequency = 915 MHz, LNA Gain = Low, Mixer Gain = Low

Figure 15. LNA/Mixer 1 dB Compression Point, V

25°C, RF Frequency = 915 MHz, LNA Gain = High, Mixer Gain = High

= 3.0 V, Temperature =

Figure 13. Transmit Spectrum at 928 MHz, GFSK, Data Rate = 300 kbps,

Frequency Deviation = 75 kHz (Minimum Recommended V

Operation Shown for Robustness)

= 2.2 V, 1.8 V

Rev. A | Page 20 of 104

Figure 16. LNA/Mixer IIP3, V

915 MHz, LNA Gain = Low, Mixer Gain = Low, Source 1 Frequency =

= 3.0 V, Temperature = 25°C, RF Frequency =

(915 + 0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

Data Sheet ADF7023-J

–90

–80

–70

–60

–50

–40

–30

–20

–10

–50 –45 –40 –35 –30 –25 –20 –15 –10

MIXER OUTPUT POWER (dBm)

LNA INPUT P OWER (dBm)

IIP3 = –12.2dBm

FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT IM3 3/1 SLOPE FIT

09555-228

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

ATTENUATION (dB)

FREQUENCY OFFSET (MHz)

100kHz 150kHz 200kHz 300kHz

09555-229

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

ATTENUATION (dB)

FREQUENCY OFFSET (MHz)

3.6V, +85° C

1.8V, –40°C

2.4V, –40°C

3.0V, –40°C

3.6V, –40°C

1.8V, +25° C

2.4V, +25° C

3.0V, +25° C

3.6V, +25° C

1.8V, +85° C

2.4V, +85° C

3.0V, +85° C

09555-230

–10

–11

–10

–9–8–7–6–5–4–3–2–1

012345678

BLOCKING ( dB)

MODULATED INTERFERER

CARRIER WAVE INTERFERER

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

09555-237

–20

–10

–9–8–7–6–5–4–3–2–1

012345678

OCKING (dB)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

MODULATED INTERFERER

CARRIER WAVE INTERFERER

09555-238

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

–10

–20

–11

–10

–9–8–7–6–5–4–3–2–1

012345678

BLOCKING ( dB)

MODULATED INTERFERER

CARRIER WAVE INTERFERER

09555-239

Figure 17. LNA/Mixer IIP3, V

RF Frequency = 915 MHz, LNA Gain = High, Mixer Gain = High,

= 3.0 V, Temperature = 25°C,

Source 1 Frequency = (915 + 0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

Figure 18. IF Filter Profile vs. IF Bandwidth, V

= 3.0 V, Temperature = 25°C

Figure 20. Receiver Wideband Blocking at 915 MHz, Data Rate = 38.4 kbps

Figure 21. Receiver Wideband Blocking at 915 MHz, Data Rate = 100 kbps

Figure 19. IF Filter Profile vs. V

Bandwidth (Minimum Recom mended V

1.8 V Operation Shown for Robustness)

and Temperature, 100 kHz IF Filter

Figure 22. Receiver Wideband Blocking at 915 MHz, Data Rate = 300 kbps

= 2.2 V,

Rev. A | Page 21 of 104

ADF7023-J Data Sheet

–10

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60

BLOCKING ( dB)

BLOCKER FRE QUENCY OFF S E T (MHz)

09555-240

25°C, 3.0V

–10

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

BLOCKING ( dB)

BLOCKER FRE QUENCY OFF S E T (MHz)

09555-242

25°C, 3.0V

–20

–10

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

BLOCKING ( dB)

BLOCKER FRE QUENCY OFF S E T (MHz)

09555-243

25°C, 3.0V

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

–20

–15

–10

–5

BLOCKING ( dB)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

CW INTERFERER MODULATE D INTERFERER

–0.8 –0.4

09555-244

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

–20

–15

–10

–5

BLOCKING ( dB)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

CW INTERFERER MODULATE D INTERFERER

–0.8 –0.4

09555-245

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

–20

–15

–10

–5

BLOCKING ( dB)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

CW INTERFERER MODULATE D INTERFERER

–0.8 –0.4

09555-246

Figure 23. Receiver Wideband Blocking at 954 MHz, Data Rate = 50 kbps,

Frequency Deviation = 25 kHz, Carrier Wave Interferer, P

WANTED

= P

SENS

+ 3 dB

Figure 24. Receiver Close-In Blocking at 954 MHz, Data Rate = 50 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated, CW Interferer, P

+ 3 dB

SENS

WANTED

Figure 26. Receiver Close-In Blocking at 915 MHz, Data Rate = 150 kbps,

IF Filter Bandwidth = 150 kHz, Image Calibrated

Figure 27. Receiver Close-In Blocking at 915 MHz, Data Rate = 200 kbps,

IF Filter Bandwidth = 200 kHz, Image Calibrated

Figure 25. Receiver Close-In Blocking at 954 MHz, Data Rate = 100 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated, CW Interferer, P

+ 3 dB

SENS

Figure 28. Receiver Close-In Blocking at 915 MHz, Data Rate = 300 kbps,

WANTED

IF Filter Bandwidth = 300 kHz, Image Calibrated

Rev. A | Page 22 of 104

Data Sheet ADF7023-J

–90

–80

–70

–60

–50

–40

–30

–20

–10

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

ATTENUATION (dB)

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

CALIBRATED UNCALIBRATED

09555-247

–90

–80

–70

–60

–50

–40

–30

–20

–10

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

ATTENUATION (dB)

OFFSET FROM LO FREQUENCY (MHz)

100kHz BW 150kHz BW 200kHz BW 300kHz BW

09555-249

–104

–103

–102

–101

–100

–99

–98

1.8 3.0 3.6

SENSITIVITY (dBm)

VDD (V)

915MHz, –40°C 915MHz, +25°C 915MHz, +85°C

09555-250

–120

–115

–110

–105

–100

–95

0 50 100 150 200 250 300

SENSITIVITY (dBm)

DATA RATE (kb ps)

BIT ERROR RATE (1E-3) PACKET ERROR RATE (1%)

09555-251

100

PACKET ERROR RAT E ( %)

APPLIED RECEIVER POWER (dBm)

1kbps 10kbps

38.4kbps 50kbps 100kbps 200kbps 300kbps

–120 –110 –100 –90 –80 –70 –60 –50 0–10–40 –30 –20

09555-252

–100.0

–99.5

–99.0

–98.5

–98.0

–97.5

–97.0

–96.

–96.0

1.8 3.6

SENSITIVITY (dBm)

VDD (V)

–40°C

+25°C

+85°C

09555-254

Figure 29. Image Attenuation with Calibrated and Uncalibrated Images, 915 MHz, IF Filter Bandwidth = 100 kHz, V

= 3.0 V, Temperature = 25°C

Figure 30. IF Filter Profile with Calibrated Image vs. IF Filter Bandwidth,

921 MHz, V

= 3.0 V, Temperature = 25°C

Figure 32. Bit Error Rate Sensitivity (at BER = 1E − 3) and Packet Error Rate

Sensitivity (at PER = 1%) vs. Data Rate, GFSK, V

Temperature = 25°C

= 3.0 V,

Figure 33. Packet Error Rate vs. RF Input Power and Data Rate, FSK/GFSK,

928 MHz, Preamble Length = 64 Bits, V

= 3.0 V, Temperature = 25°C

Figure 31. Receiver Sensitivity (Bit Error Rate at 1E − 3) vs. VDD, Temperature,

and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency Deviation =

75 kHz, IF Bandwidth = 300 kHz

Figure 34. Receiver Sensitivity (Packet Error Rate at 1%) vs. VDD,

Temperature, and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency

Deviation = 75 kHz, IF Bandwidth = 300 kHz

Rev. A | Page 23 of 104

ADF7023-J Data Sheet

09555-339

–107 –106 –105 –104 –103 –102 –101 –100 –99

PACKET ERROR RATE (%)

Rx INPUT PO WER (dBm)

CODED, PM L = 0x0A, SYNC. TOL. = 0

UNCODED, PM L = 0x0A, SYNC. TOL. = 0

CODED, PM L = 0x0A, SYNC. TOL. = 1

CODED, PML = 0x07, SYNC. TOL. = 2

2.1dB

3.5dB

4.1dB

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

–150

150

140

130

120

110

100

908070605040302010

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

SENSITIVITY (dBm)

RF FREQUE NCY E RROR (kHz)

100kbps 150kbps 200kbps 300kbps

09555-259

2.00

–2.00

–1.75

–1.

–1.25

–1.00

–0.75

–0.50

–0.25

0.25

0.50

0.75

1.00

1.25

1.50

1.75

DATA RATE ERRO R ( %)

–40 –30 –20 –10 0 10 20 30–35 –25 –15 –5 5 15 25 35 40

RF FREQUE NCY E RROR (kHz)

>1% <1%

09555-260

2.00

–2.00

–1.75

–1.50

–1.25

–1.00

–0.75

–0.50

–0.25

0.25

0.50

0.75

1.00

1.25

1.50

1.75

DATA RATE ERRO R ( %)

–140–120–100 –80 –60 –40 –20 0 20 40 60 80 100 120 140

RF FREQUE NCY E RROR (kHz)

>1%

<1%

09555-261

–20

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–10

–8

–6

–4

–2

RSSI (dBm)

RSSI ERROR ( dB)

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT PO WER (dBm)

IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR

09555-262

–20

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–10

–8

–6

–4

–2

RSSI (dBm)

RSSI ERROR ( dB)

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT PO WER (dBm)

IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR

09555-263

Figure 35. Receiver PER Using Reed Solomon (RS) Coding; RF Frequency =

928 MHz, GFSK, Data Rate = 100 kbps, Frequency Deviation = 50 kHz, Packet

Length = 28 Bytes (Uncoded); Reed Solomon Configuration: n = 38,

k = 28, t = 5, PML = Preamble Match Level Register

Figure 36. AFC On: Receiver Sensitivity (at PER = 1%) vs. RF Frequency Error,

GFSK, 915 MHz, AFC Enabled (Ki = 7, Kp = 3), AFC Mode = Lock After

Preamble, IF Bandwidth = 100 kHz (at 100 kbps), 150 kHz (at 150 kbps),

200 kHz (at 200 kbps), and 30 0 kHz (at 300 kbps), Preamble Length = 64 Bits

Figure 38. AFC On: Packet Error Rate vs. RF Frequency Error and Data Rate

Error, AFC On, Data Rate = 300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

Figure 39. RSSI (via CMD_GET_RSSI) vs. RF Input Power, 950 MHz, GFSK, Data

Rate = 38.4 kbps, Frequency Deviation = 20 kHz, IF Bandwidth = 100 kHz,

100 RSSI Measurements at Each Input Power Level

Figure 37. AFC Off: Packet Error Rate vs. RF Frequency Error and Data Rate Error, AFC Off, Data Rate = 300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

Figure 40. RSSI (via Automatic End of Packet RSSI Measurement) vs. RF Input

Power, 950 MHz, GFSK, Data Rate = 300 kbps, Frequency Deviation = 75 kHz,

IF Bandwidth = 300 kHz, AGC_CLOCK_DIVIDE = 15, 100 RSSI Measurements

at Each Input Power Level

Rev. A | Page 24 of 104

Data Sheet ADF7023-J

–6

–4

–2

RSSI ERROR ( dB)

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT PO WER (dBm)

300kbps 200kbps 150kbps 100kbps 50kbps

38.4kbps

9.6kbps

09555-264

–20

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–10

–8

–6

–4

–2

RSSI (dBm)

RSSI ERROR ( dB)

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT PO WER (dBm)

IDEAL RSSI MEAN RSSI MEAN RSSI

(WITH POLYNOMIAL CORRECTION)

MEAN RSSI ERROR MEAN RSSI ERROR

(WITH POLYNOMIAL CORRECTION)

09555-265

–40

–30

–20

–10

TEMPERATURE CALCULATED FROM SENSOR (°C)

–40 –30 –20 –10 0 10 20 30 40 50 60 8070

TEMPERATURE (°C)

09555-347

ERROR (°C)

MEAN (°C)

–1

RECEIVER SYMBOL LEVEL

0 1 2 3 4 5 6 7 8 9

SAMPLE NUMBER

09555-269

–90 –91 –92 –93 –94 –95 –96 –97 –98

–99 –100 –101 –102 –103 –104 –105 –106 –107 –108 –109 –110

220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20

SENSITIVITY POINT (dBm)

DISCRIMI NATOR BANDWIDT H ( kHz )

0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0

MODULATION INDEX

09555-349

IFBW = 100kHz IFBW = 200kHz DISC BW (kHz)

–90

–91

–92

–93

–94

–95

–96

–97

–98

–99 –100 –101 –102 –103 –104 –105 –106 –107 –108 –109 –110

220

230

240

210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40

SENSITIVITY POINT (dBm)

DISCRIMI NATOR BANDWIDT H ( kHz )

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

MODULATION INDEX

09555-350

IFBW = 100kHz IFBW = 200kHz DISC BW (kHz)

Figure 41. Mean RSSI Error (via Automatic End of Packet RSSI Measurement)

vs. RF Input Power vs. Data Rate; RF Frequency = 950 MHz, GFSK, 100 RSSI

Measurements at Each Input Power Level

Figure 42. RSSI With and Without Cosine Polynomial Correction (via

Automatic End of Packet RSSI Measurement), 100 RSSI Measurements at

Each Input Power Level

Figure 44. Receiver Eye Diagram Measured Using the Test DAC,

RF Frequency = 915 MHz, RF Input Power = −80 dBm, Data Rate = 100 kbps, Frequency Deviation = 50 kHz

Figure 45. Rx Sensitivity vs. Modulation Index, Data Rate = 50 kbps,

MOD = GFSK, F

= ±(MI × 2 5 kHz), Data = PRBS9, BER = 1E − 3,

DEV

Bits = 1E + 6, V

= 3.0 V, Temperature = 25°C

BAT

Figure 43. Temperature Sensor Readback vs. Die Temperature, Readback

Value Converted to °C via Formula in the Temperature Sensor Section

Figure 46. Rx Sensitivity vs. Modulation Index, Data Rate = 100 kbps,

MOD = GFSK (0.5), F

Bits = 2E + 5, V

Rev. A | Page 25 of 104

= ±(MI × 50 kHz), Data = PRBS9, BER = 1E − 3,

DEV

= 3.0 V, Temperature = 25°C

BAT

ADF7023-J Data Sheet

TERMINOLOGY

ADC

Analog-to-digital converter

AGC

Automatic gain control

AFC

Automatic frequency control

Battmon

Battery monitor

BBRAM

Battery backup random access memory

CBC

Cipher block chaining

CRC

Cyclic redundancy check

Data rate

ECB

Electronic code book

ECC

Error checking code

2FSK

Two -level frequency shift keying

GFSK

Two -level Gaussian frequency shift keying

GMSK

Gaussian minimum shift keying, GFSK with modulation index = 0.5

Local oscillator

MAC

Media access control

MCR

Modem configuration random access memory

MER

Modulation error ratio

MSK

Minimum shift keying, 2FSK with modulation index = 0.5

NOP

No operation

Power amplifier

PFD

Phase frequency detector

PHY

Physical layer

RCO

RC oscillator

RISC

Reduced instruction set computer

RSSI

Receive signal strength indicator

Receive

SAR

Successive approximation register

SWM

Smart wake mode

Transmit

VCO

Volt a ge c ontrolled oscillator

WUC

Wake -up controller

XOSC

Crystal oscillator

Rev. A | Page 26 of 104

Data Sheet ADF7023-J

issuing CMD_HW_RESET

RADIO CONTROL

The ADF7023-J has five radio states designated PHY_SLEEP, PHY_OFF, PHY_ON, PHY_TX, and PHY_RX. The host processor can transition the ADF7023-J between states by issuing single

byte commands over the SPI interface. The various commands and states are illustrated in Figure 47. The communications processor handles the sequencing of various radio circuits and critical timing functions, thereby simplifying radio operation and easing the burden on the host processor.

RADIO STATES

PHY_SLEEP

In this state, the device is in a low power sleep mode. To enter the state, issue the CMD_PHY_SLEEP command, either from the PHY_OFF or PHY_ON state. To wake the radio from the state, set the RC or 32.768 kHz crystal) to wake the radio from this state. The wake-up timer should be set up before entering the PHY_SLEEP state. If retention of BBRAM contents is not required, Deep

Sleep Mode 2 can be used to further reduce the PHY_SLEEP

state current consumption. Deep Sleep Mode 2 is entered by

issuing the CMD_HW_RESET command. The options for

the PHY_SLEEP state are detailed in Table 10. When in

PHY_SLEEP, the IRQ_GP3 interrupt pin is held at logic low

while the other GPIO pins are in a high impedance state.

PHY_OFF

In the PHY_OFF state, the 26 MHz crystal, the digital regulator, and the synthesizer regulator are powered up. All memories are fully accessible. The BBRAM registers must be valid before exiting this state.

PHY_ON

In the PHY_ON state, along with the crystal, the digital regulator, the synthesizer regulator, the VCO, and the RF regulators are

powered up. A baseband filter calibration is performed when

this state is entered from the PHY_OFF state if the BB_CAL bit

in the MODE_CONTROL register (Address 0x11A) is set. The

pin low or use the wake-up controller (32.768 kHz

device is ready to operate, and the PHY_TX and PHY_RX states can be entered.

PHY_TX

In the PHY_TX state, the synthesizer is enabled and calibrated. The power amplifier is enabled, and the device transmits at the channel frequency defined by the CHANNEL_FREQ[23:0] setting (Address 0x109 to Address 0x10B). The state is entered by issuing the CMD_PHY_TX command. The device automatically transmits the transmit packet stored in the packet RAM. After transmission of the packet, the PA is disabled, and the device automatically returns to the PHY_ON state and can, optionally, generate an interrupt.

In sport mode, the device transmits the data present on the GP2 pin as described in the Sport Mode section. The host processor must issue the CMD_PHY_ON command to exit the PHY_TX state when in sport mode.

PHY_RX

In the PHY_RX state, the synthesizer is enabled and calibrated. The ADC, RSSI, IF filter, mixer, and LNA are enabled. The radio is in receive mode on the channel frequency defined by the CHANNEL_FREQ[23:0] setting (Address 0x109 to Address 0x10B).

After reception of a valid packet, the device returns to the PHY_ON state and can, optionally, generate an interrupt. In sport mode, the device remains in the PHY_RX state until the CMD_PHY_ON command is issued.

Current Consumption

The typical current consumption in each state is detailed in Table 10.

Table 10. Current Consumption in ADF7023-J Radio States

State Current (Typical) Conditions

PHY_SLEEP (Deep Sleep Mode 2) 0.18 µA Wake-up timer off, BBRAM contents not retained, entered by

PHY_SLEEP (Deep Sleep Mode 1) 0.33 µA Wake-up timer off, BBRAM contents retained PHY_SLEEP (RCO Mode ) 0.75 µA Wake-up timer on using a 32 kHz RC oscillator, BBRAM contents retained PHY_SLEEP (XTO Mode ) 1.28 µA Wake-up timer on using a 32 kHz XTAL oscillator, BBRAM contents retained PHY_OFF 1.0 mA PHY_ON 1.0 mA PHY_TX 24.1 mA 10 dBm, single-ended PA, 950 MHz PHY_RX 12.8 mA

Rev. A | Page 27 of 104

ADF7023-J Data Sheet

CONFIGURE

PROGRAM RAM

CONFIG

AES

IR CALIBRAT ION

REED-SOLOMON

IF FILTER CAL

CONFIGURE

MEASURE RSSI

RX_TO_TX_AUTO_TURNAROUND

TX_TO_RX_AUTO_TURNAROUND

CMD_PHY_TX

CMD_PHY_RX

CMD_PHY_SLEEP

CMD_PHY_ON

CMD_PHY_OFF

CMD_PHY_RX

COLD START

(BATTERY APPLIED)

CMD_CONFIG_DEV

CMD_RAM_LOAD_INIT

CMD_RAM_LOAD_DONE

CMD_AES

CMD_IR_CAL

CMD_AES

CS LOW

WUC TIME OUT

CMD_PHY_SLEEP

CMD_HW_RESET (FROM ANY STATE)

PHY_ON

PHY_TX PHY_RX

CMD_PHY_RXCMD_PHY_TX

TX_EOF

RX_EOF

PHY_OFF PHY_SLEEP

CMD_RS

CMD_CONFIG_DEV

CMD_BB_CAL

CMD_GET_RSSI

PROGRAM RAM

TRANSMIT AND RE CE IVE AUTOMATIC TURNAROUND M US T BE ENABLED BY BITS RX_TO_TX_AUTO _TURNAROUND AND

TX_TO_RX _AUTO_TURNAROUND (0x11A: M ODE_CONTRO L).

AES ENCRYPTION/DECRYPTION, IMAGE REJECTION CALIBRATION, AND REED SOL OMON CODI NG ARE AVAILABLE ONLY I F THE NECESS ARY

FIRMWARE M ODULE HAS BEEN DO WNLOADED T O THE PROGRAM RAM.

THE END OF FRAME (EOF ) AUTOMATI C TRANSITI ONS ARE DISABL E D IN SPORT M ODE.

CMD_AES REFERS TO THE THRE E AV AILABLE AES COMMANDS: CMD_AES _E NCRY P T, CMD_AES_DECRY P T, AND CMD_AES_DECRY P T_INIT.

CMD_RS REFERS TO THE THRE E AV AILABLE REE D S OLOMO N COMMANDS: CMD_RS_E NCODE_INIT , CMD_RS_ENCODE,

AND CMD_RS_DECODE.

KEY

TRANSITION INITIATED BY HOST PROCESSOR AUTOMATIC TRANSITION BY COMM UNICATIONS P ROCESSOR COMMUNICAT IONS PROCES S OR FUNCTION

DOWNLO ADABLE FIRMW ARE M ODULE STORED ON PROGRAM RAM

RADIO STATE

09555-121

Figure 47. Radio State Diagram

Rev. A | Page 28 of 104

Data Sheet ADF7023-J

INITIALIZATION

Initialization After Application of Power

When power is applied to the ADF7023-J (through the VDDBAT1/VDDBAT2 pins), it registers a power-on reset (POR) event and transitions to the PHY_OFF state. The BBRAM memory is unknown, the packet RAM memory is cleared to 0x00, and the MCR memory is reset to its default values. The host processor should use the following procedure to complete the initialization sequence:

1. Bring the

output goes high.

2. Issue the CMD_SYNC command.

3. Wait for the CMD_READY bit in the status word to go high.

4. Configure the part by writing to all 64 of the BBRAM

registers.

5. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

The ADF7023-J is now configured in the PHY_OFF state.

pin of the SPI low and wait until the MISO

Initialization After Issuing the CMD_HW_RESET Command

The CMD_HW_RESET command performs a full power-down of all hardware, and the device enters the PHY_SLEEP state. To complete the hardware reset, the host processor should complete the following procedure:

1. Wai t for 1 ms.

2. Bring the

output goes high. The ADF7023-J registers a POR and enters the PHY_OFF state.

3. Issue the CMD_SYNC command.

4. Wait for the CMD_READY bit in the status word to go high.

5. Configure the part by writing to all 64 of the BBRAM registers.

6. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

The ADF7023-J is now configured in the PHY_OFF state.

pin of the SPI low and wait until the MISO

Initialization on Transitioning from PHY_SLEEP (After CS Is Brought Low)

The host processor can bring CS low at any time to wake the

ADF7023-J from the PHY_SLEEP state. This event is not

registered as a POR event because the BBRAM contents are valid. The following is the procedure that the host processor is required to follow:

1. Bring the

output goes high. The ADF7023-J enters the PHY_OFF state.

2. Issue the CMD_SYNC command.

3. Wait for the CMD_READY bit in the status word to go high.

4. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

The ADF7023-J is now configured and ready to transition to the PHY_ON state.

line of the SPI low and wait until the MISO

Initialization After a WUC Timeout

The ADF7023-J can autonomously wake from the PHY_SLEEP state using the wake-up controller. If the ADF7023-J wakes after a WUC timeout in smart wake mode (SWM), it follows the SWM routine based on the smart wake mode configuration in BBRAM (see the Low Power Modes section). If the ADF7023-J wakes after a WUC timeout with SWM disabled and the firmware timer disabled, it wakes in the PHY_OFF state, and the following is the procedure that the host processor is required to follow:

1. Issue the CMD_SYNC command.

2. Wait for the CMD_READY bit in the status word to go high.

3. Issue the CMD_CONFIG_DEV command so that the

radio settings are updated using the BBRAM values.

The ADF7023-J is now configured in the PHY_OFF state.

Rev. A | Page 29 of 104

ADF7023-J Data Sheet

COMMANDS

The commands that are supported by the radio controller are detailed in this section. They initiate transitions between radio states or perform tasks as indicated in Figure 47. The execution times for all radio state transitions are detailed in Table 11 and Table 12.

CMD_PHY_OFF (0xB0)

This command transitions the ADF7023-J to the PHY_OFF state. It can be issued in the PHY_ON state. It powers down the RF and VCO regulators.

CMD_PHY_ON (0xB1)

This command transitions the ADF7023-J to the PHY_ON state.

If the command is issued in the PHY_OFF state, it powers up the RF and VCO regulators and performs an IF filter calibration if the BB_CAL bit is set in the MODE_CONTROL register (Address 0x11A).

If the command is issued from the PHY_TX state, the host processor performs the following procedure:

1. Ramps down the PA.

2. Sets the external PA signal low (if enabled).

3. Turns off the digital transmit clocks.

4. Powers down the synthesizer.

5. Sets FW_STAT E = PHY_ON.

If the command is issued from the PHY_RX state, the communications processor performs the following procedure:

1. Copies the measured RSSI to the RSSI_READBACK register.

2. Sets the external LNA signal low (if enabled).

3. Turns off the digital receiver clocks.

4. Powers down the synthesizer and the receiver circuitry

(ADC, RSSI, IF filter, mixer, and LNA).

5. Sets FW_STAT E = PHY_ON.

CMD_PHY_SLEEP (0xBA)

This command transitions the ADF7023-J to the very low power PHY_SLEEP state in which the WUC is operational (if enabled), and the BBRAM contents are retained. It can be issued from the PHY_OFF or PHY_ON state.

CMD_PHY_RX (0xB2)

This command can be issued in the PHY_ON, PHY_RX, or PHY_TX state. If the command is issued in the PHY_ON state, the communications processor performs the following procedure:

1. Powers up the synthesizer.

2. Powers up the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

3. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

4. Sets the synthesizer bandwidth.

5. Does a VCO calibration.

6. Delays for synthesizer settling.

7. Enables the digital receiver blocks.

8. Sets the external LNA enable signal high (if enabled).

9. Sets FW_STAT E = PHY_RX.

Rev. A | Page 30 of 104

If the command is issued in the PHY_RX state, the communications processor performs the following procedure:

ets the external LNA signal low (if enabled).

1. S

2. Unlocks the AFC and AGC.

3. Turns off the receive blocks.

4. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

5. Sets the synthesizer bandwidth.

6. Does a VCO calibration.

7. Delays for synthesizer settling.

8. Enables the digital receiver blocks.

9. Sets the external LNA enable signal high (if enabled).

10. Sets FW_STATE = PHY_RX.

If the command is issued in the PHY_TX state, the communications processor performs the following procedure:

1. Ramps down the PA.

2. Sets the external PA signal low (if enabled).

3. Turns off the digital transmit blocks.

4. Powers up the receiver circuitry (ADC, RSSI, IF filter,

mixer, and LNA).

5. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

6. Sets the synthesizer bandwidth.

7. Does a VCO calibration.

8. Delays for synthesizer settling.

9. Enables the digital receiver blocks.

10. Sets the external LNA enable signal high (if enabled).

11. Sets FW_STATE = PHY_RX.

CMD_PHY_TX (0xB5)

This command can be issued in the PHY_ON, PHY_TX, or PHY_RX state. If the command is issued in the PHY_ON state, the communications processor performs the following procedure:

1. Powers up the synthesizer.

2. Sets the RF channel based on the CHANNEL_FREQ[23:0]

setting in BBRAM.

3. Sets the synthesizer bandwidth.

4. Does a VCO calibration.

5. Delays for synthesizer settling.

6. Enables the digital transmit blocks.

7. Sets the external PA enable signal high (if enabled).

8. Ramps up the PA.

9. Sets FW_STAT E = PHY_TX.

10. Transmits data.

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