ANALOG DEVICES ADF7021-V Service Manual

High Performance,

R

FEATURES

High performance, low power, narrow-band transceiver Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent

channel rejection (ACR) compared with the ADF7021-N

Programmable IF filter bandwidths: 9 kHz, 13.5 kHz,

and 18.5 kHz Modulation schemes: 2FSK, 3FSK, 4FSK, MSK Spectral shaping: Gaussian and raised cosine filtering Data rates: 0.05 kbps to 24 kbps Power supply: 2.3 V to 3.6 V Programmable output power: −16 dBm to +13 dBm

in 63 steps Automatic power amplifier (PA) ramp control Receiver sensitivity

−125 dBm at 250 bps, 2FSK

−122 dBm at 1 kbps, 2FSK

Patent pending, on-chip image rejection calibration

FUNCTIONAL BLOCK DIAGRAM

RSET

Narrow-Band Transceiver IC

ADF7021-V

On-chip fractional-N PLL On-chip, 7-bit ADC and temperature sensor Fully automatic frequency control (AFC) loop Digital received signal strength indication (RSSI) Integrated Tx/Rx switch Leakage current in power-down mode: 0.1 μA

APPLICATIONS

Narrow-band, short-range device (SRD) standards

ETSI EN 300 220

500 mW output power capability in 869 MHz g3 subband

with external PA

High performance receiver rejection, blocking, and

adjacent channel power (ACP) FCC Part 90 (meets Emission Mask D requirements) FCC Part 95 ARIB STD-T67

Wireless metering Narrow-band wireless telemetry

EG[1:4]CE

C

MUXOUT

R

LNA

RFIN RFIN

RFOUT

LNA

GAIN

PA RAMP

÷1/÷2

BUFFER

IF FILTER

÷2

L2

DIV P

CPOUT

TEMP

SENSOR

LOG AMP

ADF7021-V

CP

RSSI/

PFD

N/N + 1

MUX

MODULATOR

DIV R

7-BIT ADC

2FSK 3FSK 4FSK

DEMODULATOR

Σ-Δ

OSC

OSC1 OSC2

LDO[1:4]

CLOCK

AND DATA

RECOVERY

AGC

CONTROL

AFC

CONTROL

2FSK

3FSK

4FSK

MOD CONTROL

CLK

DIV

CLKOUT

TEST MUX

Tx/Rx

CONTROL

SERIAL

PORT

GAUSSIAN/

RAISED COSINE

FILTER

3FSK

ENCODING

TxRxCLK TxRxDATA

SWD

SLE SDATA SREAD SCLK

8635-001

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADF7021-V

REVISION HISTORY

4/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 60

ADF7021-V

GENERAL DESCRIPTION

The ADF7021-V is a high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip RF synthesizer for applications that require improved phase noise performance.

The ADF7021-V is designed to operate in both the license-free ISM bands and in the licensed bands from 80 MHz to 960 MHz.

To minimize RF feedthrough and spurious emissions, the external VCO operates at 2× or 4× the desired RF frequency; the ADF7021-V supports a maximum VCO frequency operation of 1920 MHz. The 4× VCO operation is programmable by enabling an additional on-chip divide-by-2 outside the RF synthesizer loop and offers improved phase noise performance.

As with the ADF7021-N receiver, the IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications.

The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the following:

• European ETSI EN 300 220

• North American FCC Part 15, Part 90, and Part 95

• Japanese ARIB STD-T67

• Korean short-range device regulations

• Chinese short-range device regulations

A complete transceiver can be built using a small number of discrete external components, making the ADF7021-V very suitable for area-sensitive, high performance driven applications.

The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. The ADF7021-V also supports protocols that dynamically switch among 2FSK, 3FSK, and 4FSK to maximize communication range and data throughput.

The transmit section contains a low noise fractional-N PLL with an output resolution of <1 ppm. The frequency-agile PLL allows the ADF7021-V to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO is external, which provides better phase noise and thus lower adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N. The VCO tuning range extends from 0.2 V to 2 V, which should be taken into account when choosing the external VCO.

The transmitter output power is programmable in 63 steps from

−16 dBm to +13 dBm and has an automatic power amplifier ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.

A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-V supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patented automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to remove the frequency error in the incoming signal.

The receiver achieves an image rejection performance of 50 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source.

An on-chip ADC provides readback of the integrated temperature sensor, external analog input, battery voltage, and RSSI signal, which can eliminate the need for an external ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by performing a one-point calibration at room temperature and storing the result in memory.

Rev. 0 | Page 3 of 60

ADF7021-V

SPECIFICATIONS

VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth.

RF AND PLL SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS

Phase Frequency Detector (PFD)

Frequenc y

PHASE-LOCKED LOOP (PLL)

Normalized In-Band Phase Noise

1

Floor

PLL Settling 155 μs

EXTERNAL VCO

Tuning Range 0.2 2 V Pin L2 Input Sensitivity 0 dBm VCO frequency < 1920 MHz

REFERENCE INPUT

Crystal Reference External Oscillator Crystal Start-Up Time

XTAL Bias = 20 μA 0.930 ms XTAL Bias = 35 μA 0.438 ms

Input Level for External Oscillator

OSC1 Pin 0.8 V p-p Clipped sine wave OSC2 Pin CMOS levels V

ADC PARAMETERS VDD = 2.3 V to 3.6 V, TA = 25°C

Integral Nonlinearity (INL) ±0.4 LSB Differential Nonlinearity (DNL) ±0.4 LSB

1

This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance

as seen at the power amplifier (PA) output: −203 + 10 log(f

2

Guaranteed by design. Sample tested to ensure compliance.

3

A TCXO, VCXO, or OCXO can be used as an external oscillator.

4

Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.

2

2, 3

3.625 24 MHz

4

to T

MIN

RF/256 24 MHz

, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All

MAX

Maximum usable PFD at a particular RF frequency is limited by the minimum N divider value

−203 dBc/Hz

Measured for a 100 kHz frequency step to within 5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz

3.625 24 MHz

10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V

) + 20 logN.

PFD

Rev. 0 | Page 4 of 60

ADF7021-V

TRANSMISSION SPECIFICATIONS

LBW = loop bandwidth.

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DATA RATE Limited by the loop bandwidth

2FSK 0.05 18.5 kbps LBW must be ≥1.25 × data rate for correct operation 3FSK 0.05 18.5 kbps LBW = 18.5 kHz 4FSK 0.05 24 kbps LBW = 18.5 kHz

MODULATION

Frequency Deviation (f

0.306 156 kHz PFD = 20 MHz Frequency Deviation Resolution 56 Hz PFD = 3.625 MHz Gaussian Filter Bandwidth Time (BT) 0.5 Raised Cosine Filter Alpha 0.5/0.7 Programmable

TRANSMIT POWER

Maximum Transmit Power Transmit Power Variation vs.

Temperature Transmit Power Variation vs. VDD ±1 dB VDD = 2.3 V to 3.6 V at 915 MHz, TA = 25°C Transmit Power Flatness ±1 dB 902 MHz to 928 MHz, VDD = 3 V, TA = 25°C Programmable Step Size 0.3125 dB −16 dBm to +13 dBm

ADJACENT CHANNEL POWER (ACP)

460 MHz

12.5 kHz Channel Spacing −47 dBm

25 kHz Channel Spacing −53 dBm

868 MHz Compliant with ETSI EN 300 220

12.5 kHz Channel Spacing −44 dBm

25 kHz Channel Spacing −49 dBm

MODULATION BANDWIDTH

125 kHz Offset −74.5 dBm/1 kHz 125 kHz + 200 kHz −79 dBm/1 kHz 125 kHz + 400 kHz −69.5 dBm/10 kHz 125 kHz + 1 MHz −62 dBm/100 kHz

EMISSION MASK

12.5 kHz Offset

460 MHz −77 dBc

OCCUPIED BANDWIDTH

2FSK, Gaussian Data Filtering

12.5 kHz Channel Spacing 4.0 kHz 2.4 kbps PN9 data, f

25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, f 2FSK, Raised Cosine Data Filtering

12.5 kHz Channel Spacing 4.5 kHz 2.4 kbps PN9 data, f

25 kHz Channel Spacing 9.6 kHz 4.8 kbps PN9 data, f

) 0.056 28.26 kHz PFD = 3.625 MHz

DEV

1

13 dBm VDD = 3.0 V, TA = 25°C ±1 dB T

= −40°C to +85°C

A

Gaussian 2FSK modulation, 13 dBm output power, PFD = 19.68 MHz, LBW = 6 kHz

Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, f

Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, f

Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, f

Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, f

869.525 MHz, Gaussian 2FSK modulation, 4.8 kbps, f

= 2.4 kHz, 10 dBm output power,2 compliant

DEV

with ETSI EN 300 220, LBW = 6 kHz

FCC Part 90 Emission Mask D, 100 Hz resolution bandwidth, Gaussian 2FSK modulation, LBW = 6 kHz, 10 dBm output power, 2.4 kbps PN9 data,

= 1.2 kHz

f

DEV

99.0% of total mean power, LBW = 6 kHz, 10 dBm output power

= 1.2 kHz

DEV

= 2.4 kHz

DEV

= 1.2 kHz

DEV

= 2.4 kHz

DEV

= 1.2 kHz

DEV

= 2.4 kHz

DEV

= 1.2 kHz

DEV

= 2.4 kHz

DEV

Rev. 0 | Page 5 of 60

ADF7021-V

Parameter Min Typ Max Unit Test Conditions/Comments

3FSK, Raised Cosine Filtering

12.5 kHz Channel Spacing 4.3 kHz 2.4 kbps PN9 data, f 25 kHz Channel Spacing 8.5 kHz 4.8 kbps PN9 data, f

4FSK, Raised Cosine Filtering

25 kHz Channel Spacing 11.3 kHz 9.6 kbps PN9 data, f

SPURIOUS EMISSIONS

Reference Spurs −65 dBc LBW = 8 kHz

HARMONICS

3

13 dBm output power Second Harmonic −35/−52 dBc Unfiltered conductive/filtered conductive Third Harmonic −43/−60 dBc Unfiltered conductive/filtered conductive All Other Harmonics −36/−65 dBc Unfiltered conductive/filtered conductive

OPTIMUM PA LOAD IMPEDANCE

fRF = 915 MHz 39 + j61 Ω fRF = 868 MHz 48 + j54 Ω fRF = 470 MHz 97.5 + j64.4 Ω fRF = 450 MHz 98 + j65 Ω fRF = 426 MHz 100 + j65 Ω fRF = 315 MHz 129 + j63 Ω fRF = 175 MHz 173 + j49 Ω fRF = 169 MHz 74.5 + j48.5 Ω

1

Measured as maximum unmodulated power.

2

Suitable for ETSI 500 mW Tx requirements.

3

Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor).

= 1.2 kHz

DEV

= 2.4 kHz

DEV

= 1.2 kHz

DEV

RECEIVER SPECIFICATIONS

LBW = loop bandwidth and IFBW = IF filter bandwidth.

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

DATA RATE Limited by the IF filter bandwidth

2FSK 0.05 9.0 kbps IFBW = 9 kHz

0.05 13.5 kbps IFBW = 13.5 kHz

0.05 18.5 kbps IFBW = 18.5 kHz 3FSK 0.05 18.5 kbps IFBW = 18.5 kHz 4FSK 0.05 24 kbps IFBW = 18.5 kHz

SENSITIVITY Bit error rate (BER) = 10−3

2FSK

Sensitivity at 0.25 kbps −125 dBm f Sensitivity at 1 kbps −122 dBm f Sensitivity at 2.4 kbps −119 dBm f Sensitivity at 4.8 kbps −116 dBm f Sensitivity at 9.6 kbps −114 dBm f

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz

DEV

Gaussian 2FSK

Sensitivity at 0.25 kbps −125 dBm f Sensitivity at 1 kbps −122 dBm f Sensitivity at 2.4 kbps −120 dBm f Sensitivity at 4.8 kbps −117 dBm f Sensitivity at 9.6 kbps −114 dBm f

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz

DEV

GMSK

Sensitivity at 4.8 kbps −114.5 dBm f

= 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

1

Rev. 0 | Page 6 of 60

ADF7021-V

Parameter Min Typ Max Unit Test Conditions/Comments

Raised Cosine 2FSK

Sensitivity at 0.25 kbps −125 dBm f Sensitivity at 1 kbps −121 dBm f Sensitivity at 2.4 kbps −120 dBm f Sensitivity at 4.8 kbps −115 dBm f Sensitivity at 9.6 kbps −114 dBm f

3FSK

Sensitivity at 4.8 kbps −110 dBm

Raised Cosine 3FSK

Sensitivity at 4.8 kbps −110 dBm

4FSK

Sensitivity at 4.8 kbps −112 dBm

Raised Cosine 4FSK

Sensitivity at 4.8 kbps −109 dBm

INPUT IP3

Low Gain, Enhanced Linearity

−3 dBm LNA_GAIN = 3, MIXER_LINEARITY = 1

Mode Medium Gain Mode −13.5 dBm LNA_GAIN = 10, MIXER_LINEARITY = 0 High Sensitivity Mode −24 dBm LNA_GAIN = 30, MIXER_LINEARITY = 0

ADJACENT CHANNEL REJECTION

(ACR) 868 MHz

12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 0.25 kbps, f

25 kHz Channel Spacing −39 dBm IFBW = 9 kHz, data rate = 0.25 kbps, f

12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, f

25 kHz Channel Spacing −40 dBm IFBW = 9 kHz, data rate = 1 kbps, f

12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 2.4 kbps, f

25 kHz Channel Spacing −42 dBm IFBW = 9 kHz, data rate = 2.4 kbps, f

12.5 kHz Channel Spacing −63 dBm IFBW = 9 kHz, data rate = 4.8 kbps, f

25 kHz Channel Spacing −45 dBm IFBW = 9 kHz, data rate = 4.8 kbps, f

25 kHz Channel Spacing −57 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, f 460 MHz

12.5 kHz Channel Spacing −59.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, f

25 kHz Channel Spacing −37.5 dBm IFBW = 9 kHz, data rate = 0.25 kbps, f

12.5 kHz Channel Spacing −60 dBm IFBW = 9 kHz, data rate = 1 kbps, f

25 kHz Channel Spacing −41 dBm IFBW = 9 kHz, data rate = 1 kbps, f

12.5 kHz Channel Spacing −62 dBm IFBW = 9 kHz, data rate = 2.4 kbps, f

25 kHz Channel Spacing −43 dBm IFBW = 9 kHz, data rate = 2.4 kbps, f

12.5 kHz Channel Spacing −61.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, f

25 kHz Channel Spacing −44.5 dBm IFBW = 9 kHz, data rate = 4.8 kbps, f

25 kHz Channel Spacing −56 dBm IFBW = 18.5 kHz, data rate = 9.6 kbps, f

COCHANNEL REJECTION

868 MHz −5 dB IFBW = 9 kHz, data rate = 4.8 kbps, f

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz

DEV

= 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz

DEV

= 2.4 kHz, high sensitivity mode, IFBW = 18.5 kHz,

f

DEV

Viterbi detection on

= 2.4 kHz, high sensitivity mode, IFBW = 13.5 kHz,

f

DEV

alpha = 0.5, Viterbi detection on

(inner)2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5

f

DEV

kHz

(inner)2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz,

f

DEV

alpha = 0.5 Two-tone test, f

− 800 kHz

f2 = f

LO

= 860 MHz, f1 = fLO + 100 kHz,

LO

Desired signal is 3 dB above the sensitivity point of

−109.5 dBm as per EN 300 220; rejection is measured as the level of an unmodulated interferer to cause a BER of 10

−2

for

the desired signal

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1.2 kHz, LBW = 6 kHz

DEV

= 1.2 kHz, LBW = 6 kHz

DEV

= 2.4 kHz, LBW = 6 kHz

DEV

= 2.4 kHz, LBW = 6 kHz

DEV

= 4.8 kHz, LBW = 6 kHz

DEV

Desired signal is at −106.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10

−2

for

the desired signal

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1 kHz, LBW = 6 kHz

DEV

= 1.2 kHz, LBW = 6 kHz

DEV

= 1.2 kHz, LBW = 6 kHz

DEV

= 2.4 kHz, LBW = 6 kHz

DEV

= 2.4 kHz, LBW = 6 kHz

DEV

= 4.8 kHz, LBW = 6 kHz

DEV

Desired signal is 3 dB above the sensitivity point of

−109.5 dBm; rejection is measured as the level of an interferer to cause a BER of 10

−2

for the desired signal

= 2.4 kHz, LBW = 6 kHz

DEV

Rev. 0 | Page 7 of 60

ADF7021-V

Parameter Min Typ Max Unit Test Conditions/Comments

IMAGE CHANNEL REJECTION

868 MHz 26/39 dB Uncalibrated/calibrated,3 VDD = 3.0 V, TA = 25°C 460 MHz 29/50 dB Uncalibrated/calibrated,3 VDD = 3.0 V, TA = 25°C

BLOCKING

±1 MHz −29.5 dBm ±2 MHz −26.5 dBm ±5 MHz −26 dBm ±10 MHz −25.5 dBm

SATURATION (MAXIMUM

12 dBm 2FSK mode, BER = 10

INPUT LEVEL)

RECEIVED SIGNAL STRENGTH

INDICATION (RSSI) Input Power Range

4

−120 to −47 dBm Linearity ±2 dB Input power range = −100 dBm to −47 dBm Absolute Accuracy ±3 dB Input power range = −100 dBm to −47 dBm Response Time 333 μs As per AGC gain stage, AGC clock = 3 kHz

AUTOMATIC FREQUENCY LOOP

(AFC) Pull-In Range, Minimum 0.5 kHz Range is programmable in Register 10 (Bits[DB31:DB24]) Pull-In Range, Maximum

1.5 × IF_

kHz Range is programmable in Register 10 (Bits[DB31:DB24])

FILTER_BW Response Time 96 Bits Dependent on modulation index Accuracy 0.5 kHz Input power range = −100 dBm to +12 dBm

Rx SPURIOUS EMISSIONS

5

External 920 MHz VCO −54/−88 dBm

External 920 MHz VCO −45/−66 dBm

External 1738 MHz VCO −85/−85 dBm

External 1738 MHz VCO −39/−52 dBm

LNA INPUT IMPEDANCE

fRF = 915 MHz 24 − j60 Ω fRF = 868 MHz 26 − j63 Ω fRF = 470 MHz 58 − j124 Ω fRF = 450 MHz 63 − j129 Ω fRF = 426 MHz 68 − j134 Ω fRF = 315 MHz 96 − j160 Ω fRF = 175 MHz 178 − j190 Ω fRF = 169 MHz 182.5 − j194 Ω

1

Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit-occupied signal bandwidth is within the receiver

IF filter bandwidth.

2

4FSK f

is defined as the frequency spacing from the RF carrier to +f

DEV

3

Calibration of the image rejection used an external RF source.

4

For received signal levels < −100 dBm, it is recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power.

5

Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor).

DEV

or −f

. It is also equal to half the frequency spacing between adjacent symbols.

DEV

Rev. 0 | Page 8 of 60

Desired signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 3 dB above the sensitivity point (BER = 10

−2

); modulated interferer (2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the image frequency of fRF − 200 kHz; the interferer level is increased until BER = 10

−2

Desired signal is 3 dB above the sensitivity point of

−109.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10

−2

for the

desired signal; as per ETSI EN 300 220-1

−3

<1 GHz at antenna input, unfiltered conductive/filtered conductive

>1 GHz at antenna input, unfiltered conductive/filtered conductive

<1 GHz at antenna input, unfiltered conductive/filtered conductive

>1 GHz at antenna input, unfiltered conductive/filtered conductive

RFIN to RFGND; refer to the AN-859 Application Note for other frequencies

ADF7021-V

DIGITAL SPECIFICATIONS

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

TIMING INFORMATION

Chip Enabled to Regulator

Ready

Chip Enabled to Tx Mode 32-bit register write time = 50 μs

TCXO Reference 1 ms Depends on VCO settling XTAL 2 ms Depends on VCO settling

Chip Enabled to Rx Mode

TCXO Reference 1.2 ms Depends on VCO settling XTAL 2.2 ms Depends on VCO settling

Tx-to-Rx Turnaround Time

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

0.7 × VDD V

INH

0.2 × VDD V

INL

±1 μA Input Capacitance, CIN 10 pF Control Clock Input 50 MHz

LOGIC OUTPUTS

Output High Voltage, VOH VDD2 − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA CLKOUT Rise/Fall Time 5 ns CLKOUT Load 10 pF

50 μs CREG[1:4] = 100 nF

32-bit register write time = 50 μs, IF filter coarse calibration only

AGC settling +

)

(5 × t

BIT

ms

Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization;

= data bit period; AFC settling not included

t

BIT

Rev. 0 | Page 9 of 60

ADF7021-V

GENERAL SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

TEMPERATURE RANGE (TA) −40 +85 °C POWER SUPPLIES

Voltage Supply, VDD 2.3 3.6 V All VDDx pins must be tied together

TRANSMIT CURRENT CONSUMPTION1,

868 MHz

0 dBm 17.6 mA 5 dBm 20.8 mA 10 dBm 27.1 mA

460 MHz

0 dBm 13.8 mA 5 dBm 17 mA 10 dBm 23 mA

RECEIVE CURRENT CONSUMPTION

868 MHz

Low Current Mode 19.3 mA High Sensitivity Mode 21.7 mA

460 MHz

Low Current Mode 16.3 mA High Sensitivity Mode 18.3 mA

POWER-DOWN CURRENT CONSUMPTION

Low Power Sleep Mode 0.1 1 μA CE low

1

The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards.

Improved PA efficiency is achieved by using a separate PA matching network.

2

Device current only. VCO and TCXO currents are excluded.

2

V

2

V

= 3.0 V, PA is matched into 50 Ω

DD

= 3.0 V

DD

TIMING CHARACTERISTICS

VDD = 3 V ± 10%, GND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.

Table 6.

Parameter Limit at T

t1 >10 ns SDATA to SCLK setup time t2 >10 ns SDATA to SCLK hold time t3 >25 ns SCLK high duration t4 >25 ns SCLK low duration t5 >10 ns SCLK to SLE setup time t6 >20 ns SLE pulse width t8 <25 ns SCLK to SREAD data valid, readback t9 <25 ns SREAD hold time after SCLK, readback t10 >10 ns SCLK to SLE disable time, readback t11 5 < t11 < (¼ × t t12 >5 ns TxRxDATA to TxRxCLK setup time (Tx mode) t13 >5 ns TxRxCLK to TxRxDATA hold time (Tx mode) t14 5 < t14 < (¼ × t t15 >¼ × t

to T

MIN

μs SLE positive edge to positive edge of TxRxCLK (Rx mode)

BIT

Unit Description

MAX

) ns TxRxCLK negative edge to SLE

BIT

) μs TxRxCLK negative edge to SLE

BIT

Rev. 0 | Page 10 of 60

ADF7021-V

S

T

TIMING DIAGRAMS

Serial Interface

SCLK

t

3

t

4

DATA

SLE

SCLK

SDATA

SLE

SREAD

DB31 (MSB) DB30

(CONTROL BIT C1)

2FSK/3FSK Timing

t

1

REG 7 DB0

t

1

t

2

DB2

(CONTROL BIT C3)

Figure 2. Serial Interface Timing Diagram

t

2

t

3

XRV16

t

8

9

RV15

Figure 3. Serial Interface Readback Timing Diagram

±1 × DATA RATE/32 1/DATA RATE

DB1

(CONTROL BIT C2)

RV2

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

10

RV1 X

t

6

08635-002

08635-003

TxRxCLK

xRxDATA

DATA

08635-004

Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode

1/DATA RATE

TxRxCLK

TxRxDATA

DATA

SAMPLEFETCH

08635-005

Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode

Rev. 0 | Page 11 of 60

ADF7021-V

4FSK Timing

In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream.

REGISTE R 0 W RI T E

SWITCH FROM Rx TO Tx

t

SLE

TxRxCLK

SYMBOL

t

BIT

11

t

13

t

12

TxRxDATA

Tx/Rx MODE

Rx SYMBOL

MSB

Rx SYMBOL

LSB

Rx SYMBOL

MSB

Rx SYMBOL

LSB

Rx MODE Tx MODE

Tx SYMBOL

MSB

Tx SYMBOL

LSB

Tx SYMBOL

MSB

08635-006

Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode

REGISTER 0 WRITE

SWITCH FROM Tx TO Rx

t

SLE

TxRxCLK

TxRxDATA

Tx SYMBOL

MSB

Tx SYMBOL

LSB

Tx SYMBOL

MSB

t

14

Tx SYMBOL

LSB

15

t

BIT

Rx SYMBOL

MSB

SYMBOL

Rx SYMBOL

LSB

Tx/Rx MODE

Tx MODE Rx MODE

Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode

Rev. 0 | Page 12 of 60

08635-007

ADF7021-V

A

UART/SPI Mode

UART mode is enabled by setting Register 0, Bit DB28 to 1. SPI mode is enabled by setting Register 0, Bit DB28 to 1 and setting Register 15, Bits[DB19:DB17] to 0x7. The transmit/receive data clock is available on the CLKOUT pin.

t

BIT

(TRANSMIT/RECEIVE DAT A

CLOCK IN SPI M ODE.

NOT USED IN UART MODE.)

(TRANSMIT DATA INPUT

IN UART/SPI M ODE.)

(RECEIVE DATA OUTPUT

IN UART/SPI M ODE.)

(TRANSMIT/RECEIVE DAT

CLOCK IN SPI M ODE.

NOT USED IN UART MODE.)

(TRANSMIT DATA INPUT

IN UART/SPI MODE.)

(RECEIVE DATA OUTPUT

IN UART/SPI MODE.)

CLKOUT

TxRxCLK

TxRxDATA

Tx/Rx MODE

CLKOUT

TxRxCLK

TxRxDATA

SAMPLE

FETCH

Tx BIT

HIGH-Z

Tx MODE

Figure 8. Transmit Timing Diagram in UART/SPI Mode

t

BIT

FETCH SAMPLE

HIGH-Z

Rx BIT

Tx BIT

Rx BIT

8635-008

Tx/Rx MODE

Rx MODE

8635-009

Figure 9. Receive Timing Diagram in UART/SPI Mode

Rev. 0 | Page 13 of 60

ADF7021-V

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 7.

Parameter Rating

VDD to GND1 −0.3 V to +5 V Analog I/O Voltage to GND1 −0.3 V to VDDx + 0.3 V Digital I/O Voltage to GND1 −0.3 V to VDDx + 0.3 V Operating Temperature Range

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C MLF θJA Thermal Impedance 26°C/W Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

1

GND = GND1 = GND2 = GND4 = RFGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

ESD CAUTION

Rev. 0 | Page 14 of 60

ADF7021-V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVCO

VCOIN

CREG1

VDD1

RFOUT

RFGND

RFIN RFIN

R

LNA

VDD4 RSET

CREG4

GND4

GND1L1GNDL2VDD

4847464544434241403938

PIN 1

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12

CPOUT

ADF7021-V

TOP VIEW

(Not to Scale)

CREG3

VDD3

OSC1

OSC2

MUXOUT

37

36

CLKOUT

35

TxRxCLK

34

TxRxDATA

33

SWD

32

VDD2

31

CREG2

30

ADCIN

29

GND2

28

SCLK

27

SREAD

26

SDATA

25

SLE

1314151617181920212223

MIX_I

MIX_Q

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED TO THE G ROUND PLANE.

GND4

FILT_I

MIX_Q

FILT_Q

GND4

24

CE

TEST_A

08635-011

Figure 10. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 VCOIN Do not connect. 2 CREG1

Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and ground for regulator stability and noise rejection.

3 VDD1

Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin. Tie all VDDx pins together.

4 RFOUT

The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The

output should be impedance matched to the desired load using suitable components. 5 RFGND Ground for Output Stage of Transmitter. Tie all GND pins together. 6 RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. 7

8 R

RFIN

External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

LNA

9 VDD4

Complementary LNA Input.

Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins

together. 10 RSET

External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with

5% tolerance. 11 CREG4

Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for

regulator stability and noise rejection. 12, 19, 22 GND4 Ground for LNA/Mixer Block. Tie all GND pins together. 13 to 16

17, 18, 20, 21

MIX_I, MIX_I MIX_Q, MIX_Q

FILT_I, FILT_I, FILT_Q, FILT_Q,

,

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.

23 TEST_A Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected. 24 CE

Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost

when CE is low, and the part must be reprogrammed after CE is brought high. 25 SLE

Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of

the 16 latches. A latch is selected using the control bits. 26 SDATA

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a

high impedance CMOS input.

Rev. 0 | Page 15 of 60

ADF7021-V

Pin No. Mnemonic Description

27 SREAD

28 SCLK

29 GND2 Ground for Digital Block. Tie all GND pins together. 30 ADCIN

31 CREG2

32 VDD2

33 SWD

34 TxRxDATA

35 TxRxCLK

36 CLKOUT

37 MUXOUT

38 OSC2

39 OSC1

40 VDD3

41 CREG3

42 CPOUT

43 VDD

44 L2 VCO Buffer Input. 45 GND Ground. Tie all GND pins together. 46 L1 Do not connect. 47 GND1 Ground. Tie all GND pins together. 48 CVCO Do not connect. EP Exposed Paddle The exposed paddle must be connected to the ground plane.

Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin.

Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the SCLK rising edge. This pin is a digital CMOS input.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is through the SREAD pin.

Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection.

Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together.

Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence. This provides an interrupt for an external microcontroller, indicating that valid data is being received.

Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI receive mode, this pin provides an output for the received data. In UART/SPI transmit mode, this pin is high impedance.

Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In standard transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART/SPI transmit mode, this pin is used to input the transmit data. In UART/SPI receive mode, this pin is high impedance.

Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark/space ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in applications where the CLKOUT feature is used.

Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine whether the PLL is locked to the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the serial interface regulator.

Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the internal crystal oscillator.

Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator.

Voltage Supply for Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins together.

Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection.

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO.

Voltage Supply for RF Circuitry. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together.

Rev. 0 | Page 16 of 60

ADF7021-V

–

TYPICAL PERFORMANCE CHARACTERISTICS

80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1 10 100 1k 10k 100k

FREQUENCY OFFSET (kHz)

RF FREQ = 460MHz TCXO = 19.2MHz

ICP= 0.3mA

= 0.9mA

I

CP

Figure 11. Phase Noise Response at 460 MHz, VDD = 3 V

08635-077

16 12

8

PA_BIAS = 9µA

4

0 –4 –8

–12 –16 –20 –24

RF OUTPUT POWER (dBm)

–28 –32 –36 –40

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60

PA_BIAS = 11µA

PA_BIAS = 7µA

PA SETTING

PA_BIAS = 5µA

Figure 14. RF Output Power vs. PA Setting

08635-012

60

–70

–80

–90

–100 –110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1 10 100 1k 10k

FREQUENCY OFFSET (kHz)

RF FREQ = 8 68M Hz TCXO = 19. 2 M Hz

ICP= 0.3mA I

= 0.9mA

CP

I

= 1.5mA

CP

I

= 2.1mA

CP

Figure 12. Phase Noise Response at 868 MHz, VDD = 2.3 V

20

DEMODULATI O N = G F SK

10

DATA RATE = 2.4kbps

f

= 1.2kHz

DEV

RF FREQ = 4 70M Hz

0

IFBW = 4kHz

–10

–20 –30

–40

–50

OUTPUT POWER (dBm)

–60

–70 –80

–25,000

0

–20,000

–15,000

FREQUENCY OFFSET FROM CARRIER (Hz)

–5000

–10,000

FCC PART 90 EMISSION MASK D

5000

10,000

15,000

Figure 13. Output Spectrum in FCC Part 90 Emission Mask D

and GFSK Modes

20,000

25,000

20

0

–20

–40

–60

OUTPUT POWER (dBm)

–80

–100

300 800 1300 1800 2300 2800

08635-078

FREQUENCY (MHz)

08635-013

Figure 15. PA Output Harmonic Response with T-Stage LC Filter

10

0

–10

–20

–30

–40

–50

OUTPUT POWER (dBm)

–60

–70

–80

867.97 867.98 867.99 868.00 868.01 868.02 868.03

08635-079

GFSK

FREQUENCY (MHz)

DATA RATE = 9.6kbps DATA = P RBS9

f

= 2.4kHz

DEV

RF FREQ = 868MHz

2FSK

08635-014

Figure 16. Output Spectrum in 2FSK and GFSK Modes

Rev. 0 | Page 17 of 60

ADF7021-V

R

10

0

–10

–20

–30

–40

–50

OUTPUT POWER (dBm)

–60

–70

–80

867.97 867.98 867.99 868.00 868.01 868.02 868.03 FREQUENCY (MHz)

DATA RATE = 9.6kbps DATA = P RBS 9

f

= 2.4kHz

DEV

RF FREQ = 86 8M Hz

RC2FSK

2FSK

Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes

08635-015

RAMP RATE:

10

CW ONLY 256 CODES/BI T 128 CODES/BI T

0

64 CODES/BIT 32 CODES/BIT

–10

–20

–30

OUTPUT PO WER (dBm)

–40

–50

–60

–100 –50 500 100

FREQUENCY OFFSET (kHz)

TRACE = MAX HOLD PA ON/OFF RATE = 3Hz PA ON/OFF CYCLES = 10,000 V

= 3.0V

DD

Figure 20. Output Spectrum in Maximum Hold

for Various PA Ramp Rate Options

08635-018

10

0

–10

–20

–30

–40

–50

OUTPUT POWER (dBm)

–60

–70

–80

867.97 867.98 867.99 868.00 868.01 868.02 868.03 FREQUENCY (MHz)

DATA RATE = 9.6kbps DATA = PRBS9

f

DEV

RF FREQ = 868M Hz

RC3FSK

= 2.4kHz

3FSK

Figure 18. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes

10

0

–10

–20

–30

–40

–50 –60

OUTPUT PO WER (dBm)

–70

–80 –90

867.94 867.96 867.98 868.00 868.02 868.04 868.06

RC4FSK

FREQUENCY (MHz)

DATA RATE = 9.6kbps DATA = PRBS9

f

= 2.4kHz

DEV

RF FREQ = 868M Hz

4FSK

Figure 19. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes

0

–1

–2

–3

–40°C, 2.3V

–4

LOG BE

08635-016

–40°C, 3V –40°C, 3.6V +25°C, 2. 3V

–5

+25°C, 3V +25°C, 3. 6V +85°C, 2. 3V

–6

+85°C, 3V +85°C, 3. 6V

–7

–125 –123 –121 –119 –117 –115 –113 –111 –109 –107 –105

RF INPUT POWER (dBm)

DATA RAT E = 2.4kbps f

= 4.8Hz

DEV

RF FREQ = 868M Hz IFBW = 9kHz

08635-019

Figure 21. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz

0

–1

–2

–3

–40°C, 2.3V

–4

LOG BE

08635-017

–40°C, 3V –40°C, 3.6V +25°C, 2.3V

–5

+25°C, 3V +25°C, 3.6V +85°C, 2.3V

–6

+85°C, 3V +85°C, 3.6V

–7

–127 –125 –123 –121 –119 –117 –115 –113 –111

RF INPUT POWER (dBm)

DATA RATE = 1.2kbps f

= 2.4Hz

DEV

RF FREQ = 46 0M Hz IFBW = 9kHz

08635-020

Figure 22. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz

Rev. 0 | Page 18 of 60

ANALOG DEVICES ADF7021-V Service Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

RF AND PLL SPECIFICATIONS

TRANSMISSION SPECIFICATIONS

RECEIVER SPECIFICATIONS

DIGITAL SPECIFICATIONS

GENERAL SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAMS

Serial Interface

2FSK/3FSK Timing

4FSK Timing

UART/SPI Mode

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS