Analog Devices ADF7010 Datasheet

High Performance ISM Band

a

FEATURES
Single Chip Low Power UHF Transmitter
902 MHz–928 MHz Frequency Band
On-Chip VCO and Fractional-N PLL

2.3 V–3.6 V Supply Voltage
Programmable Output Power

–16 dBm to +12 dBm, 0.3 dB Steps
Data Rates up to 76.8 kbps
Low Current Consumption

28 mA at 8 dBm Output
Power-Down Mode (<1 A)
24-Lead TSSOP Package

APPLICATIONS
Low Cost Wireless Data Transfer
Wireless Metering
Remote Control/Security Systems
Keyless Entry

ASK/FSK/GFSK Transmitter IC

ADF7010

GENERAL DESCRIPTION

The ADF7010 is a low power OOK/ASK/FSK/GFSK UHF
transmitter designed for use in ISM band systems. It contains
an integrated VCO and sigma-delta fractional-N PLL. The
output power, channel spacing, and output frequency are pro­grammable with four 24-bit registers. The fractional-N PLL
enables the user to select any channel frequency within the U.S.
902 MHz–928 MHz band, allowing the use of the ADF7010 in
frequency hopping systems.

It is possible to choose from the four different modulation
schemes: Binary or Gaussian Frequency Shift Keying (FSK/
GFSK), Amplitude Shift Keying (ASK), or On/Off Keying
(OOK). The device also features a crystal compensation register
that can provide 1 ppm resolution in the output frequency.
Indirect temperature compensation of the crystal can be accom­plished inexpensively using this register.

Control of the four on-chip registers is via a simple 3-wire inter­face. The devices operate with a power supply ranging from

2.3 V to 3.6 V and can be powered down when not in use.

DV

D

GND

TxCLK

TxDATA

DATA

CLK

FUNCTIONAL BLOCK DIAGRAM

C

REG

CPVDDCP

CLK

OSC1

DD

OOK/ASK

FSK/GFSK

LE

OSC2

SERIAL

INTERFACE

 CLK

 R

FREQUENCY

COMPENSATION

FREQUENCY

CENTER

OUT

PFD/

CHARGE

PUMP

GND

 FRACTIONAL N

SIGMA-DELTA

C

VCO

LOCK DETECT

VCO

VCO

OOK/ASK

PA

LDO

REGULATOR

MUXOUT

GND

RF

OUT

RF

GND

C

REG

MUXOUT

R

SET

V

DD

CE

A

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

TEST

ADF7010–SPECIFICATIONS

(VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T

1

specifications are at VDD = 3 V, TA = 25C.)

MIN

to T

, unless otherwise noted. Typical

MAX

Parameter Min Typ Max Unit

RF CHARACTERISTICS

Output Frequency Ranges

U.S. ISM Band 902 928 MHz

Phase Frequency Detector Frequency 3.625 20 MHz @ 928 MHz

TRANSMISSION PARAMETERS

Transmit Rate

FSK 0.3 76.8 kbps
ASK 0.3 9.6 kbps
GFSK 0.3 76.8 kbps

Frequency Shift Keying

FSK Separation

2, 3

1 110 kHz, Using 3.625 MHz PFD

4.88 620 kHz, Using 20 MHz PFD

Gaussian Filter t 0.5

Amplitude Shift Keying Depth 30 dB, Max Output Power 2 dBm
On/Off Keying 40 dB
Output Power
Output Power Variation

Max Power Setting 9 12 dBm, V

11 dBm, V

9.5 dBm, V

= 3.6 V

DD

= 3.0 V

DD

= 2.3 V

DD

Programmable Step Size

–16 dBm to +12 dBm 0.3125 dB

LOGIC INPUTS

V

, Input High Voltage 0.7  V

INH

, Input Low Voltage 0.2  V

V

INL

I

INH/IINL

C

, Input Current 1 mA

, Input Capacitance 10 pF

IN

DD

DD

V
V

Control Clock Input 50 MHz

LOGIC OUTPUTS

VOH, Output High Voltage DV

, Output Low Voltage 0.4 V, I

V

OL

CLK
CLK

Rise/Fall Time 16 ns, F

OUT

Mark: Space Ratio 50:50

OUT

– 0.4 V, I

DD

= 500 mA

OH

= 500 mA

OL

= 4.8 MHz into 10 pF

CLK

POWER SUPPLIES

Voltage Supply

DV

DD

2.3 3.6 V

Transmit Current Consumption

–20 dBm (0.01 mW) 12 mA
–10 dBm (0.1 mW) 15 mA
0 dBm (1 mW) 20 mA
+8 dBm (6.3 mW) 28 mA
+12 dBm (16 mW) 40 mA

Crystal Oscillator Block Current

Consumption 190 mA
Regulator Current Consumption 380 mA
Power-Down Mode

Low Power Sleep Mode 0.2 1 mA

REV. 0–2–

Parameter Min Typ Max Unit

PHASE-LOCKED LOOP

VCO Gain 80 MHz/V @ 915 MHz
Phase Noise (In-Band)
Phase Noise (Out of Band)
Spurious 100 kHz Loop BW

Integer Boundary
Reference –50 dBc

Harmonics

7

Second Harmonic V

4

5

6

–80 dBc/Hz @ 5 kHz Offset
–100 dBc/Hz @ 1 MHz Offset

–55 dBc, 50 kHz Loop

–14 dBc

= 3.0 V –27 –18 dBc

DD

Third Harmonic VDD = 3.0 V –21 –18 dBc
All Other Harmonics –35 dBc

REFERENCE INPUT

Crystal Reference 3.625 20 MHz
External Oscillator 3.625 40 MHz

Input Level, High Voltage 0.7  V

DD

Input Level, Low Voltage 0.2  V

DD

V
V

FREQUENCY COMPENSATION

Pull In Range of Register 1 100 ppm

PA CHARACTERISTICS

RF Output Impedance

High Range Amplifier 16 – j33 W, Z

TIMING INFORMATION

Chip Enabled to Regulator Ready
Crystal Oscillator to CLK

OUT

TEMPERATURE RANGE, T

NOTES

1

Operating temperature range is as follows: –40∞C to +85∞C.

2

Frequency Deviation = (PFD Frequency  Mod Deviation )/212.

3

GFSK Frequency Deviation = (PFD Frequency  2m)/2

4

VDD = 3 V, PFD = 19.2 MHz, PA = 8 dBm

5

VDD = 3 V, Loop Filter BW = 100 kHz

6

Measured >1 MHz away from integer channel. See Successful Design with ADF7010 Transmitter application note.

7

Not production tested. Based on characterization.

Specifications subject to change without notice.

7

50 200 ms

OK 2 ms, 19.2 MHz Xtal

A

–40 +85 C

12

where m = Mod Control.

REF

= 50 W

ADF7010

REV. 0

–3–

ADF7010

(V

TIMING CHARACTERISTICS

Limit at
T

to T

Parameter (B Version) Unit Test Conditions/Comments

MIN

t

1

t

2

t

3

t

4

t

5

t

6

Guaranteed by design but not production tested.

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

MAX

= 3 V 10%, VGND = 0 V, TA = 25C, unless otherwise noted.)

DD

CLOCK

DATA

LE

t

1

DB23 (MSB) DB22 DB2

t

2

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

1, 2

VDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.0 V

VCOVDD, RFVDD, CPVDD to GND . . . . . –0.3 V to +7 V

Digital I/O Voltage to GND . . . . . . –0.3 V to DVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

TSSOP 
CSP 
CSP 

Thermal Impedance . . . . . . . . . . . . . . 150.4∞C/W

JA

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . 122∞C/W

JA

(Paddle Not Soldered) . . . . . . . . . . . . . . . . . 216∞C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C

t

3

t

4

DB1

(CONTROL BIT C2)

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating of
<1 kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.

3

GND = CPGND = RFGND = DGND = AGND = 0 V.

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

ORDERING GUIDE

Model Temperature Range Package Option

ADF7010BRU –40ºC to +85ºC RU-24 (TSSOP)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF7010 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–4–

PIN CONFIGURATION

ADF7010

R

SET

CPV

CP

GND

CP

OUT

CE

DATA

CLK

TxDATA

TxCLK

MUXOUT

D

GND

DD

LE

1

2

3

4

5

ADF7010

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

TSSOP

24

C

REG

23

C

VCO

22

VCO

IN

21

A

GND

20

RF

OUT

19

RF

GND

18

DV

DD

17

TEST

16

VCO

GND

15

OSC1

14

OSC2

13

CLK

OUT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1R

2 CPV

SET

DD

External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 4.7 kW as default:

I

CP MAX

So, with R

95.

=

R

SET

= 4.7 kW, I

SET

CPMAX

= 2.02 mA.

Charge Pump Supply. This should be biased at the same level as RFVDD and DVDD. The pin should be
decoupled with a 0.1 mF capacitor as close to the pin as possible.

3CP

4CP

GND

OUT

Charge Pump Ground

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.

5CEChip Enable. A logic low applied to this pin powers down the part. This must be high for the part to

function. This is the only way to power down the regulator circuit.

6 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.

This is a high impedance CMOS input.

7 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This is a high impedance CMOS input.

8LELoad Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches, the latch being selected using the control bits.

9TxDATA Digital data to be transmitted is input on this pin.

10 TxCLK GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the

ADF7010. The clock is provided at the same frequency as the data rate.

11 MUXOUT This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled

reference frequency to be accessed externally. Used commonly for system debug. See Function Register Map.

12 D

GND

13 CLK

OUT

Ground Pin for the RF Digital Circuitry

The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock input
of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can be
reduced with a series RC. For 4.8 MHz output clock, a series 50 W into 10 pF will reduce spurs to
< –50 dBc. Defaults on power-up to divide by 16.

14 OSC2 Oscillator Pin. If a single-ended reference is used (such as a TCXO), it should be applied to this pin.

When using an external signal generator, a 51 W resistor should be tied from this pin to ground. The
XOE bit in the R Register should set high when using an external reference.

REV. 0

–5–

ADF7010

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Function

15 OSC1 Oscillator Pin. For use with crystal reference only. This is three-stated when an external reference oscillator

is used.

16 VCO

GND

17 TEST Input to the RF fractional-N divider. This pin allows the user to connect an external VCO to the part.

18 DV

19 RF

20 RF

21 A

22 VCO

23 C

24 C

DD

GND

OUT

GND

IN

VCO

REG

Voltage Controlled Oscillator Ground

Disabling the internal VCO activates this pin. If the internal VCO is used, this pin should be grounded.

Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors
to the analog ground plane should be placed as close as possible to this pin.

Ground for Output Stage of Transmitter

The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The
output should be impedance matched to the desired load using suitable components. See the Output RF
Stage section.

Ground Pin for the RF Analog Circuitry

The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator
(VCO). The higher the tuning voltage the higher the output frequency.

A 0.22 mF capacitor should be added to reduce noise on VCO bias lines. Tied to C

A 2.2 mF capacitor should be added at C

to reduce regulator noise and improve stability. A

REG

REG

pin.

reduced

capacitor will improve regulator power-on time but may cause higher spurious components.

REV. 0–6–