Analog Devices ADF4251 Datasheet

Dual Fractional-N/Integer-N

Frequency Synthesizer

ADF4251

FEATURES

3.0 GHz Fractional-N/1.2 GHz Integer-N

2.7 V to 3.3 V Power Supply
Separate V

Allows Extended Tuning Voltage to 5 V

P

Programmable Dual Modulus Prescaler

RF: 4/5, 8/9

IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Programmable Modulus on Fractional-N Synthesizer
Trade-Off Noise versus Spurious Performance
Software and Hardware Power-Down

APPLICATIONS
Base Stations for Mobile Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA,

PHS)
Wireless LANs
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

VDD1 VDD2 VDD3 DVDDVP1 VP2R

ADF4251

REF

IN

2

DOUBLER

GENERAL DESCRIPTION

The ADF4251 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators
(LO) in the upconversion and downconversion sections of
wireless receivers and transmitters. Both the RF and IF syn­thesizers consist of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a programmable refer­ence divider. The RF synthesizer has a ⌺-⌬ based fractional
interpolator that allows programmable fractional-N division.
The IF synthesizer has programmable integer-N counters. A
complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and VCO (volt­age controlled oscillator).

Control of all the on-chip registers is via a simple 3-wire inter­face. The devices operate with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

SET

CE

CP

RF

4-BIT R

COUNTER

PHASE

FREQUENCY

DETECTOR

REFERENCE

CHARGE

PUMP

MUXOUT

CLK

DATA

LE

FROM
REFIN

OUTPUT

MUX

24-BIT

DATA

REGISTER

DOUBLER

2

A

GND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

LOCK

DETECT

FRACTIONAL N

RF DIVIDER

INTEGER N
IF DIVIDER

PHASE

FREQUENCY

15-BIT R

COUNTER

1 A

2 D

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

DETECTOR

GNDCPGND

1 CP

GND

2

CHARGE

PUMP

RFINA

RF

IN

IFINB

IF

IN

CP

IF

B

A

(VDD1 = VDD2 = VDD3 = DVDD = 3 V  10%, VP1 = VP2 = 5 V  10%, GND = 0 V,

1

R

ADF4251–SPECIFICATIONS

= 2.7 k, dBm referred to 50 , TA = T

SET

MIN

to T

, unless otherwise noted.)

MAX

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RF

A, RFINB)

IN

RF Input Sensitivity –10/0 dBm min/max
RF Input Frequency (RF

A, RFINB)

IN

2

2

0.25/3.0 GHz min/max

0.1/3.0 GHz min/max Input Level = –8/0 dBm min/max
RF Phase Detector Frequency 30 MHz max Guaranteed by Design
Allowable Prescaler Output Frequency 375 MHz max

IF CHARACTERISTICS

IF Input Frequency (IF

IN

A, IFINB)

2

50/1200 MHz min/max
IF Input Sensitivity –10/0 dBm min/max
IF Phase Detector Frequency 55 MHz max Guaranteed by Design
Allowable Prescaler Output Frequency 150 MHz max

REFERENCE CHARACTERISTICS

Input Frequency 250 MHz max For f < 10 MHz, use dc-coupled square

REF

IN

wave (0 to V

Input Sensitivity 0.5/VDD1V p-p min/max AC-coupled. When dc-coupled, use

REF

IN

Input Current ±100 µA max

REF

IN

0 to V

DD

).

DD

max (CMOS compatible).

REFIN Input Capacitance 10 pF max

CHARGE PUMP

Sink/Source High Value 4.375 mA typ See Table V

RF I

CP

Low Value 625 µA typ

IF I

Sink/Source High Value 5 mA typ See Table IX

CP

Low Value 625 µA typ

Three-State Leakage Current 1 nA typ

I

CP

RF Sink and Source Current Matching 2 % typ 0.5 V < V

< VP – 0.5

CP

IF Sink and Source Current Matching 2 % typ
I

CP

vs. V

CP

2% typ 0.5 V < VCP < VP – 0.5
ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

, Input High Voltage 1.35 V min

V

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN Input Capacitance 10 pF max

LOGIC OUTPUTS

, Output High Voltage VDD – 0.4 V min IOH = 0.2 mA

V

OH

VOL, Output Low Voltage 0.4 V max IOL = 0.2 mA

POWER SUPPLIES

V

DD1, VDD

DV

1, VP2V

V

P

I

DD

2, VDD3 2.7/3.3 V min/V max

DD

3

RF + IF 13 mA typ 16 mA max

VDD1

1/5.5 V min/V max

DD

RF Only 10 mA typ 13 mA max
IF Only 4 mA typ 5.5 mA max

Low Power Sleep Mode/Power-Down 10 pA typ

RF NOISE AND SPURIOUS CHARACTERISTICS

Noise Floor –141 dBc/Hz typ @ 20 MHz PFD Frequency
In-Band Phase Noise Performance

Lowest Spur Mode –90 dBc/Hz typ RF
Low Noise and Spur Mode –95 dBc/Hz typ RF
Lowest Noise Mode –103 dBc/Hz typ RF

4

@ VCO Output

= 1.8 GHz, PFD = 20 MHz

OUT

= 1.8 GHz, PFD = 20 MHz

OUT

= 1.8 GHz, PFD = 20 MHz

OUT

Spurious Signals See Typical Performance Characteristics

NOTES

1

Operating Temperature Range (B Version): –40°C to +85°C.

2

Use a square wave for frequencies less than F

3

RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, VDD = 3 V, VP1 = 5 V, and VP2 = 3 V.

4

The in-band phase noise is measured with the EVAL-ADF4251EB2 Evaluation Board and the HP5500E Phase Noise Test System. The spectrum analyzer provides the
REFIN for the synthesizer (f

Specifications subject to change without notice.

= 10 MHz @ 0 dBm). F

REFOUT

MIN

.

= 1.74 GHz, F

OUT

= 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, VDD = 3.3 V, and VP= 5 V.

REF

REV. 0–2–

ADF4251

TIMING CHARACTERISTICS

*

(VDD1 = VDD2 = VDD3 = DVDD = 3 V  10%, VP1 = VP2 = 5 V  10%, GND = 0 V, unless otherwise noted.)

Limit at

to T

T

MIN

MAX

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

*Guaranteed by design but not production tested.

CLOCK

DATA

10 ns min LE Setup Time
10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

DB23

(MSB)

t

4

DB22

t

3

DB2

t

2

t

5

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

LE

t

1

LE

t

6

Figure 1. Timing Diagram

REV. 0

–3–

ADF4251

ABSOLUTE MAXIMUM RATINGS

1, 2

(TA = 25°C, unless otherwise noted.)

VDD1, VDD2, VDD3, DVDD to GND3 . . . . . . . . –0.3 V to +4 V

REF

, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V

IN

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V

V

P

V

1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . . –3.3 V to +3.5 V

P

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

LFCSP ␪

Thermal Impedance . . . . . . . . . . . . . . . . 122°C/W

JA

Soldering Reflow Temperature

Vapor Phase (60 sec max) . . . . . . . . . . . . . . . . . . . . . 240°C

IR Reflow (20 sec max) . . . . . . . . . . . . . . . . . . . . . . . 240°C

ORDERING GUIDE

Model Temperature Range Package Option*

ADF4251BCP –40ºC to +85ºC CP-24
ADF4251BCP-REEL –40ºC to +85ºC CP-24
ADF4251BCP-REEL7 –40ºC to +85ºC CP-24

*CP = Lead Frame Chip Scale Package

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating
of <2 kW, and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = CP

GND

1, A

GND

1, D

GND

, A

2, and CP

GND

GND

2.

PIN CONFIGURATION

1

3

2

DD

DD

22 V

9

GND

D

2

P

DD

21 V

20 V

CLK 10

DATA 11

IF

19 CP

LE 12

18 CP
17 DV
16 IFINA
15 IF

IN

14 A

GND

13 R

SET

GND

DD

B

2

2

CP

RF

CP

1 2

GND

RF

A 3

IN

RFINB 4

A

1 5

GND

MUXOUT 6

1

1

P

24 V

23 V

PIN 1
INDICATOR

ADF4251

TOP VIEW

(Not to Scale)

7

IN

CE 8

REF

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4251 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. 0–4–

ADF4251

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

CP

RF

CP

1 RF Charge Pump Ground

GND

RF

A Input to the RF Prescaler. This small signal input is normally taken from the VCO.

IN

RF

BComplementary Input to the RF Prescaler

IN

A

1Analog Ground for the RF Synthesizer

GND

MUXOUT This multiplexer output allows either the RF or IF lock detect, the scaled RF or IF, or the scaled reference fre-

REF

IN

CE Chip Enable. A Logic Low on this bit powers down the device and puts the charge pump outputs into three-state.

D

GND

CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a

LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

R

SET

A

2Ground for the IF Synthesizer

GND

IF

BComplementary Input to the IF Prescaler

IN

IF

A Input to the IF Prescaler. This small signal input is normally taken from the IF VCO.

IN

DV

DD

CP

2IF Charge Pump Ground

GND

CP

IF

V

2IF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible

P

V

2Positive Power Supply for the IF Section. Decoupling capacitors to the ground plane should be placed as close as

DD

V

3 Positive Power Supply for the RF Digital Section. Decoupling capacitors to the ground plane should be placed as close

DD

V

1 Positive Power Supply for the RF Analog Section. Decoupling capacitors to the ground plane should be placed as close

DD

V

1 RF Charge Pump Power Supply. Decoupling capacitors to the ground plane should be placed as close as possible

P

RF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.

quency to be accessed externally.

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 kW. This input can be driven from a TTL or CMOS crystal oscillator.

A Logic High on this pin powers up the device, depending on the status of the software power-down bits.

Digital Ground for the Fractional Interpolator

shift register on the CLK rising edge. This input is a high impedance CMOS input.

high impedance CMOS input.

seven latches, the latch being selected using the control bits.

Connecting a resistor between this pin and ground sets the minimum charge pump output current. The relationship
between I

I

CP MIN

Therefore, with R

=

and R

CP

1 6875.

R

SET

is:

SET

= 2.7 kW, I

SET

= 0.625 mA.

CP MIN

Positive Power Supply for the Fractional Interpolator Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. DV

must have the same voltage as VDD1, VDD2, and VDD3.

DD

IF Charge Pump Output. This is normally connected to a loop filter that drives the input to an external VCO.

to this pin. This voltage should be greater than or equal to V

possible to this pin. V

as possible to this pin. V

as possible to this pin. V

2 has a value 3 V ± 10%. VDD2 must have the same voltage as VDD1, VDD3, and DVDD.

DD

3 has a value 3 V ± 10%. VDD3 must have the same voltage as VDD1, VDD2, and DVDD.

DD

1 has a value 3 V ± 10%. VDD1 must have the same voltage as VDD2, VDD3, and DVDD.

DD

DD

2.

to this pin. This voltage should be greater than or equal to VDD1.

REV. 0

–5–

ADF4251

REF

MUXOUT

CLK

DATA

IN

LE

ADF4251

FROM
REFIN

VDD1 VDD2 VDD3 DVDDVP1 VP2R

A

GND

4-BIT R

COUNTER

LOCK

DETECT

15-BIT R

COUNTER

1 A

GND

2 D

PHASE

FREQUENCY

DETECTOR

FRACTIONAL N

RF DIVIDER

INTEGER N

IF DIVIDER

PHASE

FREQUENCY

DETECTOR

GNDCPGND

1 CP

DOUBLER

OUTPUT

MUX

24-BIT

DATA

REGISTER

DOUBLER

2

2

Figure 2. Detailed Functional Block Diagram

GND

REFERENCE

CHARGE

CHARGE

2

SET

PUMP

PUMP

CE

CP

RF

RFINA

RF

IN

IFINB

IF

IN

CP

IF

B

A

REV. 0–6–

Typical Performance Characteristics–ADF4251

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 10MHz

–20

CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–99.19dBc/Hz

TPC 1. Phase Noise Plot, Lowest Noise Mode,

1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

–10

= 1.875mA

I

CP

PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–90.36dBc/Hz

TPC 2. Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 10MHz

–20

CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–50dBc@

100kHz

–400kHz –200kHz 1.7518GHz 200kHz 400kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

TPC 4. Spurious Plot, Lowest Noise Mode,

1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

–10

= 1.875mA

I

CP

PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–51dBc@

–400kHz

100kHz

–200kHz 1.7518GHz 200kHz 400kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

TPC 5. Spurious Plot, Low Noise and Spur Mode,

1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

–10

= 1.875mA

I

CP

PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–85.86dBc/Hz

TPC 3. Phase Noise Plot, Lowest Spur Mode,

1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

–10

= 1.875mA

I

CP

PFD FREQUENCY = 10MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–400kHz

–72dBc@

100kHz

–200kHz 1.7518GHz 200kHz 400kHz

TPC 6. Spurious Plot, Lowest Spur Mode,

1.7518 GHz RF

, 10 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

TPCs 1–12 attained using EVAL-ADF4252EB1 Evaluation Board; measurements from HP8562E spectrum analyzer.

REV. 0

–7–

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

ADF4251

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–102dBc/Hz

TPC 7. Phase Noise Plot, Lowest Noise Mode,

1.7518 GHz RF

, 20 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–93.86dBc/Hz

TPC 8. Phase Noise Plot, Low Noise and Spur
Mode, 1.7518 GHz RF

, 20 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–53dBc@

100kHz

–400kHz –200kHz 1.7518GHz 200kHz 400kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

TPC 10. Spurious Plot, Lowest Noise Mode,

1.7518 GHz RF

, 20 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–63.2dBc@

–400kHz

100kHz

–200kHz 1.7518GHz 200kHz 400kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

TPC 11. Spurious Plot, Low Noise and Spur Mode,

1.7518 GHz RF

, 20 MHz PFD Frequency, 200 kHz

OUT

Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 10Hz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2kHz

–1kHz 1.7518GHz 1kHz 2kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

–89.52dBc/Hz

TPC 9. Phase Noise Plot, Lowest Spur Mode,

1.7518 GHz RF

, 20 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

0

VDD = 3V, VP = 5V

= 1.875mA

I

–10

CP

PFD FREQUENCY = 20MHz
CHANNEL STEP = 200kHz

–20

LOOP BANDWIDTH = 20kHz
FRACTION = 59/100

–30

RBW = 1kHz

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–72.33dBc@

–400kHz

100kHz

–200kHz 1.7518GHz 200kHz 400kHz

REFERENCE
LEVEL = – 4.2dBm

FREQUENCY

TPC 12. Spurious Plot, Lowest Spur Mode,

1.7518 GHz RF

, 20 MHz PFD Frequency,

OUT

200 kHz Channel Step Resolution

REV. 0–8–

ADF4251

–70

–75

–80

–85

LOWEST SPUR MODE

–90

–95

–100

LOW NOISE AND SPUR MODE

–105

PHASE NOISE – dBc/Hz

LOWEST NOISE MODE

–110

–115

–120

1.430 1.4601.435

1.440 1.445 1.450 1.455

FREQUENCY – GHz

TPC 13. In-Band Phase Noise vs. Frequency

–10

–20

–30

–40

LOWEST NOISE MODE

–50

–60

–70

–80

SPURIOUS LEVEL – dBc

–90

–100

LOWEST SPUR MODE

–110

1.430 1.4601.435

TPC 14. 100 kHz Spur vs. Frequency

1.440 1.445 1.450 1.455
FREQUENCY – GHz

*

–20

–30

–40

–50

–60

LOWEST NOISE MODE

–70

–80

–90

SPURIOUS LEVEL – dBc

–100

–110

LOWEST SPUR MODE

–120

1.430 1.4601.435

*

TPC 16. 400 kHz Spur vs. Frequency

–20

–30

–40

–50

–60

LOWEST NOISE MODE

–70

–80

–90

SPURIOUS LEVEL – dBc

–100

–110

LOWEST SPUR MODE

–120

1.430 1.4601.435

TPC 17. 600 kHz Spur vs. Frequency

1.440 1.445 1.450 1.455
FREQUENCY – GHz

*

1.440 1.445 1.450 1.455
FREQUENCY – GHz

*

–20

–30

–40

–50

–60

LOWEST NOISE MODE

–70

–80

–90

SPURIOUS LEVEL – dBc

–100

–110

LOWEST SPUR MODE

–120

1.430 1.4601.435

1.440 1.445 1.450 1.455
FREQUENCY – GHz

TPC 15. 200 kHz Spur vs. Frequency

*

–20

–30

–40

–50

–60

–70

–80

–90

SPURIOUS LEVEL – dBc

–100

LOWEST NOISE MODE

–110

LOWEST SPUR MODE

–120

1.430 1.4601.435

1.440 1.445 1.450 1.455
FREQUENCY – GHz

TPC 18. 3 MHz Spur vs. Frequency

*TPCs 13–18: Across all fractional channel steps from f = 0/130 to f = 129/130.

RF

= 1.45 GHz, Int Reg = 55, Ref = 26 MHz, and LBW = 40 kHz. TPCs 13–24 attained using EVAL-ADF4252EB2 Evaluation Board.

OUT

REV. 0

–9–

*