Analog Devices ADF4212L a Datasheet

Dual Low Power PLL

Frequency Synthesizer

ADF4212L

FEATURES

Total, 7.5 mA

I

DD

Bandwidth RF/IF, 2.4 GHz/1.0 GHz

2.7 V to 3.3 V Power Supply
Separate VP Allows Extended Tuning Voltage
Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
20-Lead TSSOP and 20-Lead MLF Chip Scale Package

APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless LANS
Cable TV Tuners (CATV)
Communications Test Equipment

FUNCTIONAL BLOCK DIAGRAM

VDD1 VDD2 VP1 VP2

ADF4212L

12-BIT IF

IF

REF

CLOCK

DATA

IN

IN

LE

OSCILLATOR

PRESCALER

22-BIT

DATA

REGISTER

IF

SDOUT

B-COUNTER

6-BIT IF

A-COUNTER

14-BIT IF

R-COUNTER

14-BIT RF

R-COUNTER

GENERAL DESCRIPTION

The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It con­sists of a low noise digital PFD (Phase Frequency Detector), a
precision charge pump, a programmable reference divider,
programmable A and B counters, and a dual modulus prescaler
(P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction
with the dual modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R counter) allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be implemented
if the synthesizer is used with external loop filters and VCOs
(Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire inter­face with 1.8 V compatibility. The devices operate with a power
supply ranging from 2.7 V to 3.3 V and can be powered down
when not in use.

R

SET

IF PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

LOCK

DETECT

IF

RF

REFERENCE

CHARGE

PUMP

IF CURRENT

SETTING

IFCP3 IFCP2 IFCP1

OUTPUT

MUX

RFCP3

RFCP2 RFCP1

REFERENCE

CP

IF

MUXOUT

12-BIT RF

B-COUNTER

RF

IN

RF

PRESCALER

DGND

RF

AGND

6-BIT RF

A-COUNTER

DGNDIFAGND

RF

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

IF

RF PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

REFERENCE

R

SET

FLO SWITCH

CP

FL

RF

O

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADF4212L–SPECIFICATIONS

AGNDIF = DGNDIF = 0 V; TA = T

Parameter B Version Typical Unit Test Conditions/Comments

RF/IF CHARACTERISTICS

RF Input Frequency (RF
RF Input Sensitivity –10/0 –10/0 dBm min/max V
IF Input Frequency (IF
IF Input Sensitivity –10/0 –10/0 dBm min/max VDD = 3 V

MAXIMUM ALLOWABLE

Prescaler Output Frequency

REFIN CHARACTERISTICS See Figure 2 for Input Circuit

REFIN Input Frequency 10/150 10/150 MHz min/max
REFIN Input Sensitivity 500 mV/V

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

ICP Sink/Source Programmable, See Table V

High Value 5 5 mA typ With R
Low Value 625 625 µA typ
Absolute Accuracy 2 2 % typ With R

Range 1.5/5.6 1.5/5.6 kΩ min/max

R

SET

Three-State Leakage Current 1 1 nA max

I

CP

Sink and Source Current Matching 6 6 % typ 0.5 V < V

vs. V

I

CP

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 1.4 V min

INH

, Input Low Voltage 0.6 0.6 V max

V

INL

I

, Input Current ±1 ±1 µA max

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-Drain 1 kΩ Pull-Up to 1.8 V
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

VDD1 2.7/3.3 2.7/3.3 V min/V max

2V

V

DD

VP1, VP2V

(RF and IF)

I

DD

5

RF Only 6 6 mA max 5.0 mA Typical
IF Only 4 4 mA max 2.5 mA Typical

(IP1 + IP2) 0.6 0.6 mA typ

I

P

Low Power Sleep Mode 1 1 µA typ

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
less than this value.

4

Guaranteed by design. Sample tested to ensure compliance.

5

TA = 25°C. RF = 1 GHz. Prescaler = 32/33. IF = 500 MHz. Prescaler = 16/17.

Specifications subject to change without notice.

to T

MIN

, unless otherwise noted; dBm referred to 50 .)

MAX

B Chips

) 0.2/2.4 0.2/2.4 GHz min/max For Operation below F

IN

) 100/1000 100/1000 MHz min/max

IN

3

4

200 200 MHz max

500 mV/VDDV p-p min/max

DD

75 75 MHz max

22 % typ 0.5 V < VCP < VP – 0.5 V

1V

DD

1/5.5 VDD1/5.5 V min/V max

DD

10 10 mA max 7.5 mA Typical

(VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF =

2

, Use a Square Wave

MIN

DD

= 3 V

DD

AC-Coupled. When DC-Coupled,
0 to V

Max (CMOS Compatible)

DD

= 2.7 kΩ

SET

= 2.7 kΩ

SET

< VP – 0.5 V, 2% typ

CP

1

1

REV. A–2–

SPECIFICATIONS

to T

T

MIN

Parameter B Version B Chips

NOISE CHARACTERISTICS

RF Phase Noise Floor

Phase Noise Performance

Spurious Signals

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C

2

The B Chip specifications are given as typical values.

3

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider
value). See TPC 14.

4

The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the
REFIN for the synthesizer (f

5

f

REFIN

6

f

REFIN

7

Same conditions as listed on the preceding line.

8

f

REFIN

9

f

REFIN

Specifications subject to change without notice.

, unless otherwise noted; dBm referred to 50 V.)

MAX

3

4

IF: 540 MHz Output
IF: 900 MHz Output
RF: 900 MHz Output
RF: 1750 MHz Output
RF: 2400 MHz Output

IF: 540 MHz Output
IF: 900 MHz Output
RF: 900 MHz Output
RF: 1750 MHz Output
RF: 2400 MHz Output

= 10 MHz; f
= 10 MHz; f

= 10 MHz; f
= 10 MHz; f

PFD

PFD

PFD

PFD

5

6

6

8

9

5

6

6

8

9

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz
= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz

= 200 kHz; Offset Frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz
= 1 MHz; Offset Frequency = 1 kHz; fRF = 2400 MHz; N = 9800; Loop B/W = 20 kHz

(VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA =

2

Unit Test Conditions/Comments

–170 –170 dBc/Hz typ @ 25 kHz PFD Frequency
–162 –162 dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output
–89 –89 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–87 –87 dBc/Hz typ See Note 7
–89 –89 dBc/Hz typ See Note 7
–84 –84 dBc/Hz typ See Note 7
–87 –87 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
–90/–94 –90/–94 dB typ See Note 7
–90/–94 –90/–94 dB typ See Note 7
–80/–82 –80/–82 dB typ See Note 7
–80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

1

ADF4212L

(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V;

TIMING CHARACTERISTICS*

TA = T

MIN

to T

, unless otherwise noted; dBm referred to 50 .)

MAX

Limit at
T

to T

MIN

MAX

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

*Guaranteed by design but not production tested.

Specifications subject to change without notice.

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

t

t

3

4

CLOCK

t

t

1

2

DATA

DB20 (MSB) DB19 DB2

LE

LE

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

REV. A

Figure 1. Timing Diagram

–3–

ADF4212L

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2, 3

VDD1 to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

V

1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

V

P

V

1, VP2 to VDD1, VDD2 . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

P

Digital I/O Voltage to GND . . . . . . . –0.3 V to DV

Analog I/O Voltage to GND . . . . . . . . –0.3 V to V

REFIN, RFIN, IFIN to GND . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating of

<2 kV, and is ESD sensitive. Proper precautions should be taken for handling and
assembly.

3

GND = AGND = DGND = 0 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

TSSOP ␪
LFCSP ␪
LFCSP ␪

Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance (Paddle Soldered) . . 122°C/W

JA

Thermal Impedance (Paddle Not Soldered) 216°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Model Temperature Range Package Option*

ADF4212LBRU –40°C to +85°C RU-20
ADF4212LBCP –40°C to +85°C CP-20

*RU = Thin Shrink Small Outline Package (TSSOP)

CP = Chip Scale Package (LFCSP)
Contact the factory for chip availability.

ORDERING GUIDE

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4212L features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A–4–

PIN CONFIGURATIONS

FL

O

RF

IN

CP

RF

AGND

RF

DGND

RF

1

2

3

4

5

LE

R

SET

AGND

IF

DGND

IF

11

IF

IN

12

13

14

15

1617181920

CP

IF

V

P

2

V

DD

2

V

P

1

V

DD

1

109876

DATA

CLK

MUXOUT

REF

IN

DGND

IF

ADF4212L

TOP VIEW

(NOT TO SCALE)

ADF4212L

LFCSP

VDD1

CP

DGND

RF

AGND

REF

DGND

UXOUT

V

P

RF

RF

RF

FL

1

2

1

3

4

5

IN

6

7

O

8

IN

9

IF

10

TSSOP

ADF4212L

TOP VIEW

(Not To Scale)

20

19

18

17

16

15

14

13

12

11

VDD2

VP2

CP

IF

DGND

IF

IN

AGND

R

SET

LE
DATA

CLK

IF

IF

PIN FUNCTION DESCRIPTION

Mnemonic Description

CP

RF

RF Charge Pump Output. When enabled, this provides ±ICP to the external RF loop filter, which in turn drives the
external RF VCO.

DGND

RF

IN

AGND

FL

O

REF

IN

RF

RF

Digital Ground Pin for the RF Digital Circuitry.

Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.

Ground Pin for the RF Analog Circuitry.

Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.

DGND

IF

Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.

MUXOUT This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled reference

frequency to be accessed externally.

CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.

LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.

R

SET

AGND

IF

IF

IN

CP

IF

V

2 Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where VDD2 is 3 V, it

P

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The
nominal voltage potential at the R

therefore, with R

= 2.7 kΩ, I

SET

pin is 0.66 V. The relationship between ICP and R

SET

I

CP MAX

= 5 mA for both the RF and IF charge pumps.

CP MAX

13 5.

=

R

SET

SET

is

Ground Pin for the IF Analog Circuitry.

Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.

Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.

can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

V

2Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be

DD

V

DD

V

1 Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where VDD1 is 3 V, it

P

REV. A

1Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible

placed as close as possible to this pin. V
same potential as V

to this pin. V

can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

DD

1.

DD

1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2.

2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the

DD

–5–

ADF4212L–Typical Performance Characteristics

0

= 3V

V

DD

VP = 5V

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

0 500 1000 1500 2000

FREQUENCY – MHz

2500 3000

TPC 1. Input Sensitivity (RF Input)

0

VDD = 3V
V

= 5V

P

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

–35

0 500 1000 1500

FREQUENCY – MHz

TPC 2. Input Sensitivity (IF Input)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE
LEVEL = –3.0dBm

–400k –200k 1.75G 200k 400k

FREQUENCY – Hz

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY =
200kHz
LOOP BANDWIDTH =
20kHz
RES. BANDWIDTH = 1Hz
VIDEO BANDWIDTH = 1Hz
SWEEP = 2.5 SECONDS
AVERAGES = 20

–85.9dB

TPC 4. Reference Spurs, RF Side (1750 MHz,
200 kHz, 20 kHz)

rms NOISE =

= –50dBc/Hz

10dB/DIV

–50

–60

–70

–80

–90

–100

–110

–120

PHASE NOISE – dBc/Hz

–130

–140

–150

100Hz 1MHz

R

L

FREQUENCY OFFSET

FROM 1.75GHz CARRIER

1.38 DEGREES

1.38 rms

TPC 5. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)

0

VDD = 3V, VP = 5V
I

= 5mA

–10

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz

–20

RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz

–30

SWEEP = 1.9 SECONDS
AVERAGES = 22

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2k –1k 1.75G 1k 2k

FREQUENCY – Hz

REFERENCE
LEVEL = –3.2dBm

–84.2dBc/Hz

TPC 3. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE
LEVEL = –4.3dBm

–2k –1k 540M 1k 2k

FREQUENCY – Hz

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 22

–88.8dBc/Hz

TPC 6. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)

REV. A–6–