ANALOG DEVICES ADF4210, ADF4211, ADF4212, ADF4213 Service Manual

a

Dual RF/IF PLL Frequency Synthesizers

ADF4210/ADF4211/ADF4212/ADF4213

FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz

2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode

APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

VDD1VDD2VP1VP2

GENERAL DESCRIPTION

The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro­grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase­Locked Loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5 V and can be powered down when not in use.

R

SET

12-BIT IF

DGND

B-COUNTER

8-BIT IF

A-COUNTER

14-BIT IF

R-COUNTER

R-COUNTER

12-BIT RF

B-COUNTER

6-BIT RF

A-COUNTER

DGND

IF

14-BIT RF

IF

IN

REF

IN

CLOCK

DATA

LE

RF

IN

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

OSCILLATOR

DGND

REGISTER

RF

PRESCALER

24-BIT

DATA

PRESCALER

AGND

IF

SDOUT

RF

RF

PHASE
COMPARATOR

IF

LOCK

DETECT

RF

LOCK

DETECT

PHASE
COMPARATOR

ADF4210/ADF4211/
ADF4212/ADF4213

AGND

IF

IF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

REFERENCE

CHARGE

PUMP

IF CURRENT

SETTING

IFCP3 IFCP2 IFCP1

OUTPUT

MUX

RFCP3 RFCP2 RFCP1

IF CURRENT

SETTING

CHARGE

PUMP

REFERENCE

R

SET

FLO SWITCH

CP

IF

MUXOUT

CP

RF

FL

O

ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS

1

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; R
TA = T

to T

MIN

P

arameter B Version B Chips

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RFIN) See Figure 3 for Input Circuit.

ADF4210 0.1/1.2 0.1/1.2 GHz min/max Use a square wave for frequencies lower than F
ADF4211 0.1/2.0 0.1/2.0 GHz min/max
ADF4212 0.15/2.7 0.15/2.7 GHz min/max

ADF4213 0.2/3.0 0.2/3.0 GHz min/max
RF Input Sensitivity –10/0 –10/0 dBm min/max
IF Input Frequency (IF

ADF4210 60/550 60/550 MHz min/max

ADF4211 60/550 60/550 MHz min/max

ADF4212 0.06/1.0 0.06/1.0 GHz min/max

ADF4213 0.06/1.0 0.06/1.0 GHz min/max
IF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RFIN) See Figure 3 for Input Circuit.

ADF4210 0.18/1.2 0.18/1.2 GHz min/max Use a square wave for frequencies lower than F

ADF4211 0.18/2.0 0.18/2.0 GHz min/max

ADF4212 0.2/2.3 0.2/2.3 GHz min/max

ADF4213 0.2/2.5 0.2/2.5 GHz min/max
RF Input Sensitivity –5/0 –5/0 dBm min/max
IF Input Frequency (IF

ADF4210 100/550 100/550 MHz min/max

ADF4211 100/550 100/550 MHz min/max

ADF4212 0.1/1.0 0.1/1.0 GHz min/max

ADF4213 0.1/1.0 0.1/1.0 GHz min/max
IF Input Sensitivity –5/0 –5/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency

REFIN CHARACTERISTICS See Figure 2 for Input Circuit.

REFIN Input Frequency 0/115 0/115 MHz min/max For F < 5 MHz, use dc-coupled square wave

REFIN Input Sensitivity

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

ICP Sink/Source Programmable: See Table V

High Value 5 5 mA typ With R

Low Value 625 625 µA typ

Absolute Accuracy 3 3 % typ With R

R

SET

Three-State Leakage Current 1 1 nA typ

I

CP

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V

vs. V

I

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

INH

V

INL

I

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

V

, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA

OH

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

unless otherwise noted.)

MAX

2

Unit Test Conditions/Comments

)

IN

3

)

IN

3

4

5

165 165 MHz max

200 200 MHz max

–5/0 –5/0 dBm min/max AC-Coupled. When dc-coupled, 0 to VDD max

55 55 MHz max

Range 1.5/5.6 1.5/5.6 kΩ, min/max

CP

, Input High Voltage 0.8 × DV

, Input Low Voltage 0.2 × DV

2 2 % typ 0.5 V ⱕ VCP ⱕ VP – 0.5 V

DD

DD

0.8 × DV

0.2 × DV

DD

DD

V min
V max

, Input Current ± 1 ± 1 µA max

DD

).

(0 to V

(CMOS-Compatible)

= 2.7 kΩ

SET

= 2.7 kΩ

SET

CP

= 2.7 k dBm to 50 ;

SET

ⱕ VP – 0.5 V

MIN

MIN

.

.

–2–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Parameter B Version B Chips2Un it Test Conditions/Comments

POWER SUPPLIES

V

1 2.7/5.5 2.7/5.5 V min/V max

DD

2V

V

DD

V

P

I

(RF + IF)

DD

6

ADF4210 11.5 11.5 mA max 9.0 mA typical
ADF4211 15.0 15.0 mA max 11.0 mA typical
ADF4212 17.5 17.5 mA max 13.0 mA typical
ADF4213 20 20 mA max 15 mA typical

I

(RF Only)

DD

ADF4210 6.75 6.75 mA max 5.0 mA typical
ADF4211 10 10 mA max 7.0 mA typical
ADF4212 12.5 12.5 mA max 9.0 mA typical
ADF4213 15 15 mA max 11 mA typical

I

(IF Only)

DD

ADF4210 5.5 5.5 mA max 4.5 mA typical
ADF4211 5.5 5.5 mA max 4.5 mA typical
ADF4212 5.5 5.5 mA max 4.5 mA typical
ADF4213 5.5 5.5 mA max 4.5 mA typical

I

1 + IP2) 1.0 1.0 mA max TA = 25°C, 0.55 mA typical

P (IP

Low-Power Sleep Mode 1 1 µA typ

NOISE CHARACTERISTICS

ADF4213 Phase Noise Floor

Phase Noise Performance

ADF4210/ADF4211, IF: 540 MHz Output
ADF4212/ADF4213, IF: 900 MHz Output
ADF4210/ADF4211, RF: 900 MHz Output
ADF4212/ADF4213, RF: 900 MHz Output

7

8

9

10

10

10

ADF4211/ADF4212, RF: 1750 MHz Output
ADF4211/ADF4212, RF: 1750 MHz Output
ADF4212/ADF4213, RF: 2400 MHz Output

Spurious Signals

ADF4210/ADF4211, IF: 540 MHz Output
ADF4212/ADF4213, IF: 900 MHz Output
ADF4210/ADF4211, RF: 900 MHz Output
ADF4212/ADF4213, RF: 900 MHz Output

9

10

10

10

ADF4211/ADF4212, RF: 1750 MHz Output
ADF4211/ADF4212, RF: 1750 MHz Output
ADF4212/ADF4213, RF: 2400 MHz Output14–80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is

less than this value.

4

VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25°C.

5

Guaranteed by design. Sample tested to ensure compliance.

6

VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25°C.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See

TPC 16.

8

The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the

REFIN for the synthesizer (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

Same conditions as listed in Note 10.

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

= 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.

PFD

= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

PFD

= 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.

PFD

= 10 MHz @ 0 dBm).

REFOUT

1V

DD

DD

1

VDD1/6.0 VDD1/6.0 V min/V max VDD1, VDD2 ⱕ VDD1, VDD2 ⱕ 6.0 V

–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–89 –89 dBc/Hz typ See Note 11
–89 –89 dBc/Hz typ See Note 11
–91 –91 dBc/Hz typ See Note 11

12

–85 –85 dBc/Hz typ See Note 11

13

–67 –67 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

14

–88 –88 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
–90/–94 –90/–94 dB typ See Note 11
–90/–94 –90/–94 dB typ See Note 11
–90/–94 –90/–94 dB typ See Note 11

12

–80/–82 –80/–82 dB typ See Note 11

13

–65/–70 –65/–70 dB typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency

REV. A

–3–

ADF4210/ADF4211/ADF4212/ADF4213

WARNING!

ESD SENSITIVE DEVICE

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6 V  10%; AGNDRF = DGND

TIMING CHARACTERISTICS

Limit at

to T

T

Parameter (B Version) Unit Test Conditions/Comments

MIN

t

1

t

2

t

3

t

4

t

5

t

6

NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.

10 ns min DATA to CLOCK Set-Up Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Set-Up Time
20 ns min LE Pulsewidth

CLOCK

DATA

LE

LE

MAX

DB20

(MSB)

= AGNDIF = DGNDIF = 0 V; TA = T

t

3

t

1

t

2

DB19 DB2

to T

MIN

MAX

t

4

(CONTROL BIT C2)

unless otherwise noted.)

DB1

DB0 (LSB)

(CONTROL BIT C1)

t

5

RF

t

6

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V

DD

V

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

P

V

1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . –0.3 V to DV

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB,

IN

A, IFINB to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

IF

IN

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ
CSP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W

JA

1, 2

+ 0.3 V

DD

+ 0.3 V

P

CSP θ

(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per­manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4210BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4210BCP –40°C to +85°C Chip Scale Package CP-20
ADF4211BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4211BCP –40°C to +85°C Chip Scale Package CP-20
ADF4212BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4212BCP –40°C to +85°C Chip Scale Package CP-20
ADF4213BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4213BCP –40°C to +85°C Chip Scale Package CP-20

*Contact the factory for chip availability.

–4–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

PIN FUNCTION DESCRIPTIONS

Pin Number
TSSOP Mnemonic Function

1V

2V

3CP

4 DGND
5RF
6 AGND
7FL
8 REF

9 DGND
10 MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

14 R

15 AGND
16 IF
17 DGND
18 CP

19 VP2 Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where

20 V

1 Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as

DD

close as possible to this pin. V

DD

1 should have a value of between 2.7 V and 5.5 V. VDD1 must have

the same potential as VDD2.

1 Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where

P

RF

V

1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

DD

Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.

RF

IN

RF

O

IN

Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
RF/IF Fastlock Mode.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.

IF

Digital Ground for the IF Digital, Interface and Control Circuitry.

Reference Frequency to be accessed externally.

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.

input is a high impedance CMOS input.

one of the four latches, the latch being selected using the control bits.

SET

IF

IN

IF

IF

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R

13 5.

=

R

SET

= 5 mA for both the RF and IF Charge Pumps.

So, with R

= 2.7 kΩ, I

SET

I

CP MAX

CP MAX

pin is 0.66 V. The relationship between ICP and R

SET

SET

is

Ground Pin for the IF Analog Circuitry.
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input

to an external VCO.

VDD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

2 Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should

DD

be placed as close as possible to this pin. V

DD

2 should have a value of between 2.7 V and 5.5 V. VDD2

must have the same potential as VDD1.

REV. A

VDD1

VP1

CP

DGND

RF

AGND

FL

REF

DGND

MUXOUT

1

2

3

RF

4

RF

5

IN

6

RF

7

O

8

IN

9

IF

10

TSSOP

ADF4210/
ADF4211/
ADF4212/
ADF4213

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

V

DD

2

V

P

CP

IF

DGND

IF

IN

AGND

R

SET

LE

DATA

CLK

PIN CONFIGURATIONS

CP-20

1

2

DD

IF

2

DD

P

V

V

CLK

MUXOUT

IF

CP

DATA

15

DGND

IF

14

IF

IN

13

AGND

IF

12

R

SET

11

LE

1

P

V

2

CP

1

RF

DGND

2

AGND

RF

3

RF

IN

4

RF

FL

5

O

IF

IF

V

20 19 18 17 16

ADF4210/
ADF4211/
ADF4212/
ADF4213

TOP VIEW

(Not to Scale)

6 7 8 9 10

IN

REF

DGND

–5–

ADF4210/ADF4211/ADF4212/ADF4213

–Typical Performance Characteristics

FREQUENCY S11 REAL S11 IMAG

50000000.0

150000000.0

250000000.0

350000000.0

450000000.0

550000000.0

650000000.0

750000000.0

850000000.0

950000000.0

1050000000.0

1150000000.0

1250000000.0

1350000000.0

1450000000.0

1550000000.0

1650000000.0

1750000000.0

1850000000.0

1950000000.0

2050000000.0

0.955683

0.956993

0.935463

0.919706

0.871631

0.838141

0.799005

0.749065

0.706770

0.671007

0.630673

0.584013

0.537311

0.505090

0.459446

0.381234

0.363150

0.330545

0.264232

0.242065

0.181238

–0.052267
–0.112191
–0.185212
–0.252576
–0.323799
–0.350455
–0.408344
–0.455840
–0.471011
–0.535268
–0.557699
–0.604256
–0.622297
–0.642019
–0.686409
–0.693908
–0.679602
–0.721812
–0.697386
–0.711716
–0.723232

FREQUENCY S11 REAL S11 IMAG

2150000000.0

2250000000.0

2350000000.0

2450000000.0

2550000000.0

2650000000.0

2750000000.0

2850000000.0

2950000000.0

0.138086

0.102483

0.054916

0.018475
–0.019935
–0.054445
–0.083716
–0.129543
–0.154974

–0.699896
–0.704160
–0.696325
–0.669617
–0.668056
–0.666995
–0.634725
–0.615246
–0.610398

TPC 1. S-Parameter Data for the ADF4213 RF Input
(Up to 3.0 GHz)

0

–10

REFERENCE
LEVEL = –5.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2kHz –1kHz 900MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–91.2dBc/Hz

TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)

0

–5

VDD = 3V

= 3V

V

P

–10

TA = +85C

–15

TA = +25C

–20

–25

RF INPUT POWER – dBm

TA = –40C

–30

–35

0

123

RF INPUT FREQUENCY – GHz

TPC 4. Input Sensitivity (ADF4213)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.5421

–40

–50

–60

0.54 rms

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,

µ

20 kHz, Typical Lock Time: 400

s)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.6522

–40

–50

–60

0.65 rms

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

TPC 3. ADF4213 Integrated Phase Noise (900 MHz,

µ

200 kHz, 35 kHz, Typical Lock Time: 200

s)

0

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 20

–91.0dBc/Hz

OUTPUT POWER – dB

–10

–20

–30

–40

–50

–60

–70

–80

REFERENCE
LEVEL = –5.7dBm

–90

–100

–400kHz –200kHz

900MHz

200kHz 400kHz

TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

–6–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –5.7dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 25

–90.5dBc/Hz

TPC 7. ADF4213 Reference Spurs (900 MHz,
200 kHz, 35 kHz)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.6

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER 1MHz

1.6 rms

TPC 8. ADF4213 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –8.0dBm

–400Hz –200Hz 1750MHz +200Hz +400Hz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

AVERAGES = 10

–75.2dBc/Hz

TPC 10. ADF4213 Phase Noise (1750 MHz, 30 kHz, 3 kHz)

POWER OUTPUT – dB

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –5.7dBm

–80kHz –40kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK DETECT

MODE

–79.6dBc

1750MHz +40kHz +80kHz

TPC 11. ADF4213 Reference Spurs (1750 MHz,
30 kHz, 3 kHz)

OUTPUT POWER – dB

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 3100MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 45

–86.6dBc/Hz

TPC 9. ADF4213 Phase Noise (2800 MHz, 1 MHz, 100 kHz)

REV. A

–7–

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.7

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER 1MHz

1.7 rms

TPC 12. ADF4213 Integrated Phase Noise (2800 MHz,
1 MHz, 100 kHz)

ADF4210/ADF4211/ADF4212/ADF4213

OUTPUT POWER – dB

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –17.2dBm

–2MHz –1MHz 3100MHz +1MHz +2MHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS

AVERAGES = 1

–80.6dBc

TPC 13. ADF4213 Reference Spurs (2800 MHz, 1 MHz,
100 kHz)

–60

VDD = 3V

= 3V

V

–70

P

–120

–130

–140

–150

–160

PHASE NOISE – dBc/Hz

–170

–180

1 10000100 1000

10

PHASE DETECTOR FREQUENCY – kHz

VDD = 3V
V

= 5V

P

TPC 16. ADF4213 Phase Noise (Referred to CP Output)
vs. PFD Frequency

–60

VDD = 3V

= 5V

V

–70

P

–80

PHASE NOISE – dBc/Hz

–90

–100

–20

TEMPERATURE – C

100–40 0 20 40 60 80

TPC 14. ADF4213 Phase Noise vs. Temperature (900 MHz,
200 kHz, 20 kHz)

–5

–15

–25

–35

–45

–55

–65

–75

–85

FIRST REFERENCE SPUR – dBc

–95

–105

1

TUNING VOLTAGE – Volts

TPC 15. ADF4213 Reference Spurs (200 kHz) vs. V

VDD = 3V

= 5V

V

P

50234

TUNE

(900 MHz, 200 kHz, 20 kHz)

–80

–90

FIRST REFERENCE SPUR – dBc

–100

–20

TEMPERATURE – C

100–40 0 20 40 60 80

TPC 17. ADF4213 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)

–60

VDD = 3V

= 5V

V

–70

–80

PHASE NOISE – dBc/Hz

–90

–100

–20

TEMPERATURE – C

P

100–40 0 20 40 60 80

TPC 18. ADF4213 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)

–8–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

13-BIT B-

COUNTER

5-BIT A-

COUNTER

PRESCALER

P/P + 1

FROM RF

INPUT STAGE

MODULUS

CONTROL

N = BP + A

LOAD

LOAD

TO PFD

–60

VDD = 3V

= 5V

V

–70

–80

–90

FIRST REFERENCE SPUR – dBc

–100

–20

TEMPERATURE – C

P

100–40 0 20 40 60 80

TPC 19. ADF4213 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

100k

NC

REF

SW1

NO

SW2

SW3

NC = NO CONNECT

IN

NC

BUFFER

TO R COUNTER

Figure 2. Reference Input Stage

RF/IF INPUT STAGE

The RF/IF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.

PRESCALER (P/P + 1)

The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF/IF input stage and divides
it down to a manageable frequency for the CMOS A and B
counters in the RF and If sections. The prescaler in both
sections is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. See Tables IV and VI. It is based on a syn­chronous 4/5 core.

RF/IF A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less, when V

= 5 V. Typically,

DD

they will work with 250 MHz output from the prescaler. Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid, but a value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:

f

= [(P × B) + A] × f

VCO

f

= Output Frequency of external voltage controlled

VCO

REFIN

/R

oscillator (VCO).

P = Preset modulus of dual modulus prescaler (8/9,

16/17, etc.).

B = Preset Divide Ratio of binary 13-bit counter

(3 to 8191).

A = Preset Divide Ratio of binary 6-bit A counter

(0 to 63).

f

= External reference frequency oscillator.

REFIN

R = Preset divide ratio of binary 15-bit programmable refer-

ence counter (1 to 32767).

REV. A

RFINA

RF

GENERATOR

B

IN

BIAS

1.6V

2k2k

Figure 3. RF/IF Input Stage

AV

AGND

DD

Figure 4. RF/IF A and B Counters

RF/IF COUNTER

The 15-bit RF/IF R counter allows the input reference fre­quency to be divided down to product the input clock to the
phase frequency detector (PFD). Division ratios from 1 to
32767 are allowed.

–9–

ADF4210/ADF4211/ADF4212/ADF4213

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP

The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a fixed-delay element that sets the width of
the antibacklash pulse. This is typically 3 ns. This pulse ensures
that there is no deadzone in the PFD transfer function and gives
a consistent reference spur level.

V

P

CHARGE

PUMP

CP

CPGND

HI

R DIVIDER

HI

N DIVIDER

R DIVIDER

N DIVIDER

CP OUTPUT

U1

CLR1

CLR2

U2

UP

Q1D1

DELAY

DOWN

Q2D2

U3

Lock Detect

MUXOUT can be programmed for two types of lock detect:
Digital Lock Detect and Analog Lock Detect. Digital Lock
Detect is active high. It is set high when the phase error on three
consecutive Phase Detector cycles is less than 15 ns. It will stay
set high until a phase error of greater than 25 ns is detected on
any subsequent PD cycle. The N-channel open-drain analog
lock detect should be operated with an external pull-up resistor
of 10 kΩ nominal. When lock has been detected, it is high with
narrow low-going pulses.

RF/IF INPUT SHIFT REGISTER

The ADF421x family digital section includes a 24-bit input shift
register, a 14-bit IF R counter and a 18-bit IF N counter, com­prising a 6-bit IF A counter and a 12-bit IF B counter. Also
present is a 14-bit RF R counter and an 18-bit RF N counter,
comprising a 6-bit RF A counter and a 12-bit RF B counter.
Data is clocked into the 24-bit shift register on each rising edge
of CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of four latches on the rising edge of
LE. The destination latch is determined by the state of the two
control bits (C2, C1) in the shift register. These are the two LSBs
DB1, DB0 as shown in the timing diagram of Figure 1. The
truth table for these bits is shown in Table VI. Table I shows a
summary of how the latches are programmed.

Table I. C2, C1 Truth Table

Control Bits
C2 C1 Data Latch

0 0 IF R Counter
0 1 IF AB Counter (A and B)
1 0 RF R Counter
1 1 RF AB Counter (A and B)

Figure 5. RF/IF PFD Simplified Schematic and Timing
(In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF421x family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by P3, P4, P11, and P12. See Tables
III and V. Figure 6 shows the MUXOUT section in block dia­gram form.

DV

DD

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT
IF N COUNTER OUTPUT

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT
RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

DIGITAL LOCK DETECT

CONTROLMUX

MUXOUT

DGND

Figure 6. MUXOUT Circuit

–10–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table II. ADF421x Family Latch Summary

IF R COUNTER LATCH

IF CP CURRENT

SETTING

DOWN

IF POWER-

SETTING

DB21

PRESCALER

DB21

DB21

DB23 DB22

IF

CP2IFCP1IFCP0

GAIN

IF CP

DB23 DB22

RF CP CURRENT

DB23 DB22

RF

CP2RFCP1RFCP0

O

IF F

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CP

PRECISION

THREE-STATE

LOCK DETECT

IF PD

POLARITY

R15

15-BIT REFERENCE COUNTER

IF N COUNTER LATCH

IF

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P6P7P8 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

12-BIT B COUNTER

6-BIT A COUNTER

A1A2A3A4A5A6B12P5

RF R COUNTER LATCH

O

RF

LOCK DETECT

P11P12

CP

RF PD

POLARITY

THREE-STATE

R15

RF F

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

15-BIT REFERENCE COUNTER

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P1P2P3P4

CONTROL

BITS

C2 (0)

CONTROL

BITS

C2 (1)

C1 (1)

C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P9P10

RF

GAIN

RF CP

POWER-

DB23 DB22

P17 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1P16 P15 P14

REV. A

RF N COUNTER LATCH

RF

PRESCALER

DOWN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21

12-BIT B COUNTER

6-BIT A COUNTER

–11–

A1A2A3A4A5A6B12

CONTROL

BITS

C2 (1) C1 (1)

ADF4210/ADF4211/ADF4212/ADF4213

Table III. IF R Counter Latch Map

IF R COUNTER LATCH

IF CP CURRENT

SETTING

DB23 DB22

IF

CP2IFCP1IFCP0

DB21

O

IF F

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CP

PRECISION

THREE-STATE

LOCK DETECT

0 NEGATIVE
1 POSITIVE

IF PD

POLARITY

R15

P1 IF PD POLARITY

R15 R14 R13 .......... R3 R2 R1 DIVIDE RATIO

000..........0011

000..........0102

000..........0113

000..........1004

.................

.................

.................

111..........10032764

111..........10132765

111..........11032766

111..........11132767

15-BIT REFERENCE COUNTER

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P1P2P3P4

P2 CHARGE PUMP OUTPUT

0 NORMAL
1 THREE-STATE

P12 P11
FROM RF R LATCH P4 P3 MUXOUT

0000LOGIC LOW STATE
0001IF ANALOG LOCK DETECT
0010IF REFERENCE DIVIDER OUTPUT
0011IF N DIVIDER OUTPUT
0100RF ANALOG LOCK DETECT
0101RF/IF ANALOG LOCK DETECT
0110IF DIGITAL LOCK DETECT
0111LOGIC HIGH STATE
1000RF REFERENCE DIVIDER OUTPUT
1001RF N DIVIDER OUTPUT
1010THREE-STATE OUTPUT
1011IF COUNTER RESET
1100RF DIGITAL LOCK DETECT
1101RF/IF DIGITAL LOCK DETECT
1110RF COUNTER RESET
1111IF AND RF COUNTER RESET

I

(mA)

IF CP2 IF CP1 IF CP0 1.5k 2.7k 5.6k

0001.0880.6250.294

0012.1761.250.588

0103.2641.8750.882

0114.3522.51.176

1005.443.1251.47

1016.5283.751.764

1107.6164.3752.058

1118.7045.02.352

CP

–12–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table IV. IF N Counter Latch Map

IF N COUNTER LATCH

PRESCALER

GAIN

IF CP

DOWN

IF POWER-

DB23 DB22

DB21

P6P7P8 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

P6 P5 IF PRESCALER

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

P7 IF POWER-DOWN

0 DISABLE
1 ENABLE

IF

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

B12 B11 B10 B3 B2 B1 B COUNTER DIVIDE RATIO

000..........0113

000..........1004

.................

.................

.................

1 1 1 .......... 1 0 0 4092

1 1 1 .......... 1 0 1 4093

1 1 1 .......... 1 1 0 4094

1 1 1 .......... 1 1 1 4095

12-BIT B COUNTER

A COUNTER

A6 A5 .......... A2 A1

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

0 0 .......... 0 0 4

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

6-BIT A COUNTER

C2 (0)

A1A2A3A4A5A6B12P5

DIVIDE RATIO

CONTROL

BITS

C1 (1)

P8 IF CP GAIN

0 DISABLE
1 ENABLE

REV. A

–13–

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

VALUES OF N  F

REF

, N

is (P2 – P).

MIN

ADF4210/ADF4211/ADF4212/ADF4213

Table V. RF R Latch Map

RF R COUNTER LATCH

RF CP CURRENT

SETTING

DB23 DB22

RF

CP2RFCP1RFCP0

DB21

O

RF

RF F

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P11P12

CP

RF PD

POLARITY

THREE-STATE

LOCK DETECT

R15

P9 RF PD POLARITY

0 NEGATIVE
1 POSITIVE

P10 CHARGE PUMP OUTPUT

0 NORMAL
1 THREE-STATE

R15 R14 R13 .......... R3 R2 R1 DIVIDE RATIO

000..........0011

000..........0102

000..........0113

000..........1004

.................

.................

.................

1 1 1 .......... 1 0 0 32764

1 1 1 .......... 1 0 1 32765

1 1 1 .......... 1 1 0 32766

1 1 1 .......... 1 1 1 32767

15-BIT REFERENCE COUNTER

CONTROL

BITS

C2 (1)

C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14P9P10

P12

0000LOGIC LOW STATE
0001IF ANALOG LOCK DETECT
0010IF REFERENCE DIVIDER OUTPUT
0011IF N DIVIDER OUTPUT
0100RF ANALOG LOCK DETECT
0101RF/IF ANALOG LOCK DETECT
0110IF DIGITAL LOCK DETECT
0111LOGIC HIGH STATE
1000RF REFERENCE DIVIDER OUTPUT
1001RF N DIVIDER OUTPUT
1010THREE-STATE OUTPUT
1011IF COUNTER RESET
1100RF DIGITAL LOCK DETECT
1101RF/IF DIGITAL LOCK DETECT
1110RF COUNTER RESET
1111IF AND RF COUNTER RESET

RF CP2 RF CP1 RF CP0 1.5k 2.7k 5.6k

0001.1250.6250.301

0012.251.250.602

0103.3751.8750.904
0 1 1 4.5 2.5 1.205

1005.6253.1251.506

1016.753.751.808

1107.7875 4.375 2.109
1 1 1 9.0 5.0 2.411

FROM IF R LATCH

ICP (mA)

MUXOUTP11 P4 P3

–14–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Table VI. RF N Counter Latch Map

RF N COUNTER LATCH

RF

PRESCALER

GAIN

RF CP

DOWN

RF POWER-

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB23 DB22

P17 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1P16 P15 P14

DB21

P15 P14 PRESCALER

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

P16 RF POWER-DOWN

0 DISABLE
1 ENABLE

B12 B11 B10 B3 B2 B1 B COUNTER DIVIDE RATIO

000..........0113

000..........1004

.................

.................

.................

111..........1004092

111..........1014093

111..........1104094

111..........1114095

12-BIT B COUNTER

A1A2A3A4A5A6B12

A COUNTER

CONTROL

BITS

C2 (1) C1 (1)

6-BIT A COUNTER

A6 A5 .......... A2 A1 DIVIDE RATIO

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

0 0 .......... 0 0 4

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

P17 RF CP GAIN

0 DISABLE
1 ENABLE

REV. A

–15–

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B
MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS

VALUES OF N  F

REF

, N

MIN

is (P2 – P).

ADF4210/ADF4211/ADF4212/ADF4213

PROGRAM MODES

Table III and Table V show how to set up the Program Modes
in the ADF421x family. The following should be noted:

1. IF and RF Analog Lock Detect indicate when the PLL is in
lock. When the loop is locked and either IF or RF Analog
Lock Detect is selected, the MUXOUT pin will show a logic
high with narrow low-going pulses. When the IF/RF Analog
Lock Detect is chosen, the locked condition is indicated only
when both IF and RF loops are locked.

2. The IF Counter Reset mode resets the R and AB counters in
the IF section and also puts the IF charge pump into three­state. The RF Counter Reset mode resets the R and AB
counters in the RF section and also puts the RF charge
pump into three-state. The IF and RF Counter Reset mode
does both of the above. Upon removal of the reset bits, the
AB counter resumes counting in close alignment with the R
counter (maximum error is one prescaler output cycle).

3. The Fastlock mode uses MUXOUT to switch a second loop
filter damping resistor to ground during Fastlock operation.
Activation of Fastlock occurs whenever RF CP Gain in the
RF Reference counter is set to one.

IF Power-Down

It is possible to program the ADF421x family for either synchro­nous or asynchronous power-down on either the IF or RF side.

Synchronous IF Power-Down

Programming a “1” to P7 of the ADF421x family will initiate a
power-down. If P2 of the ADF421x family has been set to “0”
(normal operation), a synchronous power-down is conducted.
The device will automatically put the charge pump into three­state and then complete the power-down.

Asynchronous IF Power-Down

If P2 of the ADF421x family has been set to “1” (three-state the
IF charge pump), and P7 is subsequently set to “1,” an asyn­chronous power-down is conducted. The device will go into
power-down on the rising edge of LE, which latches the “1” to
the IF power-down bit (P7).

Synchronous RF Power-Down

Programming a “1” to P16 of the ADF421x family will initiate a
power-down. If P10 of the ADF421x family has been set to “0”
(normal operation), a synchronous power-down is conducted. The
device will automatically put the charge pump into three-state
and then complete the power-down.

Asynchronous RF Power-Down

If P10 of the ADF421x family has been set to “1” (three-state
the RF charge pump), and P16 is subsequently set to “1,” an
asynchronous power-down is conducted. The device will go into
power down on the rising edge of LE, which latches the “1” to
the RF power-down bit (P16).

Activation of either synchronous or asynchronous power-down
forces the IF/RF loop’s R and AB dividers to their load state
conditions and the IF/RF input section is debiased to a high­impedance state.

The REF

oscillator circuit is only disabled if both the IF and

IN

RF power-downs are set.

The input register and latches remain active and are capable of
loading and latching data during all the power-down modes.

The IF/RF section of the devices will return to normal powered
up operation immediately upon LE latching a “0” to the
appropriate power-down bit.

–16–

IF SECTION

PROGRAMMABLE IF REFERENCE (R) COUNTER

If control bits C2, C1 are 0, 0, the data is transferred from the
input shift register to the 14-bit IFR counter. Table III shows
the input shift register data format for the IFR counter and the
divide ratios possible.

IF Phase Detector Polarity

P1 sets the IF Phase Detector Polarity. When the IF VCO char­acteristics are positive this should be set to “1.” When they are
negative it should be set to “0.” See Table III.

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when pro­grammed to a “1.” It should be set to “0” for normal operation.
See Table III.

IF PROGRAM MODES

Table III and Table V show how to set up the Program Modes
in the ADF421x family.

IF Charge Pump Currents

IFCP2, IFCP1, IFCP0 program current setting for the IF
charge pump. See Table III.

PROGRAMMABLE IF AB COUNTER

If control bits C2, C1 are 0, 1, the data in the input register is used
to program the IF AB counter. The N counter consists of a 6-bit
swallow counter (A counter) and 12-bit programmable counter
(B counter). Table IV shows the input register data format for
programming the IF AB counter and the possible divide ratios.

IF Prescaler Value

P5 and P6 in the IF A, B Counter Latch sets the IF prescaler
value. See Table IV.

IF Power-Down

Table III and Table V show the power-down bits in the
ADF421x family.

IF Fastlock

The IF CP Gain bit (P8) of the IF N register in the ADF421x
family is the Fastlock Enable Bit. Only when this is “1” is IF
Fastlock enabled. When Fastlock is enabled, the IF CP current
is set to its maximum value. Since the IF CP Gain bit is con­tained in the IF N Counter, only one write is needed to both
program a new output frequency and also initiate Fastlock. To
come out of Fastlock, the IF CP Gain bit on the IF N register
must be set to “0.” See Table IV.

RF SECTION

PROGRAMMABLE RF REFERENCE (R) COUNTER

If control bits C2, C1 are 1, 0, the data is transferred from the
input shift register to the 14-bit RFR counter. Table V shows
the input shift register data format for the RFR counter and the
possible divide ratios.

RF Phase Detector Polarity

P9 sets the IF Phase Detector Polarity. When the RF VCO
characteristics are positive this should be set to “1.” When they
are negative it should be set to “0.” See Table V.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when pro­grammed to a “1.” It should be set to “0” for normal operation.
See Table V.

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

RF PROGRAM MODES

Table III and Table V show how to set up the Program Modes
in the ADF421x family.

RF Charge Pump Currents

RFCP2, RFCP1, RFCP0 program current setting for the RF
charge pump. See Table V.

PROGRAMMABLE RF N COUNTER

If control bits C2, C1 are 1, 1, the data in the input register is
used to program the RF N (A + B) counter. The N counter
consists of a 6-bit swallow counter (A Counter) and 12-bit
programmable counter (B Counter). Table IV shows the input
register data format for programming the RF N counter and the
possible divide ratios.

RF Prescaler Value

P14 and P15 in the RF A, B Counter Latch sets the RF pres­caler value. See Table VI.

RF Power-Down

Table III and Table V show the power-down bits in the
ADF421x family.

RF Fastlock

The RF CP Gain bit (P17) of the RF N register in the ADF421x
family is the Fastlock Enable Bit. Only when this is “1” is IF
Fastlock enabled. When Fastlock is enabled, the RF CP current
is set to its maximum value. Also an extra loop filter damping
resistor to ground is switched in using the FL

pin, thus com-

O

pensating for the change in loop characteristics while in Fastlock.
Since the RF CP Gain bit is contained in the RF N Counter, only
one write is needed to both program a new output frequency and
also initiate Fastlock. To come out of Fastlock, the RF CP Gain bit
on the RF N register must be set to “0.” See Table VI.

APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver

Figure 7 shows the ADF4210/ADF4211/ADF4212/ADF4213
being used with a VCO to produce the LO for a GSM base
station transmitter.

The reference input signal is applied to the circuit at FREF

IN

and, in this case, is terminated in 50 Ω. A typical GSM system
would have a 13 MHz TCXO driving the reference input with­out any 50 Ω termination. In order to have a channel spacing of
200 kHz (the GSM standard), the reference input must be
divided by 65, using the on-chip reference.

WIDEBAND PLL

Many of the wireless applications for synthesizers and VCOs in
PLLs are narrowband in nature. These applications include
various wireless standards such as GSM, DSC1800, CDMA, or
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
wideband applications where the local oscillator could have up
to an octave tuning range. For example, cable TV tuners have
a total range of about 400 MHz. Figure 8 shows an applica­tion where the ADF4213 is used to control and program the
Micronetics M3500–1324. The loop filter was designed for an
RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, I

of 10 mA (2.5 mA synthesizer I

CP

CP

multiplied by the gain factor of 4), VCO KD of 80 MHz/V (sen­sitivity of the M3500–1324 at an output of 2100 MHz) and a
phase margin of 45°C.

In narrowband applications, there is generally a small variation
(less than 10%) in output frequency and also a small variation
(typically < 10%) in VCO sensitivity over the range. However,

100pF

100pF

18

18

18

RF

OUT

IF

OUT

100pF

18

18

100pF

18

DECOUPLING CAPACITORS (22F/10PF) ON VDD, VP OF THE
ADF4211/ADF4212/ADF4213 AND ON V
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

51

V

CC

VCO190-

540T

100pF

FREF

620pF

IN

3.3k

5.6k

8.2nF

1.3nF

2.7k

1000pF1000pF

51

OF THE VCOS HAVE

CC

V

VP2

CP

IF

R

SET

RFINB

P

V

DD

VDD2VDD1

REF

ADF4210/
ADF4211/
ADF4212/
ADF4213

RF

RF

AGND

DGND

IN

MUXOUT

IF

DGND

VP1

CP

RF

CLK

IF

DATA

AGND

V

P

620pF

V

CC

VCO190-

902T

51

RF

1.3nF

IN

LE

3.3k

5.6k

8.2nF

LOCK
DETECT

100pF

SPI-COMPATIBLE SERIAL BUS

Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4210/ADF4211/ADF4212/ADF4213

REV. A

–17–

ADF4210/ADF4211/ADF4212/ADF4213

DD

VDD2

IN

ADF4213

RF

DGND

V

VP1VDD1

MUXOUT

RF

AGND

P

CP

RF

IF

DGND

VP2

R

RF

SET

IN

IF

AGND

2.7k

100pF

3.9nF

LOCK
DETECT

20k

27nF

470

51

DECOUPLING CAPACITORS ON VDD, VP OF THE ADF4213,
ON V
HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
THE IF SECTION OF THE CIRCUIT HAS ALSO BEEN OMITTED TO
SIMPLIFY THE SCHEMATIC.

FREF

1000pF

IN

1000pF

51

SPI-COMPATIBLE SERIAL BUS

V

REF

CE
CLK
DATA
LE

Figure 8. Wideband PLL Circuit

in wide-band applications both of these parameters have a much
greater variation. In Figure 8, for example, we have –25% and
+30% variation in the RF output from the nominal 1.8 GHz.
The sensitivity of the VCO can vary from 130 MHz/V at
1900 MHz to 30 MHz/V at 2400 MHz. Variations in these
parameters will change the loop bandwidth. This in turn can
affect stability and lock time. By changing the programmable

, it is possible to obtain compensation for these varying

I

CP

loop conditions and ensure that the loop is always operating
close to optimal conditions.

INTERFACING

The ADF4210/ADF4211/ADF4212/ADF4213 family has a
simple SPI-compatible serial interface for writing to the device.
SCLK, SDATA, and LE control the data transfer. When LE
(Latch Enable) goes high, the 22 bits that have been clocked
into the input register on each rising edge of SCLK will be
transferred to the appropriate latch. See Figure 1 for the Timing
Diagram and Table I for the Latch Truth Table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz, or one update every 1.1 ms. This is certainly more
than adequate for systems that will have typical lock times in
hundreds of microseconds.

ADuC812 to ADF421x Family Interface

Figure 9 shows the interface between the ADF421x family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF421x family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.

On first applying power to the ADF421x family, it needs four
writes (one each to the R counter latch and the AB counter latch
for both RF1 and RF2 sides) for the output to become active.

18

RF

18

18

OUT

20V

3k

1k

AD820

130pF

OF THE AD820 AND ON THE VCC OF THE M3500-1324

CC

12V

V

V_TUNE

M3500-1324

GND

CC

OUT

100pF

100pF

When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be about
180 kHz.

SCLOCK

MOSI

ADuC812

I/O PORTS

SCLK

SDATA

ADF4210/
ADF4211/

LE

ADF4212/
ADF4213

CE

MUXOUT
(LOCK DETECT)

Figure 9. ADuC812 to ADF421x Family Interface

ADSP-21xx to ADF421x Family Interface

Figure 10 shows the interface between the ADF421x family and
the ADSP-21xx Digital Signal Processor. As previously discussed,
the ADF421x family needs a 24-bit serial word for each latch
write. The easiest way to accomplish this, using the ADSP-21xx
family, is to use the Autobuffered Transmit Mode of operation
with Alternate Framing. This provides a means for transmitting
an entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the Autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.

SCLK

SDATA

ADF4210/
ADF4211/

LE

ADF4212/
ADF4213

CE

MUXOUT
(LOCK DETECT)

ADSP-21xx

I/O FLAGS

SCLK

DT

TFS

Figure 10. ADSP-21xx to ADF421x Family Interface

–18–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

20 11

101

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.260 (6.60)

0.252 (6.40)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)
BSC

0.0433 (1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8
0

PCB Guidelines for Chip Scale Package

The lands on the chip scale package (CP-20), are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This will ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be clearance of at least 0.25 mm between the thermal
pad and inner edges of the pad pattern. This will ensure that
shorting is avoided.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Thin Shrink Small Outline Package (TSSOP)

(RU-20)

Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
grid pitch. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via. The user should connect the printed circuit
board pad to AGND.

REV. A

INDICATOR

0.035 (0.90) MAX

0.033 (0.85) NOM

SEATING

PIN 1

12 MAX

PLANE

Chip Scale Package

(CP-20)

0.157 (4.0)
BSC SQ

TOP

VIEW

0.020 (0.50)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

0.148 (3.75)
BSC SQ

0.031 (0.80) MAX

0.026 (0.65) NOM

0.008 (0.20)
REF

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.030 (0.75)

0.022 (0.60)

0.014 (0.50)

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

–19–

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

16

15

11

10

0.080 (2.00)

0.010 (0.25)

BOTTOM

VIEW

REF

MIN

20

6

1

5

0.080 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

ADF4210/ADF4211/ADF4212/ADF4213

Location Page

Data Sheet changed from REV. 0 to REV. A.

Changes to Test Conditions/Comments section of Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edit to RF

PCB Guidelines for Chip Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CP-20 Package replaced by CP-20[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

and IFIN Function text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

IN

–Revision History

C01029–0–6/01(A)

–20–

PRINTED IN U.S.A.

REV. A