ANALOG DEVICES ADF4206, ADF4207, ADF4208 Service Manual

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FEATURES
ADF4206: 550 MHz/550 MHz
ADF4207: 1.1 GHz/1.1 GHz
ADF4208: 2.0 GHz/1.1 GHz

2.7 V to 5.5 V Power Supply
Selectable Charge Pump Supply (VP) Allows Extended

Tuning Voltage in 3 V Systems
Selectable Charge Pump Currents
On-Chip Oscillator Circuit
Selectable Dual Modulus Prescaler

RF2: 32/33 or 64/65

RF1: 32/33 or 64/65
3-Wire Serial Interface
Power-Down Mode

APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

VDD1VDD2V

Dual RF PLL Frequency Synthesizers

ADF4206/ADF4207/ADF4208

GENERAL DESCRIPTION

The ADF4206 family of dual frequency synthesizers can be
used to implement local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
Each synthesizer consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, programmable A and B counters and a dual­modulus prescaler (P/P + 1). The A (6-bit) and B (11-bit)
counters, in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter), allows selectable REFIN frequen­cies at the PFD input. The on-chip oscillator circuitry allows
the reference input to be derived from crystal oscillators.

A complete PLL (Phase-Locked Loop) can be implemented if
the synthesizers are used with an external loop filter and VCOs
(Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V
to 5.5 V and can be powered down when not in use.

1V

P

2

P

N = BP + A

11-BIT RF2

RF1

B-COUNTER

6-BIT RF2

A-COUNTER

14-BIT RF2

R-COUNTER

14-BIT RF1

R-COUNTER

11-BIT RF1

B-COUNTER

6-BIT RF1

A-COUNTER

AGND

A

RF2

RF2

OSC

OSC

CLOCK

DATA

RF1INA

RF1

IN

IN

OUT

B

IN

LE

IN

OSCILLATOR

REGISTER

B

PRESCALER

22-BIT

DATA

N = BP + A

PRESCALER

RF2

SDOUT

RF1

DGND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADF4206/ADF4207/ADF4208

PHASE

COMPARATOR

CHARGE

PUMP

RF2

LOCK

DETECT

OUTPUT

MUX

RF1

LOCK

DETECT

CHARGE

PUMP

PHASE

COMPARATOR

DGND

RF1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

RF2

AGND

RF2

CP

RF2

MUXOUT

CP

RF1

1

ADF4206/ADF4207/ADF4208–SPECIFICATIONS

VDD1, VDD2 ⱕ VP1, VP2 ⱕ 6.0 V; AGND

Parameter B Version B Chips2Unit Test Conditions/Comments

RF/IF CHARACTERISTICS (3 V) See Figure 2 for input circuit.

RF1 Input Frequency (RF1

ADF4206 0.05/0.55 0.05/0.55 GHz min/max
ADF4207 0.08/1.1 0.08/1.1 GHz min/max

ADF4208 0.08/2.0 0.08/2.0 GHz min/max
RF Input Sensitivity –15/+4 –15/+4 dBm min/max
IF Input Frequency (RF2

ADF4206 0.05/0.55 0.05/0.55 GHz min/max

ADF4207/ADF4208 0.08/1.1 0.08/1.1 GHz min/max
IF Input Sensitivity –15/+4 –15/+4 dBm min/max
Maximum Allowable Prescaler Output 165 165 MHz max

Frequency

3

RF CHARACTERISTICS (5 V)

RF1 Input Frequency (RF1

ADF4206 0.05/0.55 0.05/0.55 GHz min/max

ADF4207 0.08/1.1 0.08/1.1 GHz min/max

ADF4208 0.08/2.0 0.08/2.0 GHz min/max
RF Input Sensitivity –10/+4 –10/+4 dBm min/max
IF Input Frequency (RF2

ADF4206 0.05/0.55 0.05/0.55 GHz min/max

ADF4207/ADF4208 0.08/1.1 0.08/1.1 GHz min/max
IF Input Sensitivity –10/+4 –10/+4 dBm min/max
Maximum Allowable Prescaler Output 200 200 MHz max

Frequency

3

REFIN CHARACTERISTICS

REFIN Input Frequency 5/40 5/40 MHz min/max For f < 5 MHz Use Square Wave 0 to V
REFIN Input Sensitivity

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

Sink/Source

I

CP

High Value 5 5 mA typ

Low Value 1.25 1.25 mA typ
Absolute Accuracy 2.5 2.5 % typ
ICP Three-State Leakage Current 1 1 nA typ

LOGIC INPUTS

, Input High Voltage 0.8 × V

V

INH

, Input Low Voltage 0.2 × V

V

INL

, Input Current ± 1 ± 1 µA max

I

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

, Output High Voltage VDD – 0.4 VDD – 0.4 V min IOH = 500 µA

V

OH

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

1 2.7/5.5 2.7/5.5 V min/V max

V

DD

2V

V

DD

V

P

(IDD1 + IDD2)

I

DD

6

ADF4206 14 14 mA max 9.5 mA Typical at VDD = 3 V, TA = 25°C

ADF4207 16.5 16.5 mA max 11 mA Typical at V

ADF4208 21 21 mA max 14 mA Typical at V

1

I

DD

ADF4206 8 8 mA max 5.5 mA Typical at V

ADF4207 9 9 mA max 6 mA Typical at V

ADF4208 14 14 mA max 9 mA Typical at V

2

I

DD

ADF4206 7.5 7.5 mA max 5 mA Typical at V

ADF4207 8.5 8.5 mA max 5.5 mA Typical at V

ADF4208 9 9 mA max 5.5 mA Typical at V

(IP1 + IP2) 1 1 mA max TA = 25°C

I

P

Low-Power Sleep Mode 0.5 0.5 µA typ

) Use a square wave for frequencies lower than f

IN

)

IN

) Use a square wave for frequencies lower than f

IN

) MHz min/max

IN

4

5

= DGND

RF1

= AGND

RF1

= DGND

RF2

= 0 V; TA = T

RF2

MIN

to T

MAX

–2 –2 dBm min AC-Coupled. When DC-Coupled,

0 to V

55 55 MHz max

0.8 × VDDV min

DD

0.2 × VDDV max

DD

1V

DD

DD

1

VDD1/6.0 VDD1/6.0 V min/V max VDD1, VDD2 ⱕ VP1, VP2 ⱕ 6.0 V

(VDD1 = VDD2 = 3 V ⴞ 10%, 5 V ⴞ 10%;

unless otherwise noted, dBm referred to 50 ⍀.)

Max (CMOS-Compatible)

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

= 3 V, TA = 25°C

DD

DD

MIN

MIN

.

.

–2–

REV. 0

ADF4206/ADF4207/ADF4208

Parameter B Version B Chips2Unit Test Conditions/Comments

NOISE CHARACTERISTICS

Phase Noise Floor (RF1)

ADF4206 –169 –169 dBc/Hz typ @ 25 kHz PFD Frequency
ADF4207 –171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
ADF4208 –173 –173 dBc/Hz typ @ 25 kHz PFD Frequency
ADF4206 –160 –160 dBc/Hz typ @ 200 kHz PFD Frequency
ADF4207 –162 –162 dBc/Hz typ @ 200 kHz PFD Frequency
ADF4208 –164 –164 dBc/Hz typ @ 200 kHz PFD Frequency

Phase Noise Performance

ADF4206 (RF1, RF2) –92 –92 dBc/Hz typ @ 540 MHz Output, 200 kHz at PFD
ADF4207 (RF1, RF2) –90 –90 dBc/Hz typ @ 900 MHz Output, 200 kHz at PFD
ADF4207 (RF1, RF2)
ADF4208 (RF1) –85 –85 dBc/Hz typ @ 1750 MHz Output, 200 kHz at PFD
ADF4208 (RF1) –91 –91 dBc/Hz typ @ 900 MHz Output, 200 kHz at PFD
ADF4208 (RF1)
ADF4208 (RF2) –89 –89 dBc/Hz typ @ 900 MHz Output, 200 kHz at PFD

Spurious Signals

RF1, RF2

(20 kHz Loop B/W) –80/–84 –80/–84 dB typ @ 200 kHz/400 kHz and 200 kHz PFD

RF1, RF2 (1 kHz Loop B/W) –65/–73 –65/–73 dB typ @10 kHz/20 kHz and 10 kHz PFD

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is

less than this value.

4

VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels.

5

Guaranteed by design. Sample tested to ensure compliance.

6

Typical values apply for VDD = 3 V; P = 32; RF1IN1/RF2IN2 for ADF4206 = 540 MHz; RF1IN1/RF2IN2 for ADF4207 = 900 MHz; RF1IN1/RF2IN2 for ADF4208 = 900 MHz.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

8

The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation

Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

PFD

PFD

7

8

9

10

= 30 kHz; Offset Frequency = 300 Hz; f
= 10 kHz; Offset Frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

–81 –81 dBc/Hz typ @ 836 MHz, 30 kHz at PFD

–66 –66 dBc/Hz typ @ 1750 MHz Output, 200 kHz at PFD

= 836 MHz; N = 27866; Loop B/W = 3 kHz.

RF/IF

@ VCO Output

REFOUT

= 10 MHz @ 0 dBm).

REV. 0

–3–

ADF4206/ADF4207/ADF4208

TIMING CHARACTERISTICS

Limit at

to T

T

Parameter (B Version) Unit Test Conditions/Comments

MIN

t

1

t

2

t

3

t

4

t

5

t

6

NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

MAX

(VDD1 = VDD2 = 3 V ⴞ 10%, 5 V ⴞ 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGND
AGND

= DGND

RF2

= 0 V; TA = T

RF2

MIN

to T

unless otherwise noted, dBm referred to 50 ⍀.)

MAX

= DGND

RF1

RF1

=

CLOCK

t

1

2

DB20 DB2

DATA

LE

t

DB21 (MSB)

LE

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted.)

1, 2

VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

V

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

P

1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

V

P

Digital I/O Voltage to GND . . . . . . –0.3 V to DV

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

, OSC

OSC

IN

RF2

RF

A to RFINB (RF1, RF2) . . . . . . . . . . . . . . . . . . ±320 mV

IN

OUT

(A, B) to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

IN

, RF1

(A, B),

IN

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

3

t

4

(CONTROL BIT C2)

CSP θ
CSP θ

DB1

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W

JA

(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W

JA

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

t

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4206BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4207BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4208BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20

*Contact the factory for chip availability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although

WARNING!

the ADF4206/ADF4207/ADF4208 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

ESD SENSITIVE DEVICE

REV. 0

ADF4206/ADF4207/ADF4208

PIN FUNCTION DESCRIPTIONS

Mnemonic
Pin ADF4206/
No. ADF4207 ADF4208 Function

1V

2V
3CP

4 DGND
5 RF1
6 OSC

7OSC

1V

DD

1V

P

RF1

RF1

IN

IN

OUT

8 MUXOUT OSC

9 CLK OSC
10 DATA MUXOUT This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled

11 LE CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The

12 RF2

13 DGND

14 CP
15 V

16 V

IN

RF2

RF2

2 RF2INB Complementary Input to the RF2 Prescaler. This point should be decoupled to the ground

P

2 RF2INA Input to the RF2 Prescaler. This low-level input signal is normally ac-coupled to the

DD

17 DGND
18 CP

19 V
20 V

1 Positive Power Supply for the RF1 Section. A 0.1 µF capacitor should be connected between

DD

1 Power Supply for the RF1 Charge Pump. This should be greater than or equal to VDD.

P

CP

RF1

this pin and the RF1 ground pin, DGND

5.5 V. V

1 must have the same potential as VDD2.

DD

. VDD1 should have a value of between 2.7 V and

RF1

Output from the RF1 Charge Pump. This is normally connected to a loop filter which, in
turn, drives the input to an external VCO.

DGND

RF1

Ground Pin for the RF1 Digital Circuitry.
RF1INA Input to the RF1 Prescaler. This low-level input signal is normally taken from the RF1 VCO.
RFINB Complementary Input to the RF1 Prescaler of the ADF4208. This point should be decoupled to

the ground plane with a small bypass capacitor.
AGND

IN

RF1

Ground Pin for the RF1 Analog Circuitry.

Oscillator Input. It has a VDD/2 threshold and can be driven from an external CMOS or TTL

logic gate.

OUT

Oscillator Output.

Reference Frequency to be accessed externally. See Table V.

data is latched into the 22-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.
DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control

bits. This input is a high impedance CMOS input.
LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is

loaded into one of the four latches, the latch being selected using the control bits.
AGND

RF2

Ground Pin for the RF2 Analog Circuitry.

plane with a small bypass capacitor.

external VCO.

RF2

RF2

Ground Pin for the RF2, Digital, Interface, and Control Circuitry.

Output from the RF2 Charge Pump. This is normally connected to a loop filter that drives

the input to an external VCO.

2 Power Supply for the RF2 Charge Pump. This should be greater than or equal to VDD.

P

2 Positive Power Supply for the RF2, Interface, and Oscillator Sections. A 0.1 µF capacitor

DD

should be connected between this pin and the RF2 ground Pin, DGND

. VDD2 should

RF2

have a value between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.

REV. 0

VDD1

V

CP

DGND

RF1

OSC

OSC

OUT

MUXOUT

RF1

RF1

1

P

N

I

IN

TSSOP

1

2

ADF4206/

3

ADF4207

4

5

TOP VIEW

6

(Not to Scale)

7

8

16

15

14

13

12

11

10

9

V

DD

V

2

P

CP

RF2

DGND

RF2

LE

DATA

CLK

PIN CONFIGURATIONS

TSSOP

VDD1

RF1

RF1

OSC

CP

OSC

VP1

RF1

RF1

N

I

N

I

RF1

OUT

A

B

IN

1

2

3

4

ADF4208

5

6

7

TOP VIEW

(Not to Scale)

8

9

10

2

RF2

IN

DGND

AGND

MUXOUT

20

19

18

17

16

15

14

13

12

11

V

DD

2

V

P

CP

RF2

DGND

RF2

RF2

AGND

LE

DATA

CLK

2

RF2

A

N

I

B

N

I

RF2

–5–

ADF4206/ADF4207/ADF4208

–Typical Performance Characteristics

FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
GHz S MA R 50

FREQ MAGS11 ANGS11

0.0 0.957111193 –3.130429321

0.15 0.963546793 –6.686426265

0.25 0.953621785 –11.19913586

0.35 0.953757706 –15.35637483

0.45 0.929831379 –20.3793432

0.55 0.908459709 –22.69144845

0.65 0.897303634 –27.07001443

0.75 0.876862863 –31.32240763

0.85 0.849338092 –33.68058163

0.95 0.858403269 –38.57674885

1.05 0.841888714 –41.48606772

1.15 0.840354983 –45.97597958

1.25 0.822165839 –49.19163116

FREQ MAGS11 ANGS11

1.35 0.816886959 –51.80711782

1.45 0.825983016 –56.20373378

1.55 0.791737125 –61.21554647

1.65 0.770543186 –61.88187496

1.75 0.793897072 –65.39516615

1.85 0.745765233 –69.24884474

1.95 0.7517547 –71.21608147

2.05 0.745594889 –75.93169947

2.15 0.713387801 –78.8391674

2.25 0.711578577 –81.71934806

2.35 0.698487131 –85.49067481

2.45 0.669871818 –88.41958754

2.55 0.668353367 –91.70921678

TPC 1. S-Parameter Data for the AD4208 RF1 Input
(Up to 2.5 GHz)

0

VDD = 5V
VP = 5V

–5

–10

–15

–20

–25

RF INPUT POWER – dBm

–30

–35

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

TA = +85ⴗC

TA = –40ⴗC

TA = +25ⴗC

RF INPUT SENSITIVITY – GHz

TPC 2. Input Sensitivity for the ADF4208 (RF1)

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

–400k

REFERENCE LEVEL =

–4.2dBm

–200k 900M 200k

FREQUENCY – Hz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

–90.2dBc/Hz

400k

TPC 4. ADF4208 RF1 Reference Spurs (900 MHz,
200 kHz, 20 kHz)

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

10dB/DIVISION

R

= –40dBc/Hz

L

rms NOISE = 0.52ⴗ

0.52ⴗ rms

TPC 5. ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 20 kHz)

OUTPUT POWER – dB

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

REFERENCE LEVEL =

–4.2dBm

–2k

–1k 900M 1k

FREQUENCY – Hz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19

–90.5dBc/Hz

2k

TPC 3. ADF4208 RF1 Phase Noise (900 MHz, 200 kHz,
20 kHz)

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

10dB/DIVISION

R

= –40dBc/Hz

L

rms NOISE = 0.62ⴗ

0.62ⴗ rms

TPC 6. ADF4208 RF1 Integrated Phase Noise (900 MHz,
200 kHz, 35 kHz)

–6–

REV. 0