Analog Devices ADF4154 Datasheet

Fractional-N Frequency Synthesizer

FEATURES

RF bandwidth 500 MHz to 4 GHz

2.7 V to 3.3 V power supply
Separate V
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/

ADF4112/ADF4113, ADF4106 and ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
Fast-lock mode with built-in timer

APPLICATIONS

CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment

allows extended tuning voltage

P

ADF4154

GENERAL DESCRIPTION

The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a Σ-Δ based fractional interpolator to allow program­mable fractional-N division. The INT, FRAC, and MOD regis­ters define an overall N divider (N = (INT + (FRAC/MOD))).
In addition, the 4-bit reference counter (R counter) allows
selectable REF
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and a voltage controlled
oscillator (VCO).

A key feature of the ADF4154 is the fast-lock mode with a built­in timer. The user can program a predetermined count-down
time value so that the PLL will remain in wide bandwidth mode,
instead of having to control this time externally.

Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to

3.3 V, and can be powered down when not in use.

frequencies at the PFD input. A complete

IN

FUNCTIONAL BLOCK DIAGRAM

REF

IN

HIGH Z

MUXOUT

CLOCK

DATA

LE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

×2

DOUBLER

OUTPUT

MUX

24-BIT

DATA

REGISTER

AGND

V

DD

DGND

V

DD

R

DIV

N

DIV

4-BIT

R COUNTER

LOCK

DETECT

FAST-LOCK

SWITCH

THIRD ORDER

FRACTIONAL

INTERPOLATOR

FRACTION

REG

DGND CPGND

AV

DD

Figure 1.

DV

DDVP

MODULUS

REG

SDV

DD

+

PHASE

FREQUENCY

DETECTOR

–

N COUNTER

INTEGER REG

P = 4/5 OR 8/9

B = 9 BITS; A = 3 BITS

R

SET

REFERENCE

CHARGE

PUMP

CURRENT

SETTING

RFCP3 RFCP2 RFCP1

CP

RFINA
RF

IN

B

ADF4154

04833-0-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF4154

TABLE OF CONTENTS

Specifications..................................................................................... 3

R-Divider Register, R1 ............................................................... 15

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Pin Function Descriptions...................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

RF Input Stage............................................................................... 9

RF INT Divider............................................................................. 9

INT, FRAC, MOD, and R Relationship...................................... 9

RF R Counter ................................................................................ 9

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Registers................................................................... 10

Program Modes .......................................................................... 10

Control Register, R2................................................................... 15

Noise and Spur Register, R3 ...................................................... 16

Reserved Bits............................................................................... 16

RF Synthesizer: A Worked Example ........................................ 16

Modulus....................................................................................... 17

Reference Doubler and Reference Divider ............................. 17

12-Bit Programmable Modulus................................................ 17

Spurious Optimization and Fast-lock...................................... 17

Fast-Lock Timer and Register Sequences ............................... 17

Fast-Lock: A Worked Example ................................................. 18

Fast-Lock: Loop Filter Topology .............................................. 18

Spurious Signals.......................................................................... 18

Filter Design—ADIsimPLL....................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for Chip Scale Package .................... 19

Registers........................................................................................... 11

Register Definition ..................................................................... 15

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Rev. 0 | Page 2 of 20

ADF4154

SPECIFICATIONS

Table 1. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
noted; dBm referred to 50 Ω. The operating temperature for the B version is −40°C to +80°C.

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V)

Figure 18 for input circuit.

See

RF Input Frequency (RFIN)1 0.5/4.0 GHz min/max −8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/µs.

1.0/4.0 GHz min/max −10 dBm/0 dBm min/max.

REFERENCE CHARACTERISTICS See Figure 17 for input circuit.

REFIN Input Frequency1

10/250 MHz min/max

For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate >
21 V/µs.

REFIN Input Sensitivity 0.7/AVDD V p-p

AC-coupled.

min/max
0 to AVDD V max CMOS compatible.
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 µA max

PHASE DETECTOR

Phase Detector Frequency2 32 MHz max

CHARGE PUMP

ICP Sink/Source Programmable. See Table 5.

High Value 5 mA typ With R

= 5.1 kΩ.

SET

Low Value 312.5 µA typ
Absolute Accuracy 2.5 % typ With R
R

Range 1.5/10 kΩ min/max

SET

= 5.1 kΩ.

SET

ICP Three-State Leakage Current 1 nA typ Sink and source current.
Matching 2 % typ 0.5 V < VCP < VP – 0.5.
ICP vs. VCP 2 % typ 0.5 V < VCP < VP – 0.5.
ICP vs. Temperature 2 % typ VCP = VP/2.

LOGIC INPUTS

V

, Input High Voltage 1.4 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V.
VOL, Output Low Voltage 0.4 V max IOL = 500 µA.

POWER SUPPLIES

AVDD 2.7/3.3 V min/V max
DVDD, SDVDD AVDD
VP AVDD/5.5 V min/V max

3

I

24 mA max 20 mA typical.

DD

Low Power Sleep Mode 1 µA typ

NOISE CHARACTERISTICS

Phase Noise Figure of Merit4 −213 dBc/Hz typ
ADF4154 Phase Noise Floor5 −143 dBc/Hz typ @ 10 MHz PFD frequency.

−139 dBc/Hz typ @ 26 MHz PFD frequency.
Phase Noise Performance6 @ VCO output.

1750 MHz Output7 −102 dBc/Hz typ @ 1 kHz offset, 26 MHz PFD frequency.

1

Use a square wave for frequencies below f

2

Guaranteed by design. Sample tested to ensure compliance.

3

AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 17

4

This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(f

at the VCO output. The value given is the lowest noise mode.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).

The value given is the lowest noise mode.

6

The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer.

7

f

REFIN

= 26 MHz; f

= 26 MHz; offset frequency = 1 kHz; RF

PFD

.

MIN

) + 20logN to calculate in-band phase noise performance, as seen

PFD

= 1750 MHz; loop B/W = 20 kHz; lowest noise mode.

OUT

MIN

to T

, unless otherwise

MAX

Rev. 0 | Page 3 of 20

ADF4154

TIMING CHARACTERISTICS

Table 2. AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
noted; dBm referred to 50 Ω.

Parameter1 Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

1

Guaranteed by design, but not production tested.

CLOCK

t

4

t

5

MIN

to T

, unless otherwise

MAX

DATA

LE

LE

t

2

DB23 (MSB) DB22 DB2

t

1

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

04833-0-026

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 20

ADF4154

ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings.

1, 2, 3

TA = 25°C, unless

otherwise noted.

Parameter Rating

VDD to GND −0.3 V to +4 V
VDD to VDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to VDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
LFCSP θJA Thermal Impedance

122°C/W

(Paddle Soldered)

LFCSP θJA Thermal Impedance

216°C/W

(Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

1

This device is a high performance RF integrated circuit with an ESD rating of

< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.

2

GND = A

3

VDD = AVDD = DVDD = SDVDD.

GND

= D

GND

= 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 20

ADF4154

D

D

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

D

D

1

R

SET

CP

CPGND 3

AGND
RFINB 5
RFINA

AV

DD

REF

IN

2

ADF4154

4

TOP VIEW

(Not to Scale)

6
7
8

16
15
14
13
12
11
10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
SDV

DD

DGND

04833-0-002

CPGND

AGND
AGND
RF

IN

RFINA

1
2
3
4

B

5

Figure 3. TSSOP Pin Configuration

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TSSOP LFCSP Mnemonic Description

1 19 R

2 20 CP

SET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I

525I.

=

CP

max

R

SET

where R

= 5.1 kΩ and I

SET

Charge Pump Output. When enabled, this provides ±I

CPmax

and R

CP

= 5 mA.

SET

is

to the external loop filter, which in turn drives

CP

the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF (see Figure 18).
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD

8 8 REFIN

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AV

as DV

.

DD

has a value of 3 V ± 10%. AVDD must have the same voltage

DD

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it

can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 SDVDD

11 12 CLK

Σ-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to

this pin. SDV

has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.

DD

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a

high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.
15 16, 17 DVDD

16 18 VP

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV

voltage as AV

.

DD

has a value of 3 V ± 10%. DVDD must have the same

DD

Charge Pump Power Supply. This should be greater than or equal to V

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

SET

CP

R

VPDV

DV

20

191817

16

15

9

10

DGND

DGND

MUXOUT

14

LE

13

DATA

12

CLK
SDV

11

DD

PIN 1
INDICATOR

ADF4154

TOP VIEW

678

IN

DD

AVDDAV

REF

/2 and an equivalent input

DD

. In systems where VDD is 3 V, it

DD

04833-0-003

Rev. 0 | Page 6 of 20