ANALOG DEVICES ADF4153 Service Manual

A

V

A

www.BDTIC.com/ADI

Fractional-N Frequency Synthesizer

FEATURES

RF bandwidth to 4 GHz

2.7 V to 3.3 V power supply
Separate V
Y version available: −40°C to +125°C
Programmable fractional modulus
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113

and ADF4106
Consistent RF output phase
Loop filter design possible with ADIsimPLL

APPLICATIONS

CATV equipment
Base stations for mobile radio (GSM, PCS, DCS, WiMAX,

SuperCell 3G, CDMA, W-CDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA)
Wireless LANs, PMR
Communications test equipment

allows extended tuning voltage

P

ADF4153

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer
that implements local oscillators in the upconversion
and downconversion sections of wireless receivers and
transmitters. It consists of a low noise digital phase
frequency detector (PFD), a precision charge pump, and
a programmable reference divider. There is a Σ-Δ based
fractional interpolator to allow programmable fractional-N
division. The INT, FRAC, and MOD registers define an
overall N divider (N = (INT + (FRAC/MOD))). In addition,
the 4-bit reference counter (R counter) allows selectable
REFIN frequencies at the PFD input. A complete phase­locked loop (PLL) can be implemented if the synthesizer is
used with an external loop filter and a voltage controlled
oscillator (VCO).

A simple 3-wire interface controls all on-chip registers.
The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

DDVP

SDV

DD

DV

DD

ADF4153

REF

MUXOUT

CLK

DATA

IN

HIGH-Z

LE

×2

DOUBLER

OUTPUT

MUX

24-BIT

DATA

REGISTER

V
DGND

V
R
N

AGND

4-BIT

R COUNTER

DD

LOCK

DD
DIV

DIV

DETECT

THIRD ORDER

FRACTIONAL

INTERPOLATOR

REG

MODULUS

REG

FRACTION

DGND CPGND

+

PHASE

FREQUENCY

DETECTOR

–

N-COUNTER

INTEGER

REG

Figure 1.

R

SET

REFERENCE

CHARGE

PUMP

CURRENT

SETTING

RFCP3 RFCP2 RFCP1

CP

RF

IN

RFINB

03685-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2003–2008 Analog Devices, Inc. All rights reserved.

ADF4153

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description ........................................................................... 8

Reference Input Section ............................................................... 8

RF Input Stage ............................................................................... 8

RF INT Divider ............................................................................. 8

INT, FRAC, MOD, and R Relationship ..................................... 8

RF R Counter ................................................................................ 8

Phase Frequency Detector (PFD) and Charge Pump .............. 9

MUXOUT and Lock Detect ........................................................ 9

Input Shift Registers ..................................................................... 9

Program Modes ............................................................................ 9

REVISION HISTORY

10/08—Rev. B to Rev. C

Added Y Version (Throughout) ..................................................... 1

Changes to Ordering Guide .......................................................... 23

08/05—Rev. A to Rev. B

Changes to Features .......................................................................... 1

Changes to Applications .................................................................. 1

Changes to Specifications ................................................................ 3

Changes to Absolute Maximum Ratings ....................................... 5

Changes to Figure 7 to Figure 9 ...................................................... 7

Deleted Figure 8 to Figure 10; Renumbered Sequentially ........... 8

Deleted Figure 11 and Figure 14; Renumbered Sequentially ..... 9

Changes to Table 9 .......................................................................... 13

Added Initialization Sequence Section ........................................ 17

Changes to Fastlock with Spurious Optimization Section........ 18

Inserted Figure 16; Renumbered Sequentially ............................ 18

Added Spur Mechanisms Section ................................................. 18

Added Table 11; Renumbered Sequentially ................................ 18

Added Spur Consistency Section ................................................. 19

N Divider Register, R0 ............................................................... 15

R Divider Register, R1 ................................................................ 15

Control Register, R2 ................................................................... 15

Noise and Spur Register, R3 ...................................................... 16

Reserved Bits ............................................................................... 16

Initialization Sequence .............................................................. 17

RF Synthesizer: A Worked Example ........................................ 17

Modulus ....................................................................................... 17

Reference Doubler and Reference Divider ............................. 17

12-Bit Programmable Modulus ................................................ 17

Fastlock with Spurious Optimization ...................................... 18

Spur Mechanisms ....................................................................... 18

Spur Consistency ........................................................................ 19

Phase Resync ............................................................................... 19

Filter Design—ADIsimPLL ....................................................... 19

Interfacing ................................................................................... 19

PCB Design Guidelines for Chip Scale Package .................... 20

Applications Information .............................................................. 21

Local Oscillator for a GSM Base Station Transmitter ........... 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Changes to Phase Resync Section ................................................ 19

Inserted Figure 17; Renumbered Sequentially ........................... 19

Deleted Spurious Signals—

Predicting Where They Will Appear Section ............................. 20

Changes to Figure 19 ...................................................................... 20

Changes to Figure 20 ...................................................................... 21

Added Applications Section .......................................................... 21

Changes to Figure 22 Caption ...................................................... 22

Changes to Ordering Guide .......................................................... 22

1/04—Rev. 0 to Rev. A

Renumbered Figures and Tables ...................................... Universal

Changes to Specifications ................................................................. 3

Changes to Pin Function Description ............................................ 7

Changes to RF Power-Down Section ........................................... 17

Changes to PCB Design Guidelines for Chip Scale

Package Section............................................................................... 21

Updated Outline Dimensions ....................................................... 22

Updated Ordering Guide .............................................................. 22

7/03—Revision 0: Initial Version

Rev. C | Page 2 of 24

ADF4153

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
dBm referred to 50 Ω.

Table 1.

Parameter B Version1Y Version2Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V) See Figure 12 for input circuit

RF Input Frequency (RFIN) 0.5/4.0 0.5/4.0 GHz min/max B Version: −8 dBm minimum/0 dBm maximum

0.5/4.0 0.5/4.0 GHz min/max Y Version: −6.5 dBm minimum/0 dBm maximum
For lower frequencies, ensure slew rate (SR) > 400 V/μs

1.0/4.0 1.0/4.0 GHz min/max −10 dBm/0 dBm minimum/maximum
REFERENCE CHARACTERISTICS See Figure 11 for input circuit

REFIN Input Frequency 10/250 10/250 MHz min/max

For f < 10 MHz, use a dc-coupled, CMOS-compatible

square wave; slew rate > 25 V/μs
REFIN Input Sensitivity 0.7/AVDD 0.7/AVDD V p-p min/max Biased at AVDD/2
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 μA max

PHASE DETECTOR

Phase Detector Frequency

4

32 32 MHz max

CHARGE PUMP

ICP Sink/Source Programmable; see Table 5

High Value 5 5 mA typ With R
Low Value 312.5 312.5 μA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 1.5/10 1.5/10 kΩ min/max

SET

ICP Three-State Leakage Current 1 4.5 nA typ Sink and source current
Matching 2 2 % typ 0.5 V < VCP < VP – 0.5
ICP vs. VCP 2 2 % typ 0.5 V < VCP < VP – 0.5
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 1.4 V min

INH

V

, Input Low Voltage 0.6 0.6 V max

INL

I

, Input Current ±1 ±1 μA max

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 2.7/3.3 2.7/3.3 V min/V max
DVDD, SDVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/V max
IDD 24 24 mA max 20 mA typical
Low Power Sleep Mode 1 1 μA typ

NOISE CHARACTERISTICS

Normalized Phase Noise Floor
Phase Noise Performance
1750 MHz Output

1

Operating temperature for B version is: −40°C to +85°C.

2

Operating temperature for Y version is: −40°C to +125°C.

3

AC coupling ensures AVDD/2 bias.

4

Guaranteed by design. Sample tested to ensure compliance.

5

The number here can be used to calculate phase noise for any application. Use the formula –213 + 10 log(F

as seen at the VCO output. The value given is the lowest noise mode.

6

The phase noise is measured with the EVAL-ADF4153EBZ1 evaluation board and the Agilent E5500 phase noise system.

7

f

= 100 MHz; F

REFIN

7

−102 −102 dBc/Hz typ @ 5 kHz offset, 25 MHz PFD frequency

= 25 MHz; offset frequency = 5 kHz; RF

PFD

5

−213 −213 dBc/Hz typ

6

@ VCO output

= 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.

OUT

to T

MIN

= 5.1 kΩ

SET

= 5.1 kΩ

SET

) + 20 logN to calculate in-band phase noise performance

PFD

, unless otherwise noted;

MAX

3

Rev. C | Page 3 of 24

ADF4153

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TIMING SPECIFICATIONS

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
dBm referred to 50 Ω.

Table 2.

Parameter Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

t

CLK

t

4

5

MIN

to T

, unless otherwise noted;

MAX

DATA

LE

LE

t

2

DB23 (MSB) DB22 DB2

t

1

t

3

Figure 2. Timing Diagram

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

03685-026

Rev. C | Page 4 of 24

ADF4153

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, GND = AGND = DGND = 0 V,
V

= AVDD = DVDD = SDVDD, unless otherwise noted.

DD

Table 3.

Parameter Rating

VDD to GND −0.3 V to +4 V
VDD to VDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to VDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Extended (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 112°C/W
LFCSP θJA Thermal Impedance

(Paddle Soldered)

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 40 sec

Maximum Junction Temperature 150°C

30.4°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

Rev. C | Page 5 of 24

ADF4153

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

T

DD

DD

SE

P

DV

R

CP

V

1

R

SET

2

CP

3

CPGND

AGND
RF
RFINA

AV

REF

IN

DD

B

IN

ADF4153

TOP VIEW

4

(Not to Scale)

5

6

7

8

Figure 3. TSSOP Pin Configuration

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
SDV

DD

DGND

1CPGND
2AGND
3AGND

B

4RF

IN

A

5RF

IN

03685-002

Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
TSSOP

1 19 R

2 20 CP

Pin No.
LFCSP

Mnemonic Description

SET

Connecting a resistor between R
The relationship between I

I

=

CPMAX

where R

= 5.1 kΩ and I

SET

Charge Pump Output. When enabled, CP provides ±I

and ground sets the maximum charge pump output current.

SET

and R

CP

5.25

R

SET

CPMAX

SET

= 5 mA.

is

to the external loop filter, which in turn

CP

drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the RF Prescaler. This pin should be decoupled to the ground plane

with a small bypass capacitor, typically 100 pF (see Figure 12).
6 5 RFINA Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD

8 8 REFIN

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. AV

voltage as DV

.

DD

has a value of 3 V ± 10%. AVDD must have the same

DD

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ (see Figure 11). This input can be driven from a TTL or CMOS crystal oscillator,

or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 SDVDD

11 12 CLK

Σ-Δ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible

to this pin. SDV

has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.

DD

Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is

latched into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is

a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one

of four latches; the latch is selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be externally accessed.
15 16, 17 DVDD

16 18 VP

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

the same voltage as AV

.

DD

has a value of 3 V ± 10%. DVDD must have

DD

Charge Pump Power Supply. This should be greater than or equal to V

it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

DV

16

17

19

20

18

PIN 1
INDICATOR

ADF4153

TOP VIEW

(Not to Scale)

8

6

7

IN

DD

DD

AV

AV

REF

/2 and an equivalent input

DD

DD

15 MUXOUT
14 LE
13 DATA
12 CLK
11 SDV

9

10

DGND

DGND

. In systems where VDD is 3 V,

DD

3685-003

Rev. C | Page 6 of 24

ADF4153

–

–

–

–

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

Loop bandwidth = 20 kHz, reference = 250 MHz, VCO = Sirenza 1750T VCO, evaluation board = EVAL-ADF4153EBZ1, measurements taken
on the Agilent E5500 phase noise system.

30

20kHz LOOP BW, LOWEST NOISE MODE

–40

RF = 1.7202MHz, PFD = 25MHz, N = 68,

–50

FRAC = 101, MO D = 12 5, I
INTEGRATED PHASE ERROR = 0. 23° RM S

–60

SIRENZA 1750T VCO

–70
–80

–90
–100
–110
–120
–130

PHASE NOISE ( dBc/Hz)

–140
–150
–160
–170

1k 10k 1M 10M 100M

= 625µA, DSB

CP

100k

FREQUENCY (Hz)

Figure 5. Single-Sideband Phase Noise Plot (Lowest Noise Mode)

30

20kHz LOOP BW, LOW NOISE AND SPUR MODE

–40

RF = 1.7202MHz, PFD = 25MHz, N = 68,

–50

FRAC = 101, MOD = 125, I
INTEGRATED PHASE ERROR = 0.33° RMS

–60

SIRENZA 1750T V CO

–70

–80

–90
–100
–110
–120
–130

PHASE NOISE ( dBc/Hz)

–140
–150
–160
–170

1k 10k 1M 10M 100M

= 625µA, DSB

CP

100k
FREQUENCY (Hz)

Figure 6. Single-Sideband Phase Noise Plot (Low Noise and Spur Mode)

30

20kHz LOOP BW, LOW SPUR MODE

–40

RF = 1.7202MHz, PFD = 25MHz, N = 68,

–50

FRAC = 101, MO D = 12 5, I
INTEGRATED PHASE ERROR = 0. 36° RM S

–60

SIRENZA 1750T VCO

–70

–80

–90
–100
–110
–120
–130

PHASE NOISE ( dBc/Hz)

–140
–150
–160
–170

1k 10k 1M 10M 100M

= 625µA, DSB

CP

100k

FREQUENCY (Hz)

Figure 7. Single-Sideband Phase Noise Plot (Low Spur Mode)

03685-004

03685-005

03685-006

5

0

–5

–10

–15

–20

AMPLITUDE ( dBm)

–25

–30

–35

0 0.5 1.0 1.5 4.03.53.02.52.0 4.5

FREQUENCY (G Hz)

P = 4/5

P = 8/9

Figure 8. RF Input Sensitivity

6
5
4
3

2
1

(mA)

0

CP

I

–1
–2

–3
–4
–5
–6

01234

VCP(V)

Figure 9. Charge Pump Output Characteristics

90

–92

–94

–96

–98

–100

PHASE NOISE ( dBc/Hz)

–102

–104

–60 100–40

–20 0 20 40 60

TEMPERATURE (°C)

Figure 10. Phase Noise vs. Temperature

80

03685-011

03685-012

5

03685-014

Rev. C | Page 7 of 24

ADF4153

www.BDTIC.com/ADI

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

100kΩ

NC

SW1

SW2

SW3

NO

REF

IN

NC

Figure 11. Reference Input Stage

BUFFER

TO R COUNTER

03685-027

RF INPUT STAGE

The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.

BIAS

GENERATOR

A

RF

IN

1.6V

2kΩ 2kΩ

AV

DD

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.

INT, FRAC, MOD, AND R RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RF

= F

RF

OUT

× (INT + (FRAC/MOD)) (1)

PFD

where:

RF

is the output frequency of the external voltage controlled

OUT

oscillator (VCO).
INT is the preset divide ratio of the binary 9-bit counter (31
to 511).

MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).

The PFD frequency is given by:

F

= REFIN × (1 + D)/R (2)

PFD

where:

REF

is the reference input frequency.

IN

D is the REF

doubler bit.

IN

R is the preset divide ratio of the binary 4-bit programmable
reference counter (1 to 15).

) equation is

OUT

RF R COUNTER

B

RF

IN

AGND

Figure 12. RF Input Stage

03685-015

The 4-bit RF R counter allows the input reference frequency

) to be divided down to produce the reference clock to

(REF

IN

the PFD. Division ratios from 1 to 15 are allowed.

FROM RF

INPUT STAGE

RF N DIVIDER

N-COUNTER

INT

REG

Figure 13. RF N Divider

N = INT + FRAC/MOD

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MOD
REG

FRAC

VALUE

TO PFD

3685-016

Rev. C | Page 8 of 24