Analog Devices ADF4118, ADF4117, ADF4116 Datasheet

a

C

RF PLL Frequency Synthesizers

ADF4116/ADF4117/ADF4118

FEATURES
ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz

2.7 V to 5.5 V Power Supply
Separate V

Allows Extended Tuning Voltage in 3 V

P

Systems
Selected Charge Pump Currents
Dual Modulus Prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Fast Lock Mode

APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DV

DD

DD

GENERAL DESCRIPTION

The ADF4116 family of frequency synthesizers can be used
to implement local oscillators in the up-conversion and down­conversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (5-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP+A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be imple­mented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to

5.5 V and can be powered down when not in use.

V

CPGND

P

ADF4116/ADF4117/ADF4118

REF

CLK

DATA

RF

RFINB

IN

21-BIT

LE

A

IN

INPUT REGISTER

FROM

FUNCTION LATCH

PRESCALER

P/P +1

E

SD

OUT

N = BP + A

19

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

5-BIT

A COUNTER

14

13

5

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

18

AV

DD

SD

OUT

DGNDAGND

CHARGE

PUMP

MUX

M3 M2 M1

FL

SWITCH

CP

HIGH Z

MUXOUT

O

FL

O

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADF4116/ADF4117/ADF4118–SPECIFICATIONS

1

(AV

= DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AV

DD

Parameter B Version B Chips2Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency See Figure 22 for Input Circuit

ADF4116 45/550 45/550 MHz min/max
ADF4117 0.045/1.2 0.045/1.2 GHz min/max
ADF4118 0.1/3.0 0.1/3.0 GHz min/max Input Level = –10 dBm

ADF4118 0.2/3.0 0.2/3.0 GHz min/max
Maximum Allowable
Prescaler Output Frequency

3

RF Input Sensitivity –15/0 –15/0 dBm min/max AV

REFIN CHARACTERISTICS

Reference Input Frequency 0/100 0/100 MHz min/max
Reference Input Sensitivity

4

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max

PHASE DETECTOR FREQUENCY555 55 MHz max

CHARGE PUMP

ICP Sink/Source

High Value 1 1 mA typ

Low Value 250 250 µA typ

Absolute Accuracy 2.5 2.5 % typ

Three-State Leakage Current 1 1 nA max

I

CP

Sink and Source Current Matching 3 3 % typ 0.5 V ≤ V

vs. V

I

CP

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 0.8 × DV

INH

V

, Input Low Voltage 0.2 × DV

INL

I

INH/IINL

C

, Input Current ± 1 ±1 µA max

, Input Capacitance 10 10 pF max

IN

Reference Input Current ± 100 ± 100 µA max

LOGIC OUTPUTS

, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA

V

OH

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV

DD

DV

DD

V

P

6

I

(AIDD + DIDD) See Figure 20

DD

ADF4116 5.5 4.5 mA max 4.5 mA Typical

ADF4117 5.5 4.5 mA max 4.5 mA Typical

ADF4118 7.5 6.5 mA max 6.5 mA Typical
I

P

Low-Power Sleep Mode 1 1 µA typ

≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = T

DD

165 165 MHz max AV
200 200 MHz max AV

MIN

to T

unless otherwise noted)

MAX

DD, DVDD

DD, DVDD

DD

= 3 V
= 5 V

= 3 V

–10/0 –10/0 dBm min/max AVDD = 5 V

–5/0 –5/0 dBm min/max AC-Coupled. When DC-Coupled:

0 to V

Max (CMOS Compatible)

DD

≤ VP – 0.5

CP

2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5

0.8 × DVDDV min

DD

0.2 × DVDDV max

DD

2.7/5.5 2.7/5.5 V min/V max
AV

DD

AV

DD

AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V

0.4 0.4 mA max TA = 25°C

–2–

REV. 0

ADF4116/ADF4117/ADF4118

Parameter B Version B Chips2Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4118 Phase Noise Floor

Phase Noise Performance

ADF4116
ADF4117
ADF4118
ADF4117
ADF4118
ADF4118

9

540 MHz Output –89 –89 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

10

900 MHz Output –87 –87 dBc/Hz typ Note 15

10

900 MHz Output –90 –90 dBc/Hz typ Note 15

11

836 MHz Output –78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency

12

1750 MHz Output –85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

13

1750 MHz Output –65 –65 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

ADF4118141960 MHz Output –84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

Spurious Signals

ADF41169540 MHz Output –88/–99 –88/–99 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4117
ADF4118
ADF4117
ADF4118
ADF4118

10

900 MHz Output –90/–104 –90/–104 dBc typ Note 15

10

900 MHz Output –91/–100 –91/–100 dBc typ Note 15

11

836 MHz Output –80/–84 –80/–84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency

12

1750 MHz Output –88/–90 –88/–90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

13

1750 MHz Output –65/–73 –65/–73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency

ADF4118141960 MHz Output –80/–86 –80/–86 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

1

Operating temperature range is as follows: B Version: –40° C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters.

4

AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels.

5

Guaranteed by design. Sample tested to ensure compliance.

6

AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value).

8

The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

Same conditions as above.

Specifications subject to change without notice.

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.

PFD

= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.

PFD

TIMING CHARACTERISTICS

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTE

1

Guaranteed by design but not production tested.

Specifications subject to change without notice.

7

8

Limit at T

–170 –170 dBc/Hz typ @ 25 kHz PFD Frequency
–162 –162 dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output

(AVDD = DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V;

1

TA = T

MIN

MIN

to T

to T

unless otherwise noted)

MAX

MAX

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

REV. 0

–3–

ADF4116/ADF4117/ADF4118

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1, 2

AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

P

V

to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ
CSP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance

JA

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . . . . . . . 122°C/W

(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . . 216°C/W

CLOCK

DATA

t

1

DB20 (MSB) DB19 DB2

LE

t

2

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

6425 (CMOS) and 303 (Bipolar).

t

3

t

4

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

5

LE

Figure 1. Timing Diagram

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu­late on the human body and test equipment and can discharge without detection. Although the

WARNING!

ADF4116/ADF4117/ADF4118 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4116BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4116BCP –40°C to +85°C Chip Scale Package CP-20
ADF4117BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4117BCP –40°C to +85°C Chip Scale Package CP-20
ADF4118BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4118BCP –40°C to +85°C Chip Scale Package CP-20

*Contact the factory for chip availability.

–4–

REV. 0

ADF4116/ADF4117/ADF4118

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1FL

O

2 CP Charge Pump Output. When enabled, this provides the ±I

3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.

4 AGND Analog Ground. This is the ground return path for the prescaler.

5RF

6RF

7AV

8 REF

B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

IN

A Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.

IN

DD

IN

9 DGND Digital Ground.

10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency

15 DV

16 V

DD

P

Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter band­width. This will speed up locking of the PLL.

to the external loop filter, which in turn drives

CP

the external VCO.

small bypass capacitor, typically 100 pF. See Figure 22.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV

must be the same value as DVDD.

DD

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 kΩ. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal
oscillator or it can be ac-coupled.

state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.

the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

input is a high impedance CMOS input.

of the four latches, the latch being selected using the control bits.

to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.

REV. 0

FL

CPGND

AGND

RFINB

RFINA

AV

REF

O

CP

DD

IN

TSSOP

1

2

ADF4116

3

ADF4117
ADF4118

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT

LE

DATA

CLK

CE

DGND

PIN CONFIGURATIONS

–5–

Chip Scale Package

CP

2019181716

1

CPGND

ADF4116

2

AGND

AGND

RF

IN

RF

IN

B

A

3

4

5

6

AVDDAV

ADF4117
ADF4118

TOP VIEW

(Not to Scale)

FLOVPDVDDDV

7

8

9

10

IN

DD

REF

DGND

DGND

DD

15

14

13

12

11

MUXOUT

LE

DATA

CLK

CE

ADF4116/ADF4117/ADF4118

–Typical Performance Characteristics

Table I. S-Parameter Data for the ADF4118 RF Input

(Up to 1.8 GHz)

FREQ- PARAM- DATA- IMPEDANCE­UNIT TYPE FORMAT OHMS

GHZ S MA R 50

FREQ MagS11 AngS11

0.05 0.89207 –2.0571

0.10 0.8886 –4.4427

0.15 0.89022 –6.3212

0.20 0.96323 –2.1393

0.25 0.90566 –12.13

0.30 0.90307 –13.52

0.35 0.89318 –15.746

0.40 0.89806 –18.056

0.45 0.89565 –19.693

0.50 0.88538 –22.246

0.55 0.89699 –24.336

0.60 0.89927 –25.948

0.65 0.87797 –28.457

0.70 0.90765 –29.735

0.75 0.88526 –31.879

0.80 0.81267 –32.681

0.85 0.90357 –31.522

0.90 0.92954 –34.222

FREQ MagS11 AngS11

0.95 0.92087 –36.961

1.00 0.93788 –39.343

1.05 0.9512 –40.134

1.10 0.93458 –43.747

1.15 0.94782 –44.393

1.20 0.96875 –46.937

1.25 0.92216 –49.6

1.30 0.93755 –51.884

1.35 0.96178 –51.21

1.40 0.94354 –53.55

1.45 0.95189 –56.786

1.50 0.97647 –58.781

1.55 0.98619 –60.545

1.60 0.95459 –61.43

1.65 0.97945 –61.241

1.70 0.98864 –64.051

1.75 0.97399 –66.19

1.80 0.97216 –63.775

KEYWORD

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.64ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900 MHz CARRIER 1MHz

0.64ⴗ rms

Figure 4. ADF4118 Integrated Phase Noise (900 MHz,

µ

200 kHz, 35 kHz, Typical Lock Time: 200

s)

0

–5

–10

–15

–20

–25

–30

RF INPUT POWER – dBm

–35

–40

–45

0 4.00.5 1.5 2.0 2.5 3.0 3.5

TA = –40ⴗC

TA = ⴙ25ⴗC

1.0
RF INPUT FREQUENCY – GHz

VDD = 3V

= 3V

V

P

TA = ⴙ85ⴗC

Figure 2. Input Sensitivity (ADF4118)

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 900MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 1mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

–90.2dBc/Hz

Figure 3. ADF4118 Phase Noise (900 MHz, 200 kHz, 20 kHz)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.575ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900 MHz CARRIER 1MHz

0.575ⴗ rms

Figure 5. ADF4118 Integrated Phase Noise (900 MHz,

µ

200 kHz, 20 kHz, Typical Lock Time: 400

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –3.8dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

VDD = 3V, VP = 5V

ICP = 1mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 4

s)

–91.5dBc

Figure 6. ADF4118 Reference Spurs (900 MHz, 200 kHz,
20 kHz)

–6–

REV. 0