Analog Devices ADF4116 7 8 b Datasheet

RF PLL Frequency Synthesizers

FEATURES

ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz

2.7 V to 5.5 V power supply Separate V Selected charge pump currents Dual modulus prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33 3-wire serial interface Digital lock detect Power-down mode Fast lock mode

APPLICATIONS

Base stations for wireless radio (GSM, PCS, DCS, CDMA, WCDMA)

Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs Communications test equipment CATV equipment

allows extended tuning voltage in 3 V systems

ADF4116/ADF4117/ADF4118

GENERAL DESCRIPTION

The ADF4116 family of frequency synthesizers can be used to implement local oscillators in the up-conversion and downconversion sections of wireless receivers and transmitters. They consist of a low-noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator).

Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

CPGND

ADF4116/ADF4117/ADF4118

REF

CLK

DATA

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

21-BIT

INPUT REGISTER

FROM

FUNCTION LATCH

PRESCALER

P/P +1

OUT

N = BP + A

14-BIT

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER LOAD LOAD

5-BIT

A COUNTER

DGNDAGNDCE

Figure 1.

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

OUT

CHARGE

PUMP

MUX

M3 M2 M1

SWITCH

HIGH Z

MUXOUT

00392-B-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADF4116/ADF4117/ADF4118

TABLE OF CONTENTS

Specifications..................................................................................... 3

Counter Reset ............................................................................. 19

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transis t o r Count ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 12

Reference Input Section............................................................. 12

RF Input Stage............................................................................. 12

Prescaler (P/P + 1)...................................................................... 12

A and B Counters ....................................................................... 12

R Counter ....................................................................................12

Phase Frequency Detector (PFD) and Charge Pump............ 13

MUXOUT and Lock Detect...................................................... 13

Input Shift Register..................................................................... 13

Power-Down ............................................................................... 19

MUXOUT Control..................................................................... 19

Phase Detector Polarity ............................................................. 19

Charge Pump Three-State......................................................... 19

Fastlock Enable Bit ..................................................................... 19

Fastlock Mode Bit....................................................................... 19

Timer Counter Control............................................................. 19

Initialization Latch ..................................................................... 20

Device Programming after Initial Power-Up ......................... 20

Applications..................................................................................... 21

Local Oscillator for the GSM Base Station Transmitter........ 21

Shutdown Circuit ....................................................................... 21

Direct Conversion Modulator .................................................. 21

Interfacing ................................................................................... 24

Outline Dimensions ....................................................................... 25

Function Latch ................................................................................19

REVISION HISTORY

9/04—Changed from Rev. A to Rev. B

Changes to Specifications................................................................ 3

Changes to Ordering Guide.......................................................... 25

3/01—Changed from Rev. 0 to Rev. A

4/00—Rev. 0: Initial Version

Ordering Guide .......................................................................... 25

Rev. B | Page 2 of 28

ADF4116/ADF4117/ADF4118

SPECIFICATIONS

Operating temperature range for the B version is −40°C to +85°C.

= DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = T

MIN

to T

, unless otherwise noted;

MAX

dBm referred to 50 Ω.

Table 1.

Parameter B Version1 B Chips2 Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity −15/0 −15/0 dBm min/max AV

−10/0 10/0 dBm min/max AV RF Input Frequency

= 3 V

= 5 V

See Figure 26 for input circuit. ADF4116 80/550 80/550 MHz min/max ADF4116 45/550 45/550 MHz min/max

Input level = −8 dBm. For lower frequencies,

ensure slew rate (SR) > 36 V/µs ADF4117 0.1/1.2 0.1/1.2 GHz min/max ADF4118 0.1/3.0 0.1/3.0 GHz min/max Input level = −10 dBm ADF4118 0.2/3.0 0.2/3.0 GHz min/max Input level = −15 dBm.

Maximum Allowable Prescaler Output Frequency

165 200

MHz max MHz max

, DV , DV

= 3 V = 5 V

REFIN CHARACTERISTICS

Reference Input Frequency 5/100 5/100 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs Reference Input Sensitivity 0.4/AVDD 0.4/AVDD V p-p min/max AVDD = 3.3 V, biased at AVDD/2 4

3.0/AV

V p-p min/max AVDD = 5 V, biased at AVDD/2

REFIN Input Capacitance 10 10 pF max

REFIN Input Current ±100 ±100 µA max PHASE DETECTOR FREQUENCY5 55 55 MHz max CHARGE PUMP

Sink/Source

High Value 1 1 mA typ Low Value 250 250 µA typ

Absolute Accuracy 2.5 2.5 % typ ICP Three-State Leakage Current 1 1 nA max Sink and Source Current Matching 3 3 % typ 0.5 V ≤ VCP ≤ VP– 0.5

ICP vs. VCP 2 2 % typ 0.5 V ≤ VCP ≤ VP– 0.5

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min

INH

, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max

INL

, Input Current ±1 ± 1 µA max

INH/IINL

CIN, Input Capacitance 10 10 pF max Reference Input Current ±100 ± 100 µA max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

Rev. B | Page 3 of 28

ADF4116/ADF4117/ADF4118

Parameter B Version1 B Chips2 Unit Test Conditions/Comments

POWER SUPPLIES

AVDD 2.7/5.5 2.7/5.5 V min/V max DVDD AVDD AVDD VP AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V IDD (AIDD + DIDD)

ADF4116 5.5 4.5 mA max 4.5 mA typical ADF4117 5.5 4.5 mA max 4.5 mA typical

ADF4118 7.5 6.5 mA max 6.5 mA typical IP 0.4 0.4 mA max TA = 25°C Low-Power Sleep Mode 1 1 µA typ

NOISE CHARACTERISTICS

ADF4118 Normalized Phase Noise

Floor Phase Noise Performance8 @ VCO output

ADF4116 540 MHz Output

ADF4117 900 MHz Output

ADF4118 900 MHz Output10 −90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

ADF4117 836 MHz Output11 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency

ADF4118 1750 MHz Output12 −85 −85 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

ADF4118 1750 MHz Output13 −65 −65 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency

ADF4118 1960 MHz Output14 −84 −84 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

Spurious Signals

ADF4116 540 MHz Output10 −88/−99 −88/−99 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency ADF4117 900 MHz Output10 −90/−104 −90/−104 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency ADF4118 900 MHz Output ADF4117 836 MHz Output11 −80/−84 −80/−84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD frequency ADF4118 1750 MHz Output12 −88/−90 −88/−90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency ADF4118 1750 MHz Output13 −65/−73 −65/−73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD frequency ADF4118 1960 MHz Output14 −80/−86 −80/−86 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

Operating temperature range for the B version is −40°C to +85°C.

The B Chip specifications are given as typical values.

This is the maximum operating frequency of the CMOS counters.

AC coupling ensures that AVDD/2 bias. See Figure 35 for typical circuit.

Guaranteed by design. Sample tested to ensure compliance.

AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN

value) and 10logF

The phase noise is measured with the EVAL-ADF411xEB Evaluation Board and the HP8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the

synthesizer (f

= 10 MHz; f

REFIN

= 10 MHz; f

REFIN

= 10 MHz; f

REFIN

= 10 MHz; f

REFIN

= 10 MHz; f

REFIN

= 10 MHz; f

REFIN

−213 −213 dBc/Hz typ

: PN

= PN

PFD

SYNTH

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop Bandwidth = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop Bandwidth = 20 kHz.

PFD

= 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop Bandwidth = 3 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop Bandwidth = 20 kHz.

PFD

= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop Bandwidth = 1 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop Bandwidth = 20 kHz.

PFD

– 10logF

TOT

−89 −89 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−87 −87 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−91/−100 −91/−100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

– 20logN.

PFD

, and subtracting 20 logN (where N is the N divider

TOT

Rev. B | Page 4 of 28

ADF4116/ADF4117/ADF4118

TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = T

Guaranteed by design, but not production tested.

Table 2.

Parameter Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 10 ns min DATA to CLOCK set-up time

t2 10 ns min DATA to CLOCK hold time

t3 25 ns min CLOCK high duration

t4 25 ns min CLOCK low duration

t5 10 ns min CLOCK to LE set-up time

t6 20 ns min LE pulse width

MIN

to T

, unless otherwise noted.

MAX

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

00392-B-002

CLOCK

DATA

DB20 (MSB) DB19 DB2

Figure 2. Timing Diagram

Rev. B | Page 5 of 28

ADF4116/ADF4117/ADF4118

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND AVDD to DVDD −0.3 V to +0.3 V VP to GND −0.3 V to +7 V VP to AVDD −0.3 V to +5.5 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V RFINA to RFINB ±320 mV Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOP θJA Thermal Impedance 150.4°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

______________

GND = AGND = DGND = 0 V.

−0.3 V to +7 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT

6425 (CMOS) and 303 (bipolar).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. B | Page 6 of 28

ADF4116/ADF4117/ADF4118

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CPGND

AGND

RFINA

REF

ADF4116/

ADF4117/

ADF4118

TOP VIEW

(Not to Scale)

MUXOUT LE DATA CLK CE DGND

00392-B-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 FLO

Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth. This speeds up locking the PLL.

2 CP

Charge Pump Output. When enabled, this provides the ± I

to the external loop filter, which in turn drives the

external VCO. 3 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 AGND Analog Ground. This is the ground return path for the prescaler. 5 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 26. 6 RFINA Input to the RF Prescaler. This small signal input is ac-coupled from the VCO. 7 AVDD

8 REFIN

Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV

Reference Input. This is a CMOS input with a nominal threshold of V

must be the same value as DVDD.

/2 and an equivalent input resistance

of 100 kΩ. See Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be

ac-coupled. 9 DGND Digital Ground. 10 CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bit F2. 11 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high

impedance CMOS input. 13 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits. 14 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally. 15 DVDD

16 VP

Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

Charge Pump Power Supply. This should be greater than or equal to V

must have the same value as AVDD.

. In systems where VDD is 3 V, this supply

can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V.

Rev. B | Page 7 of 28

ADF4116/ADF4117/ADF4118

TYPICAL PERFORMANCE CHARACTERISTICS

PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE-

FREQUNIT

GHz S MA R 50

FREQ MagS11 AngS11

0.05 0.89207 –2.0571

0.10 0.8886 –4.4427

0.15 0.89022 –6.3212

0.20 0.96323 –2.1393

0.25 0.90566 –12.13

0.30 0.90307 –13.52

0.35 0.89318 –15.746

0.40 0.89806 –18.056

0.45 0.89565 –19.693

0.50 0.88538 –22.246

0.55 0.89699 –24.336

0.60 0.89927 –25.948

0.65 0.87797 –28.457

0.70 0.90765 –29.735

0.75 0.88526 –31.879

0.80 0.81267 –32.681

0.85 0.90357 –31.522

0.90 0.92954 –34.222

FREQ MagS11 AngS11

0.95 0.92087 –36.961

1.00 0.93788 –39.343

1.05 0.9512 –40.134

1.10 0.93458 –43.747

1.15 0.94782 –44.393

1.20 0.96875 –46.937

1.25 0.92216 –49.6

1.30 0.93755 –51.884

1.35 0.96178 –51.21

1.40 0.94354 –53.55

1.45 0.95189 –56.786

1.50 0.97647 –58.781

1.55 0.98619 –60.545

1.60 0.95459 –61.43

1.65 0.97945 –61.241

1.70 0.98864 –64.051

1.75 0.97399 –66.19

1.80 0.97216 –63.775

Figure 4. S-Parameter Data for the ADF4118 RF Input (Up to 1.8 GHz)

–5

–10

–15

–20

–25

–30

RF INPUT POWER (dBm)

–35

–40

–45

0 4.00.5 1.5 2.0 2.5 3.0 3.5

TA = –40°C

= +25°C

1.0 RF INPUT FREQUENCY (GHz)

Figure 5. Input Sensitivity (ADF4118)

–10 –20

–30

–40

–50

–60 –70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE LEVEL = –4.2dBm

–2kHz –1kHz 900MHz +1kHz +2kHz

= 3V, VP = 5V

= 1mA

PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 22

–90.2dBc/Hz

Figure 6. ADF4118 Phase Noise

900 MHz, 200 kHz, 20 kHz

VDD = 3V

= 3V

= +85°C

OHMS

00392-B-004

00392-B-005

00392-B-006

–40

–50

–60 –70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz

RL = –40dBc/Hz10dB/DIVISION RMS NOISE = 0.64°

0.64° rms

Figure 7. ADF4118 Integrated Phase Noise

900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs

–40 –50

–60

–70 –80 –90

–100

–110

PHASE NOISE (dBc/Hz)

–120 –130

–140

100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz

RL = –40dBc/Hz10dB/DIVISION RMS NOISE = 0.575°

0.575° rms

Figure 8. ADF4118 Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz,

Typical Lock Time: 400 µs)

–10 –20

–30

–40

–50

–60 –70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE LEVEL = –3.8dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

= 3V, VP = 5V

= 1mA

PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 4

–91.5dBc

Figure 9. ADF4118 Reference Spurs

900 MHz, 200 kHz, 20 kHz

00392-B-007

00392-B-008

00392-B-009

Rev. B | Page 8 of 28

ADF4116/ADF4117/ADF4118

–10 –20

–30

–40

–50

–60 –70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE LEVEL = –4.2dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

= 3V, VP = 5V

= 1mA

PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 35kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 10

–90.67dBc

Figure 10. ADF4118 Reference Spurs

900 MHz, 200 kHz, 35 kHz

–10 –20

–30

–40

–50

–60

OUTPUT POWER (dB)

–70

–80

–90

–100

REFERENCE LEVEL = –7.0dBm

–400kHz –200kHz 1750MHz +200kHz +400kHz

= 3V, VP = 5V

= 1mA

PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 25

–71.5dBc/Hz

Figure 11. ADF4118 Phase Noise

1750 MHz, 30 kHz, 3 kHz

–40 –50

–60

–70 –80 –90

–100

–110

PHASE NOISE (dBc/Hz)

–120 –130

–140

100Hz FREQUENCY OFFSET FROM 1.75GHz CARRIER 1MHz

RL = –40dBc/Hz10dB/DIVISION RMS NOISE = 2.0°

2.0° rms

Figure 12. ADF4118 Integrated Phase Noise

1750 MHz, 30 kHz, 3 kHz

00392-B-010

00392-B-011

00392-B-012

–10 –20

–30

–40

–50

–60 –70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE LEVEL = –7.0dBm

–60kHz –30kHz 1750MHz +30kHz +60kHz

= 3V, VP = 5V

= 5mA

PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 5kHz RES. BANDWIDTH = 300Hz VIDEO BANDWIDTH = 300Hz SWEEP = 4.2ms AVERAGES = 20

–72.3dBc

Figure 13. ADF4118 Reference Spurs

1750 MHz, 30 kHz, 3 kHz

–10 –20 –30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

REFERENCE LEVEL = –10.3dBm

–2kHz –1kHz

VVDD = 3V, VP = 5V

= 1mA

PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 26

–85.2dBc/Hz

2800MHz

+1kHz +2kHz

Figure 14. ADF4118 Phase Noise

2800 MHz, 1 MHz, 100 kHz

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.552°

–40 –50

–60

–70 –80 –90

–100

–110

PHASE NOISE (dBc/Hz)

–120 –130

–140

100Hz FREQUENCY OFFSET FROM 2.8GHz CARRIER 1MHz

1.55° rms

Figure 15. ADF4118 Integrated Phase Noise

2800 MHz, 1 MHz, 100 kHz

00392-B-013

00392-B-014

00392-B-015

Rev. B | Page 9 of 28

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