ANALOG DEVICES ADF4108 Service Manual

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PLL Frequency Synthesizer

FEATURES

8.0 GHz bandwidth

3.2 V to 3.6 V power supply
Separate charge pump supply (V

voltage in 3.3 V systems

Programmable, dual-modulus prescaler

8/9, 16/17,

32/33, or 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
Loop filter design possible with ADIsimPLL
4 mm × 4 mm, 20-lead chip scale package

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio

) allows extended tuning

P

DV

AV

DD

DD

GENERAL DESCRIPTION

The ADF4108 frequency synthesizer can be used to implement
local oscillators in the upconversion and downconversion
sections of wireless receivers and transmitters. It consists of a
low noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1).
The A (6-bit) and B (13-bit) counters, in conjunction with the
dual-modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter (R counter),
allows selectable REF
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled oscillator
(VCO). Its very high bandwidth means that frequency doublers
can be eliminated in many high frequency systems, simplifying
system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

V

CPGND

P

ADF4108

frequencies at the PFD input. A complete

IN

R

SET

REFERENCE

REF

IN

CLK

DATA

LE

RFINA

B

RF

IN

Rev. A

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responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

B COUNTER

LOAD

LOAD

A COUNTER

DGND

14

13

13-BIT

6-BIT

6

19

Figure 1.

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

SD

CURRENT

SETTING 1

CPI3 CPI2 CPI1

AV

DD

OUT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH-Z

CP

MUXOUT

ADF4108

06015-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADF4108

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Reference Input Stage................................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

Phase Frequency Detector and Charge Pump....................... 10

MUXOUT and Lock Detect...................................................... 10

Input Shift Register .................................................................... 10

Latch Summary........................................................................... 11

Reference Counter Latch Map.................................................. 12

AB Counter Latch Map ............................................................. 13

Function Latch Map................................................................... 14

Initialization Latch Map ............................................................ 15

Function Latch............................................................................ 16

Initialization Latch..................................................................... 17

Power Supply Considerations................................................... 17

Interfacing ....................................................................................... 18

ADuC812 Interface.................................................................... 18

ADSP-21xx Interface ................................................................. 18

PCB Design Guidelines for Chip Scale Package......................... 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

12/07—Rev. 0 to Rev. A

Removed TSSOP Package..................................................Universal

Changes to Features.......................................................................... 1

Changes to Table 1 Endnote 10 and Endnote 11.......................... 4

Changes to Table 3............................................................................ 6

Deleted Figure 3................................................................................ 7

Changes to Table 4............................................................................ 7

Changes to Figure 10 and Figure 11............................................... 8

Updated Outline Dimensions....................................................... 20

Deleted Figure 24............................................................................ 20

Changes to Ordering Guide.......................................................... 20

4/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADF4108

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SPECIFICATIONS

AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

, unless otherwise noted.

MAX

Table 1.

B Chips2

Parameter B Version

1

(Typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 11 for input circuit

RF Input Frequency (RFIN) 1.0/8.0 1.0/8.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/μs
RF Input Sensitivity −5/+5 −5/+5 dBm min/max
Maximum Allowable Prescaler

Output Frequency

3

300 300 MHz max P = 8

325 325 MHz max P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

4

0.8/VDD 0.8/VDD V p-p min/max Biased at AVDD/2
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 μA max

PHASE DETECTOR

Phase Detector Frequency

6

104 104 MHz max

CHARGE PUMP Programmable; see Figure 18

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 μA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Figure 18

SET

ICP Three-State Leakage 1 1 nA typ 1 nA typical; TA = 25°C
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 μA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 VDD − 0.4 V min CMOS output chosen
IOH, Output High Current 100 100 μA max
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 3.2/3.6 3.2/3.6 V min/max
DVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/max AVDD ≤ VP ≤ 5.5 V
IDD (AIDD + DIDD)

7

17 17 mA max 15 mA typ
IP 0.4 0.4 mA max TA = 25°C
Power-Down Mode (AIDD + DIDD)810 10 μA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

5

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MIN

to

Rev. A | Page 3 of 20

ADF4108

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B Chips2

Parameter B Version

NOISE CHARACTERISTICS

Normalized Phase Noise Floor
Phase Noise Performance

7900 MHz Output

11

9

10

−219 −219 dBc/Hz typ
@ VCO output

−81 −81 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency

Spurious Signals

7900 MHz Output

1

Operating temperature range (B version) is −40°C to +85°C.

2

The B chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

4

AVDD = DVDD = 3.3 V.

5

AC coupling ensures AVDD/2 bias.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, f

8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.

9

This value can be used to calculate phase noise for any application. Use the formula −219 + 10 log(f

seen at the VCO output. The value given is the lowest noise mode.

10

The phase noise is measured with the EVAL-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REFIN for the
synthesizer (f

11

f

REFIN

REFOUT

= 10 MHz; f

PFD

11

= 10 MHz @ 0 dBm).

= 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z.

−82 −82 dBc typ @ 1 MHz offset and 1 MHz PFD frequency

1

(Typ) Unit Test Conditions/Comments

= 200 kHz, REFIN = 10 MHz.

PFD

) + 20 logN to calculate in-band phase noise performance as

PFD

Rev. A | Page 4 of 20

ADF4108

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TIMING CHARACTERISTICS

AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

, unless otherwise noted.

MAX

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MIN

to

Table 2.

Parameter

1

Limit2 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK setup time
t2 10 ns min DATA to CLOCK hold time
t3 25 ns min CLOCK high duration
t4 25 ns min CLOCK low duration
t5 10 ns min CLOCK to LE setup time
t6 20 ns min LE pulse width

1

Guaranteed by design but not production tested.

2

Operating temperature range (B Version) is −40°C to +85°C.

t

t

3

4

CLOCK

DATA

DB23 (MSB)

LE

LE

t

t

1

2

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

06015-002

Rev. A | Page 5 of 20

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance

(Paddle Soldered)
Reflow Soldering

Peak Temperature (60 sec) 260°C

Time at Peak Temperature 40 sec
Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

30.4°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an

D rating of <2 kV, and it is ESD sensitive. Proper precautions

ES
should be taken for handling and assembly.

ESD CAUTION

Rev. A | Page 6 of 20