Analog Devices ADF4107 Datasheet

PLL Frequency Synthesizer

FEATURES

7.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulsewidth
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANs
Base stations for wireless radio

AV

) allows extended tuning

P

DV

DD

DD

GENERAL DESCRIPTION

The ADF4107 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (phase frequency detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual­modulus prescaler (P/P + 1), implement an N divider
(N = BP + A). In addition, the 14-bit reference counter
(R counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (phase-locked loop) can be implemented
if the synthesizer is used with an external loop filter and VCO
(voltage controlled oscillator). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.

FUNCTIONAL BLOCK DIAGRAM

V

P

CPGND

REFERENCE

ADF4107

R

SET

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

24-BIT INPUT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

A COUNTER

DGND

13

6-BIT

6

19

Figure 1.

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

SETTING 1

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4107

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADF4107

TABLE OF CONTENTS

ADF4107—Specifications................................................................ 3

Latch Summary........................................................................... 11

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 5

Pin Configurations and Functional Descriptions........................ 6

Typical Performance Characteristics ............................................. 7

Functional Description.................................................................... 9

Reference Input Stage................................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

Phase Frequency Detector and Charge Pump........................ 10

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

Reference Counter Latch Map.................................................. 12

AB Counter Latch Map ............................................................. 13

Function Latch Map................................................................... 14

Initialization Latch Map ............................................................ 15

Function Latch............................................................................ 16

Initialization Latch..................................................................... 17

Applications..................................................................................... 18

Local Oscillator for LMDS Base Station Transmitter............ 18

Interfacing ................................................................................... 19

PCB Design Guidelines for Chip Scale Package .................... 19

Outline Dimensions....................................................................... 20

ESD Caution.................................................................................... 20

Ordering Guide............................................................................... 20

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADF4107

ADF4107—SPECIFICATIONS

Table 1. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R

to T

T

MAX

Parameter B

, unless otherwise noted.)

MIN

Version

1

B Chips
(Typ)

2

Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN)3 1.0/7.0 1.0/7.0 GHz min/max See Figure 18 for input circuit.

RF Input Sensitivity –5/+5 –5/+5 dBm min/max

Maximum Allowable Prescaler

Output Frequency

4

300 300 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, use dc-coupled square wave (0 to VDD).

REFIN Input Sensitivity5 0.8/VDD 0.8/VDD V p-p min/max

AC-coupled; when dc-coupled, 0 to V

compatible).
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency6 104 104 MHz max

CHARGE PUMP Programmable; see Figure 25.

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Figure 25.

SET

ICP Three-State Leakage 1 1 nA typ
Sink and Source Current

2 2 % typ 0.5 V ≤ V

Matching

ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 µA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V.
VOH, Output High Voltage VDD – 0.4 VDD – 0.4 V min CMOS output chosen.
IOH 100 100 µA max
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AVDD 2.7/3.3 2.7/3.3 V min/V max
DVDD AVDD AVDD
VP AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤5.5V

7

I

(AIDD + DIDD) 17 15 mA max 15 mA typ

DD

IP 0.4 0.4 mA max TA = 25°C
Power-Down Mode8 (AIDD + DIDD) 10 10 µA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA =

SET

DD

= 5.1 kΩ

SET

= 5.1 kΩ

SET

≤ VP – 0.5 V

CP

, max (CMOS

Rev. 0 | Page 3 of 20

ADF4107

2

Parameter B

Version

1

B Chips
(Typ)

Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4107 Phase Noise Floor9 –174 –174 dBc/Hz typ @ 25 kHz PFD Frequency
–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency
–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency
Phase Noise Performance10 @ VCO Output

900 MHz Output11 –93 –93 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency
6400 MHz Output12 –76 –76 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD Frequency
6400 MHz Output13 –83 –83 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD Frequency

Spurious Signals

900 MHz Output11 –90/–92 –90/–92 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency
6400 MHz Output12 –65/–70 –65/–70 dBc typ @ 200 kHz/400kHz and 200 kHz PFD Frequency
6400 MHz Output13 –70/–75 –70/–75 dBc typ @ 1 MHz/2MHz and 1 MHz PFD Frequency

1

Operating temperature range (B Version) is –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

Use a square wave for lower frequencies, below the minimum stated.

4

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

5

AVDD = DVDD = 3 V.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 7.0 GHz.

8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.

9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4107EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer (f

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 32000; Loop B/W = 20 kHz.

PFD

= 1 MHz; Offset Frequency = 1 kHz; fRF = 6400 MHz; N = 6400; Loop B/W = 100 kHz.

PFD

Rev. 0 | Page 4 of 20

ADF4107

TIMING CHARACTERISTICS

Table 2. (AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R

= T

to T

T

A

MAX

, unless otherwise noted.) 1

MIN

Parameter Limit2 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK Setup Time
t2 10 ns min DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulsewidth

1

Guaranteed by design but not production tested.

2

Operating temperature range (B Version) is –40°C to +85°C.

CLOCK

DATA

LE

DB23 (MSB)

LE

t

t

1

2

DB22

Figure 2. Timing Diagram

DB2

t

3

t

4

DB1 (CONTRO L

BIT C2)

= 5.1 kΩ, dBm referred to 50 Ω,

SET

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

ABSOLUTE MAXIMUM RATINGS

Table 3. (TA = 25°C, unless otherwise noted.)

Parameter Rating

AVDD to GND1 –0.3 V to +3.6 V
AVDD to DVDD –0.3 V to +0.3 V
VP to GND –0.3 V to +5.8 V
VP to AVDD –0.3 V to +5.8 V
Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) –40°C to +85°C

Storage Temperature Range –65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
CSP θJA Thermal Impedance 122°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

Transistor Count

CMOS 6425
Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. 0 | Page 5 of 20

ADF4107

T

T

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

TSSOP

R

SET

CP

CPGND

AGND

RFINB

RF

IN

AV

REF

A

DD

IN

1

2

3

4

ADF4107

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOU

LE

DATA

CLK

CE

DGND

CPGND 1

AGND 2
AGND 3
RFINB

A

RF

IN

4
5

Figure 3. ADF4107 TSSOP (Top View)

Figure 4. ADF4107 Chip Scale Package

Table 4. Pin Functional Descriptions

Mnemonic Function

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage
potential at the R

R

SET

I

MAXCP

so, with R

SET

pin is 0.66 V. The relationship between ICP and R

SET

5.25

=

= 5.1 kΩ, I

R

SE

= 5 mA.

CP MAX

is

SET

CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO.
CPGND Charge Pump Ground. This is the ground return path for the charge pump.
AGND Analog Ground. This is the ground return path of the prescaler.

RFINB

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor,
typically 100 pF. See Figure 18.

RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

AVDD

REFIN

Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. AV

Reference Input. This is a CMOS input with a nominal threshold of V

must be the same value as DVDD.

DD

/2 and a dc equivalent input resistance of 100 kΩ. See

DD

Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

DGND Digital Ground.

CE

CLK

DATA

LE

MUXOUT

DVDD

VP

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking
the pin high will power up the device, depending on the status of the power-down bit, F2.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift
register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance
CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the
latch being selected using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed
externally.

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed
as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5
V and used to drive a VCO with a tuning range of up to 5 V.

CSP

(Chip Scale Package)

DD

DD

SETVP

DV

R
191817

PIN 1
INDICATOR

DV
16

20 CP

ADF4107

TOP VIEW

6

7

8

IN

DD

DD

AV

AV

REF

DGND 9

DGND 10

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

Rev. 0 | Page 6 of 20