Analog Devices ADF4007 Datasheet

High Frequency Divider/PLL Synthesizer

FEATURES

7.5 GHz bandwidth Maximum PFD frequency of 120 MHz Divide ratios of 8, 16, 32, or 64

2.7 V to 3.3 V power supply

) allows

Separate charge pump supply (V

extended tuning voltage in 3 V systems

contol of charge pump current

SET

Hardware power-down mode

APPLICATIONS

Satellite communications Broadband wireless access CATV Instrumentation Wireless LANs

GENERAL DESCRIPTION

The ADF4007 is a high frequency divider/PLL synthesizer that can be used in a variety of communications applications. It can operate to 7.5 GHz on the RF side and to 120 MHz at the PFD. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, and a divider/prescaler. The divider/ prescaler value can be set by two external control pins to one of four values (8, 16, 32, or 64). The reference divider is permanently set to 2, allowing an external REF up to 240 MHz.

A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and a VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost.

FUNCTIONAL BLOCK DIAGRAM

CPGND R

SET

ADF4007

frequency of

ADF4007

REF

RFINA

Rev. 0

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R COUNTER

÷ 2

N COUNTER

÷ 8, ÷ 16, ÷ 32, ÷ 64

N2 N1 GND

Figure 1.

REFERENCE

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

MUX

M2 M1

www.analog.com

MUXOUT

04537-0-001

ADF4007

TABLE OF CONTENTS

Specifications..................................................................................... 3

R Counter .......................................................................................9

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Reference Input Section............................................................... 9

RF Input Stage............................................................................... 9

Prescaler P ..................................................................................... 9

REVISION HISTORY

Revision 0: Initial Version

Phase Frequency Detector (PFD) and Charge Pump...............9

MUXOUT ................................................................................... 10

Applications..................................................................................... 11

Fixed High Frequency Local Oscillator................................... 11

Using the ADF4007 as a Divider .............................................. 12

PCB Design Guidelines for Chip Scale Package......................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

ADF4007

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R T

= T

to T

MAX

, unless otherwise noted.

MIN

Table 1.

Parameter B Version

Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN) 1.0/7.0 GHz min/max RF input level: +5 dBm to −10 dBm RF Input Frequency 0.5/7.5 GHz min/max RF input level: +5 dBm to −5 dBm

REFIN CHARACTERISTICS

REFIN Input Sensitivity 0.8/V

V p-p min/max Biased at AVDD/2 REFIN Input Frequency 20/240 MHz min/max For f < 20 MHz, use square wave (slew rate > 50 V/µs) REFIN Input Capacitance 10 pF max REFIN Input Current ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

120 MHz max

MUXOUT

MUXOUT Frequency

200 MHz max CL = 15 pF

CHARGE PUMP

ICP Sink/Source 5.0 mA typ With R Absolute Accuracy 2.5 % typ With R R

Range 3.0/11 kΩ typ

SET

ICP Three-State Leakage 10 nA max TA = 85°C Sink and Source Current Matching 2 % typ ICP vs. V

1.5 % typ

ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 V min VIL, Input Low Voltage 0.6 V max I

, I

, Input Current ±1 µA max TA = 25°C

INH

INL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage VDD − 0.4 V min IOH = 100 µA VOL, Output Low Voltage 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV DV V I

(AI

+ DI ) 17 mA max 15 mA typ

DD DD

2.7/3.3 V min/max AV

AVDD/5.5 V min/max

2.0 mA max TA = 25°C

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

−219 dBc/Hz typ

Operating temperature range (B version) is −40°C to +85°C.

AC coupling ensures AVDD/2 bias. See for typical circuit. Figure 13

Guaranteed by design. Characterized to ensure compliance.

TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN

value) and 10logFPFD. PN

SYNTH

= PN

− 10logF

TOT

− 20logN. The in-band phase noise (PN

PFD

) is measured using the HP8562E Spectrum Analyzer from Agilent.

TOT

= 5.1 kΩ, dBm referred to 50 Ω,

SET

For lower frequencies, ensure that slew rate (SR) > 560 V/µs

= 5.1 kΩ

SET

= 5.1 kΩ

SET

0.5 V ≤ VCP ≤ VP − 0.5 V

≤ V

≤ 5.5 V

, and subtracting 20logN (where N is the N divider

TOT

Rev. 0 | Page 3 of 16

ADF4007

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

AVDD to GND AVDD to DV VP to GND −0.3 V to +5.8 V VP to AV Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V Operating Temperature Range

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C CSP θJA Thermal Impedance 122°C/W Lead Temperature, Soldering

Vapor Phase (60 s) 215°C

Infrared (15 s) 220°C Transistor Count

CMOS 6425

Bipolar 303

GND = AGND = DGND = 0 V.

−0.3 V to +3.6 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 4 of 16

ADF4007

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SET

20 CP

19 R

18 VP17 DVDD16 DV

CPGND 1

AGND 2 AGND 3 RFINB4

PIN1 INDICATOR

ADF4007

TOPVIEW

15 MUXOUT 14 M1 13 M2 12 N1 11 N2

REF

DGND 9

DGND 10

04537-0-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Function

1 CPGND Charge Pump Ground. The ground return path of the charge pump.

2, 3 AGND Analog Ground. The ground return path of the prescaler.

4 RFINB

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF.

5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

6, 7 AV

8 REF

Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AV

must be the same value as DVDD.

Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ.

This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 9, 10 DGND Digital Ground. 11, 12 N2, N1 These two bits set the N value. See Table 4. 13, 14 M2, M1 These two bits set the status of MUXOUT and PFD polarity. See Table 5. 15 MUXOUT This multiplexer output allows either the N divider output or the R divider output to be accessed externally. 16, 17 DV

18 V

Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

must be the same value as AVDD.

Charge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be

set to 5 V and used to drive a VCO with a tuning range of up to 5 V. 19 R

SET

20 CP

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal

voltage potential at the R

5.25

MAXCP

SET

Therefore, if R

= 5.1 kΩ, then ICP = 5 mA.

SET

pin is 0.66 V. The relationship between ICP and R

SET

Charge Pump Output. When enabled, this pin provides ±I

to the external loop filter, which in turn drives the

SET

external VCO.

Rev. 0 | Page 5 of 16

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