ANALOG DEVICES ADF4002-EP Service Manual

A

V

V

Phase Detector/Frequency Synthesizer

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase frequency detector
Supports defense and aerospace applications

(AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request

APPLICATIONS

Clock conditioning
Clock generation
IF LO generation

) allows extended

P

DV

DD

DD

GENERAL DESCRIPTION

The ADF4002-EP frequency synthesizer is used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge pump,
a programmable reference divider, and a programmable N divider.
The 14-bit reference counter (R counter) allows selectable REF
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). In addition,
by programming R and N to 1, the part can be used as a stand­alone PFD and charge pump.

Additional application and technical information can be found
in the ADF4002 data sheet.

FUNCTIONAL BLOCK DIAGRAM

CPGND

P

REFERENCE

ADF4002-EP

R

SET

IN

REF

IN

CLK

DATA

LE

RFINA

B

RF

IN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

CE

22

AGND

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

13-BIT

N COUNTER

DGND

14

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH-Z

ADF4002-EP

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

CP

MUXOUT

09187-001

ADF4002-EP

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

REVISION HISTORY

11/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................5

Thermal Characteristics ...............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Outline Dimensions ..........................................................................8

Ordering Guide .............................................................................8



Rev. 0 | Page 2 of 8

ADF4002-EP

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted. Operating temperature range is −55°C to +125°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity −10 0 dBm

RF Input Frequency (RFIN) 5 400 MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs

REFIN CHARACTERISTICS

REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/μs

REFIN Input Sensitivity

REFIN Input Capacitance 10 pF

REFIN Input Current ±100 μA

PHASE FREQUENCY DETECTOR (PFD)

Phase Detector Frequency

CHARGE PUMP Programmable

ICP Sink/Source

High Value 5 mA R
Low Value 625 μA
Absolute Accuracy 2.5 % R
R

Range 3.0 11 kΩ

SET

ICP Three-State Leakage 1 nA TA = 25°C

ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ (VP − 0.5 V)

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ (VP − 0.5 V)

ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

Input High Voltage, VIH 1.4 V

Input Low Voltage, VIL 0.6 V

Input Current, I

Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH 1.4 V Open-drain output, 1 kΩ pull-up resistor to 1.8 V

DVDD − 0.4 V CMOS output

Output High Current, IOH 100 μA

Output Low Voltage, VOL 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 2.7 3.3 V

DVDD AVDD V

VP AVDD 5.5 V AVDD ≤ VP ≤ 5.5 V

3

I

(AIDD + DIDD) 5.0 6.0 mA

DD

IP 0.4 mA TA = 25°C

Power-Down Mode 1 μA AIDD + DIDD

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PN

Normalized 1/f Noise (PN

1

AVDD = DVDD = 3 V.

2

Guaranteed by design. Sample tested to ensure compliance.

3

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF); RF frequency and REFIN

frequency in MHz.

4

All phase noise measurements were performed with a Rohde & Schwarz FSUP26 phase noise test system using the EVAL-ADF4002EBZ1 evaluation board and the

ultralow noise, 100 MHz OCXO from Wenzel (Part No. 501-16843) as the PLL reference.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)

and 10logf

6

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a

frequency offset (f) is given by PN = P

. PN

PFD

1

0.8 AV

2

, I

±1 μA

INH

INL

SYNTH

4, 6

)

−119 dBc/Hz Measured at 10 kHz offset; normalized to 1 GHz

1_f

= PN

SYNTH

− 10logf

TOT

− 20logN.

PFD

+ 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and the flicker noise are modeled in ADIsimPLL.

1_f

104 MHz ABP[2:1] = 00 (2.9 ns antibacklash pulse width)

4, 5

)

−222 dBc/Hz PLL loop bandwidth = 500 kHz

V p-p Biased at AVDD/2 (ac coupling ensures AVDD/2 bias)

DD

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

Rev. 0 | Page 3 of 8