ANALOG DEVICES ADF4002-EP Service Manual

A

V

V

Phase Detector/Frequency Synthesizer

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase frequency detector
Supports defense and aerospace applications

(AQEC standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request

APPLICATIONS

Clock conditioning
Clock generation
IF LO generation

) allows extended

P

DV

DD

DD

GENERAL DESCRIPTION

The ADF4002-EP frequency synthesizer is used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge pump,
a programmable reference divider, and a programmable N divider.
The 14-bit reference counter (R counter) allows selectable REF
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). In addition,
by programming R and N to 1, the part can be used as a stand­alone PFD and charge pump.

Additional application and technical information can be found
in the ADF4002 data sheet.

FUNCTIONAL BLOCK DIAGRAM

CPGND

P

REFERENCE

ADF4002-EP

R

SET

IN

REF

IN

CLK

DATA

LE

RFINA

B

RF

IN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

CE

22

AGND

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

13-BIT

N COUNTER

DGND

14

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH-Z

ADF4002-EP

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

CP

MUXOUT

09187-001

ADF4002-EP

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

REVISION HISTORY

11/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................5

Thermal Characteristics ...............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................7

Outline Dimensions ..........................................................................8

Ordering Guide .............................................................................8



Rev. 0 | Page 2 of 8

ADF4002-EP

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted. Operating temperature range is −55°C to +125°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity −10 0 dBm

RF Input Frequency (RFIN) 5 400 MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs

REFIN CHARACTERISTICS

REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/μs

REFIN Input Sensitivity

REFIN Input Capacitance 10 pF

REFIN Input Current ±100 μA

PHASE FREQUENCY DETECTOR (PFD)

Phase Detector Frequency

CHARGE PUMP Programmable

ICP Sink/Source

High Value 5 mA R
Low Value 625 μA
Absolute Accuracy 2.5 % R
R

Range 3.0 11 kΩ

SET

ICP Three-State Leakage 1 nA TA = 25°C

ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ (VP − 0.5 V)

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ (VP − 0.5 V)

ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

Input High Voltage, VIH 1.4 V

Input Low Voltage, VIL 0.6 V

Input Current, I

Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH 1.4 V Open-drain output, 1 kΩ pull-up resistor to 1.8 V

DVDD − 0.4 V CMOS output

Output High Current, IOH 100 μA

Output Low Voltage, VOL 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 2.7 3.3 V

DVDD AVDD V

VP AVDD 5.5 V AVDD ≤ VP ≤ 5.5 V

3

I

(AIDD + DIDD) 5.0 6.0 mA

DD

IP 0.4 mA TA = 25°C

Power-Down Mode 1 μA AIDD + DIDD

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PN

Normalized 1/f Noise (PN

1

AVDD = DVDD = 3 V.

2

Guaranteed by design. Sample tested to ensure compliance.

3

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF); RF frequency and REFIN

frequency in MHz.

4

All phase noise measurements were performed with a Rohde & Schwarz FSUP26 phase noise test system using the EVAL-ADF4002EBZ1 evaluation board and the

ultralow noise, 100 MHz OCXO from Wenzel (Part No. 501-16843) as the PLL reference.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)

and 10logf

6

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a

frequency offset (f) is given by PN = P

. PN

PFD

1

0.8 AV

2

, I

±1 μA

INH

INL

SYNTH

4, 6

)

−119 dBc/Hz Measured at 10 kHz offset; normalized to 1 GHz

1_f

= PN

SYNTH

− 10logf

TOT

− 20logN.

PFD

+ 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and the flicker noise are modeled in ADIsimPLL.

1_f

104 MHz ABP[2:1] = 00 (2.9 ns antibacklash pulse width)

4, 5

)

−222 dBc/Hz PLL loop bandwidth = 500 kHz

V p-p Biased at AVDD/2 (ac coupling ensures AVDD/2 bias)

DD

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

Rev. 0 | Page 3 of 8

ADF4002-EP

TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted. Operating temperature range is −55°C to +125°C.

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MAX

to T

MIN

,

Table 2.

1

Parameter Limit

Unit Description

t1 10 ns min DATA to CLK setup time
t2 10 ns min DATA to CLK hold time
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
t6 20 ns min LE pulse width

1

Guaranteed by design, but not production tested.

Timing Diagram

t

t

3

4

CLK

DATA

LE

LE

DB23 (MSB)

t

t

1

2

DB22

DB2

DB1 (CONTROL

BIT C2)

Figure 2. Timing Diagram

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

09187-022

Rev. 0 | Page 4 of 8

ADF4002-EP

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.6 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND1 −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND1 −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND1 −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND1 −0.3 V to AVDD + 0.3 V
Operating Temperature Range

Industrial −55°C to +125°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = CPGND = 0 V.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

THERMAL CHARACTERISTICS

Table 4. Thermal Impedance

Package Type θJA Unit

TSSOP (RU-16) 150.4 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 5 of 8

ADF4002-EP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

1

R

SET

CP

CPGND

AGND
RFINB
RF

IN

AV

REF

A

DD

IN

INDICATOR

2

3

4

ADF4002-EP

TOP VIEW

5

(Not to Scale)

6

7

8

Figure 3. Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 R

2 CP

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R

25.5

I

where R

MAXCP

= 5.1 kΩ and I

SET

=

R

SET

CP MAX

pin is 0.66 V. The relationship between ICP and R

SET

= 5 mA.

Charge Pump Output. When enabled, this output provides ±I

the external VCO.
3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the RF input.
5 RFINB

Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.
6 RFINA Input to the RF Input. This small-signal input is ac-coupled to the external VCO.
7 AVDD

Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to the AV
8 REFIN

Reference Input. This CMOS input has a nominal threshold of AV

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 DGND Digital Ground.
10 CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit PD1.
11 CLK

Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA

Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is a high

impedance CMOS input.
13 LE

Load Enable. When LE goes high, the data stored in the shift registers is loaded into one of the four latches;

the latch is selected using the control bits. This input is a high impedance CMOS input.
14 MUXOUT

Multiplexer Output. This output allows the lock detect, the scaled RF, or the scaled reference frequency to

be accessed externally.
15 DVDD

Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to the DV
16 VP

Charge Pump Power Supply. This should be greater than or equal to AV

V

can be set to 5.5 V and used to drive a VCO with a tuning voltage of up to 5 V.

P

16

V

P

15

DV

DD

14

MUXOUT

13

LE

12

DATA

11

CLK

10

CE

9

DGND

DD

DD

09187-002

to the external loop filter that, in turn, drives

CP

pin. AVDD must be the same value as DVDD.

/2 and a dc equivalent input resistance

DD

pin. DVDD must be the same value as AVDD.

. In systems where AVDD is 3 V,

DD

SET

is

Rev. 0 | Page 6 of 8

ADF4002-EP

–

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

0

–5

–55°C

–10

–15

–20

–25

POWER (d Bm)

–30

–35

–40

+25°C
+125°C

0 100 200 300 400 500 600

FREQUENCY ( MHz)

Figure 4. RF Input Sensitivity

09187-031

130

–135

–140

–145

–150

–155

–160

–165

PHASE NOISE (dBc/Hz)

–170

–175

–180

100k 1M 10M 100M 1G

PFD FREQUENCY ( Hz )

Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency

09187-033

15

–55°C
+25°C
+125°C

–20

–25

POWER (d Bm)

–30

–35

5 7 9 11 13 15

FREQUENCY (MHz)

Figure 5. RF Input Sensitivity, Low Frequency

REF –4dBm
SAMP LOG 10dB/

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

09187-033

–100

–94.5dBc

1

CENTER 399.995MHz
RES BW 20kHz

ATTN 10dB

1R

VBW 20kHz

Figure 8. Reference Spurs (400 MHz, 1 MHz, 7 kHz)

MKR1 1.000 MHz

–94.5dBc

SPAN 2.2MHz

SWEEP 21ms (601p ts)

09187-030

70

–80

–90

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

–140

–150

–160

1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz )

rms NOISE = 0.07 DEGREES

09187-031

Figure 6. Integrated Phase Noise (400 MHz, 1 MHz, 50 kHz)

Rev. 0 | Page 7 of 8

ADF4002-EP

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 9. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF4002SRU-EP −55°C to +125°C 16-Lead TSSOP RU-16
ADF4002SRU-EP-RL7 −55°C to +125°C 16-Lead TSSOP RU-16

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09187-0-11/10(0)

Rev. 0 | Page 8 of 8