2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
) Allows Extended
P
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
FUNCTIONAL BLOCK DIAGRAM
AV
DV
DD
DD
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REF
IN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
V
CPGND
P
R
SET
ADF4001
REF
IN
CLK
DATA
LE
RFINA
RF
B
IN
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Operating temperature range (B Version) is –40°C to +85°C.
2
AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
= 10 MHz; f
REF
IN
Specifications subject to change without notice.
= 4.7 k; TA = T
SET
MIN
to T
, unless otherwise noted; dBm referred to 50 .)
MAX
20/200MHz min/max–10/0 dBm min/max
Input Frequency5/104MHz min/maxFor f < 5 MHz, Use DC-Coupled Square Wave
Input Sensitivity
2
–5dBm minAC-Coupled. When DC-Coupled:
Input Capacitance10pF max
3
55MHz max
Range2.7/10kΩ typSee Table V
CP
1.5% typ0.5 V ≤ VCP ≤ VP – 0.5
, Input Current±1µA max
2.7/5.5V min/V max
AV
DD
AVDD/6.0V min/V maxAVDD ≤ VP ≤ 6.0 V
0.4mA maxTA = 25°C
5
6
7
7
= 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
PFD
–161dBc/Hz typ@ 200 kHz PFD Frequency
–153dBc/Hz typ@ 1 MHz PFD Frequency
–99dBc/Hz typ@ 1 kHz Offset and 200 kHz PFD Frequency
–90/–95dBc typ/dBc typ@ 200 kHz/400 kHz and 200 kHz PFD Frequency
DD
DD
(AV
= DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =
DD
(0 to V
0 to V
)
DD
Max (CMOS Compatible)
DD
= 4.7 kΩ
SET
= 4.7 kΩ
SET
≤ VP – 0.5
CP
V min
V max
@ VCXO Output
1
–2–
REV. A
ADF4001
WARNING!
ESD SENSITIVE DEVICE
www.BDTIC.com/ADI
(AV
TIMING CHARACTERISTICS
R
= 4.7 k; TA = T
SET
Parameter(B Version)UnitTest Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
Guaranteed by design but not production tested.
Specifications subject to change without notice.
MIN
to T
, unless otherwise noted; dBm referred to 50 .)
MAX
Limit at
T
to T
MIN
10ns minDATA to CLOCK Setup Time
10ns minDATA to CLOCK Hold Time
25ns minCLOCK High Duration
25ns minCLOCK Low Duration
10ns minCLOCK to LE Setup Time
20ns minLE Pulsewidth
CLOCK
DATA
DB20
(MSB )
= DVDD = 3 V 10%, 5 V 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V;
DD
MAX
t
t
3
4
t
t
1
2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
LE
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
(
TA = 25°C, unless otherwise noted.)
1, 2
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
P
V
to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
P
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V
REF
, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V
ADF4001BRU–40°C to +85°CThin Shrink Small Outline Package (TSSOP)RU-16
ADF4001BRU-REEL–40°C to +85°CThin Shrink Small Outline Package (TSSOP)RU-16
ADF4001BRU-REEL7–40°C to +85°CThin Shrink Small Outline Package (TSSOP)RU-16
ADF4001BCP–40°C to +85°CLead Frame Chip Scale Package (LFCSP)*CP-20
ADF4001BCP-REEL–40°C to +85°CLead Frame Chip Scale Package (LFCSP)*CP-20
ADF4001BCP-REEL7–40°C to +85°CLead Frame Chip Scale Package (LFCSP)*CP-20
EVAL-ADF4001EB2Evaluation Board
*Contact factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
3
GND = AGND = DGND = 0 V.
–3–
ADF4001
www.BDTIC.com/ADI
PIN CONFIGURATIONS
TSSOP
R
SET
CP
CPGND
AGND
RF
IN
RF
IN
AV
REF
1
2
3
4
B
5
A
6
7
DD
8
IN
ADF4001
TOP VIEW
(Not to Scale)
V
16
P
DV
15
DD
MUXOUT
14
LE
13
DATA
12
CLK
11
CE
10
DGND
9
NOTE: TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR)
CPGND 1
AGND 2
AGND 3
B 4
RF
IN
A 5
RF
IN
PIN FUNCTION DESCRIPTIONS
TSSOPLFCSP
Pin No.Pin No.MnemonicFunction
119R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the R
between I
So, with R
and R
CP
= 4.7 kΩ, I
SET
SET
I
CP AX
is
M
23 5.
=
R
SET
CP MAX
= 5 mA.
220CPCharge Pump Output. When enabled, this provides ±I
in turn, drives the external VCO or VCXO.
31CPGNDCharge Pump Ground. This is the ground return path for the charge pump.
42, 3AGNDAnalog Ground. This is the ground return path of the prescaler.
54RF
BComplementary Input to the N counter. This point must be decoupled to the ground
IN
plane with a small bypass capacitor, typically 100 pF. See Figure 3.
65RF
76, 7AV
AInput to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
IN
DD
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
88REF
same value as DV
IN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc
DD.
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled.
99, 10DGNDDigital Ground.
1011CEChip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2.
1112CLKSerial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
1213DATASerial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input.
1314LELoad Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits.
1415MUXOUTThis multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
1516, 17DV
DD
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DV
1618V
same value as AV
P
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems
where V
is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
NC
100k⍀
SW2
REF
IN
NC
SW1
SW3
NO
BUFFER
TO
R COUNTER
Figure 2. Reference Input Stage
RF Input Stage
The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N counter buffer.
2k⍀
1.6V
2k⍀
AV
DD
BIAS
GENERATOR
A
RF
IN
FROM
N COUNTER LATCH
FROM RF
INPUT STAGE
13-BIT N
COUNTER
TO PFD
Figure 4. N Counter
R Counter
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic.
The PFD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that no
dead zone is in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the reference counter
latch, ABP2 and ABP1, control the width of the pulse (see
Table III).
V
P
CHARGE
PUMP
UP
Q1
D1
HI
U1
R DIVIDER
CLR1
DELAY
U3
CP
RFINB
AGND
Figure 3. RF Input Stage
N Counter
The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.
N and R Relationship
The N counter with the R counter make it possible to generate
output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is
fNRf
=×
VCOREFIN
f
is the output frequency of the external voltage cotrolled
VCO
oscillator (VCO).
N is the preset divide ratio of the binary 13-bit counter
(1 to 8,191).
f
is the external reference frequency oscillator.
REFIN
R is the preset divide ratio of the binary 14-bit programmable
reference counter (1 to 16,383).
HI
N DIVIDER
R DIVIDER
N DIVIDER
CP OUTPUT
U2
CLR2
Q2
CPGND
DOWN
D2
Figure 5. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4001 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
–6–
REV. A
DV
www.BDTIC.com/ADI
DD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROLMUXOUT
DGND
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to 0, digital
lock detect is set high when the phase error on three consecutive
phase detector cycles is less than 15 ns. With LDP set to 1, five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than
ADF4001
25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.
INPUT SHIFT REGISTER
The ADF4001 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a summary of how the latches are programmed.
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming
the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the A, B counters are reset. For normal operation, this bit
should be 0. Upon powering up, the F1 bit needs to be disabled,
and the N counter resumes counting in close alignment with the
R counter. (The maximum error is one prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4001 family provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the
condition that PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into Bit
PD1 (on condition that a 1 has also been loaded to PD2), the
device will go into power-down on the occurrence of the next
charge pump event.
When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated power-down), the
following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital clock detect circuitry is reset.
• The RF
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4001. Table V shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Only when
this is 1 is fastlock enabled.
Fastlock Mode Bit
DB10 of the function latch is the fastlock mode bit. When fastlock
is enabled, this bit determines which fastlock mode is used. If the
fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock
mode bit is 1, fastlock mode 2 is selected.
input is debiased.
IN
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain
bit in the N counter latch. The device exits fastlock by having a
0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2.
The device enters fastlock by having a 1 written to the CP gain bit
in the N counter latch. The device exits fastlock under the
control of the timer counter. After the timeout period determined
by the value in TC4–TC1, the CP gain bit in the N counter latch
is automatically reset to 0 and the device reverts to normal mode
instead of fastlock. See Table V for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump
currents. The intent is that the Current Setting 1 is used when
the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed). The normal sequence of events is as follows.
The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the function latch. The truth
table is given in Table V.
Now, when the user wishes to program a new output frequency,
they can simply program the N counter latch with new value for N.
At the same time, they can set the CP gain bit to a 1, which sets
the charge pump with the value in CPI6–CPI4 for a period of
time determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time, the CP gain bit in the N counter latch is reset to 0 and
is now ready for the next time that the user wishes to change the
frequency.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
PD Polarity
This bit sets the PD polarity bit (see Table V).
CP Three-State
This bit sets the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP
output is enabled.
–12–
REV. A
ADF4001
R DIVIDER
RF
IN
PFD
CHARGE
PUMP
N DIVIDER
1
1
LOOP
FILTER
CP
VCXO
13MHz
SYSTEM
CLOCK
ADF4110
ADF4111
ADF4112
ADF4113
REF
IN
CP
RF
IN
A
LOOP
FILTER
VCO
ADF4001
13MHz
RF
IN
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INITIALIZATION LATCH
When C2, C1 = 1, 1, the initialization latch is programmed.
This is essentially the same as the function latch (programmed
when C2, C1 = 1, 0).
However, when the initialization latch is programmed, there is
an additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at a load point when
the N counter data is latched, and the device will begin counting
in close phase alignment.
If the latch is programmed for synchronous power-down (the CE
pin is high; PD1 bit is high; and PD2 bit is low), the internal
pulse also triggers this power-down. The oscillator input
buffer is unaffected by the internal reset pulse, so close phase
alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply VDD.
Program the initialization latch (11 in 2 LSB of input word). Make
sure that F1 bit is programmed to 0.
Do an R load (00 in 2 LSBs).
Do an N load (01 in 2 LSBs).
When the initialization latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, N, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler band gap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.
CE Pin Method
Apply VDD.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the N counter latch (01).
Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
CE can be used to power the device up and down to check
for channel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it has been programmed at least once after V
initially applied.
REV. A
DD
was
Counter Reset Method
Apply VDD.
Do a function latch load (10 in 2 LSBs). As part of this, load 1
to the F1 bit. This enables the counter reset.
Do an R counter load (00 in 2 LSBs).
Do an N counter load (01 in 2 LSBs).
Do a function latch load (10 in 2 LSBs). As part of this, load 0
to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump but does not trigger synchronous
power-down. The counter reset method requires an extra function latch load compared to the initialization latch method.
APPLICATION
Extremely Stable, Low Jitter Reference Clock for GSM Base
Station Transmitter
Figure 7 shows the ADF4001 being used with a VCXO to produce an extremely stable, low jitter reference clock for a GSM
base station local oscillator (LO).
Figure 7. Low Jitter, Stable Clock Source for GSM Base
Station Local Oscillator Circuit
The system reference signal is applied to the circuit at REFIN.
Typical GSM systems would have a very stable OCXO as the
clock source for the entire base station. However, distribution of
this signal around the base station makes it susceptible to
noise and spurious pickup. It is also open to pulling from the
various loads it may need to drive.
The charge pump output of the ADF4001 (Pin 2 of the TSSOP)
drives the loop filter and the 13 MHz VCXO. The VCXO output
is fed back to the RF input of the ADF4001 and also drives the
reference (REF
50 Ω matching between the VCXO output, the LO REF
the RF
terminal of the ADF4001.
IN
) for the LO. A T-circuit configuration provides
IN
IN
, and
–13–
ADF4001
www.BDTIC.com/ADI
COHERENT CLOCK GENERATION
When testing A/D converters, it is often advantageous to use a
coherent test system, that is, a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
function. Figure 8 shows how the ADF4001 can be used to handle
all the possible combinations of the input signal frequency and
sampling rate. The first ADF4001 is phase locked to a VCO. The
output of the VCO is also fed into the N divider of the second
ADF4001. This results in both ADF4001s being coherent with
the REF
MUXOUT signal of the second ADF4001 is coherent with the f
. Since the REFIN comes from the signal generator, the
IN
IN
frequency to the ADC. This is used as fS, the sampling clock.
f
SINE
OUTPUT
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
REF
fS = (fIN N1)/(R1 N2)
IN
R1
ADF4001
N1
CP
RF
RF
IN
IN
LOOP
FILTER
A
IN
CONVERTER
SAMPLING
CLOCK
f
VCO
100MHz
A/D
UNDER
TEST
S
REF
R1
IN
4
1
N1
CP
RF
RF
LOOP
FILTER
IN
ADF4001
R2
REF
IN
52MHz
MASTER
CLOCK
1300
486
N2
CP
RF
RF
LOOP
FILTER
IN
ADF4001
R3
REF
IN
65
24
N3
CP
RF
RF
LOOP
FILTER
IN
ADF4001
Figure 9. Tri-Band System Clock Generation
V
P
VCXO
13MHz
VCXO
19.44MHz
VCXO
19.2MHz
13MHz SYSTEM
CLOCK FOR GSM
19.44MHz SYSTEM
CLOCK FOR WCDMA
19.2MHz SYSTEM
CLOCK FOR CDMA
RF
N2
IN
MUXOUT
NC7S04
ADF4001
Figure 8. Coherent Clock Generator
TRI-BAND CLOCK GENERATION CIRCUIT
In multiband applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz master clock. The low RF
specification and the ability to program R and N values as
f
MIN
low as 1 makes the ADF4001 suitable for this. Other f
OUT
clock frequencies can be realized using the formula
fREFNR
=×÷
OUTIN
()
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic 1 is applied to the IN input.
The low cost switch is available in both SOT-23 and micro
SOIC packages.
FREF
IN
V
DD
7
AV
CPGND
15
DV
DD
ADF4001
3
POWER-DOWN CONTROL
16
10
CE
V
DD
P
CP
1
R
SET
6
RFINA
5
RF
B
IN
AGND4DGND
9
V
S
DD
IN
ADG702
D
GND
V
GND
51
CC
VCO
OR
VCXO
2
LOOP
FILTER
10k
100pF
100pF
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
100pF
100pF
18
RF
18
18
OUT
–14–
Figure 10. Local Oscillator Shutdown Circuit
REV. A
ADF4001
www.BDTIC.com/ADI
INTERFACING
The ADF4001 family has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control
the data transfer. When LE (latch enable) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of SCLK will be transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 ms. This is certainly more than adequate
for systems with typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 11 shows the interface between the ADF4001 family and
the ADuC812 MicroConverter
®
. Since the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4001 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
On first applying power to the ADF4001 family, it needs three
writes (one each to the R counter latch, the N counter latch, and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will
be 166 kHz.
ADuC812
SCLOCK
MOSI
I/O PORTS
ADF4001
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
Figure 11. ADuC812 to ADF4001 Family Interface
ADSP-2181 Interface
Figure 12 shows the interface between the ADF4001 family and
the ADSP-21xx digital signal processor. The ADF4001 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
autobuffered mode, and then write to the transmit register of
the DSP. This last operation initiates the autobuffer transfer.
ADSP-21xx
SCLK
DT
TFS
I/O FLAGS
ADF4001
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
Figure 12. ADSP-21xx to ADF4001 Family Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip package (CP-20) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edge of the pad pattern. This will ensure that
shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
–16–
REV. A
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