ANALOG DEVICES ADF4001 Service Manual

a
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200 MHz Clock Generator PLL
ADF4001
FEATURES 200 MHz Bandwidth
2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (V
) Allows Extended
P
Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113 Typical Operating Current 4.5 mA Ultralow Phase Noise 16-Lead TSSOP 20-Lead LFCSP
APPLICATIONS Clock Generation Low Frequency PLLs Low Jitter Clock Source Clock Smoothing Frequency Translation SONET, ATM, ADM, DSLAM, SDM

FUNCTIONAL BLOCK DIAGRAM

AV
DV
DD
DD

GENERAL DESCRIPTION

The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REF
IN
frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an exter­nal loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation.
V
CPGND
P
R
SET
ADF4001
REF
IN
CLK
DATA
LE
RFINA
RF
B
IN
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
24-BIT
INPUT REGISTER
SD
OUT
22
CE AGND DGND
14-BIT
R COUNTER
14
R COUNTER
LATCH
FUNCTION
LATCH
N COUNTER
LATCH
13
13-BIT
N COUNTER
REFERENCE
PHASE
FREQUENCY
DETECTOR
LOCK DETECT
CPI3
AV
DD
SD
OUT
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CURRENT SETTING 1
CPI2
MUX
M3
CHARGE
PUMP
CPI1
M2
M1
CURRENT SETTING 2
CPI6
CPI5
HIGH Z
CP
CPI4
MUXOUT
ADF4001–SPECIFICATIONS
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CPGND = 0 V; R
Parameter B Version Unit Test Conditions/Comments
RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit
RF Input Frequency 5/165 MHz min/max RF Input Sensitivity –10/0 dBm min/max
RF CHARACTERISTICS (5 V)
RF Input Frequency 10/200 MHz min/max –5/0 dBm min/max
REF
CHARACTERISTICS See Figure 2 for Input Circuit
IN
REF
IN
REF
IN
REF
IN
REFIN Input Current ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
I
Sink/Source Programmable: See Table V
CP
High Value 5 mA typ With R Low Value 625 µA typ Absolute Accuracy 2.5 % typ With R R
SET
I
Three-State Leakage Current 1 nA typ
CP
Sink and Source Current Matching 2 % typ 0.5 V ≤ V I
vs. V
CP
ICP vs. Temperature 2 % typ VCP = VP/2
LOGIC INPUTS
V
, Input High Voltage 0.8 × DV
INH
V
, Input Low Voltage 0.2 × DV
INL
I
INH/IINL
CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage DVDD – 0.4 V min IOH = 500 µA VOL, Output Low Voltage 0.4 V max IOL = 500 µA
POWER SUPPLIES
AV
DD
DV
DD
V
P
4
I
(AIDD + DIDD)
DD
ADF4001 5.5 mA max 4.5 mA typical
I
P
Low Power Sleep Mode 1 µA typ
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor
Phase Noise Performance
200 MHz Output
Spurious Signals
200 MHz Output
NOTES
1
Operating temperature range (B Version) is –40°C to +85°C.
2
AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.
3
Guaranteed by design. Sample tested to ensure compliance.
4
TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
= 10 MHz; f
REF
IN
Specifications subject to change without notice.
= 4.7 k; TA = T
SET
MIN
to T
, unless otherwise noted; dBm referred to 50 .)
MAX
20/200 MHz min/max –10/0 dBm min/max
Input Frequency 5/104 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave
Input Sensitivity
2
–5 dBm min AC-Coupled. When DC-Coupled:
Input Capacitance 10 pF max
3
55 MHz max
Range 2.7/10 k typ See Table V
CP
1.5 % typ 0.5 V ≤ VCP VP – 0.5
, Input Current ±1 µA max
2.7/5.5 V min/V max AV
DD
AVDD/6.0 V min/V max AVDD VP 6.0 V
0.4 mA max TA = 25°C
5
6
7
7
= 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
PFD
–161 dBc/Hz typ @ 200 kHz PFD Frequency –153 dBc/Hz typ @ 1 MHz PFD Frequency
–99 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
DD
DD
(AV
= DVDD = 3 V 10%, 5 V 10%; AVDD VP 6.0 V ; AGND = DGND =
DD
(0 to V
0 to V
)
DD
Max (CMOS Compatible)
DD
= 4.7 k
SET
= 4.7 k
SET
VP – 0.5
CP
V min V max
@ VCXO Output
1
–2–
REV. A
ADF4001
WARNING!
ESD SENSITIVE DEVICE
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(AV

TIMING CHARACTERISTICS

R
= 4.7 k; TA = T
SET
Parameter (B Version) Unit Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
Guaranteed by design but not production tested. Specifications subject to change without notice.
MIN
to T
, unless otherwise noted; dBm referred to 50 .)
MAX
Limit at T
to T
MIN
10 ns min DATA to CLOCK Setup Time 10 ns min DATA to CLOCK Hold Time 25 ns min CLOCK High Duration 25 ns min CLOCK Low Duration 10 ns min CLOCK to LE Setup Time 20 ns min LE Pulsewidth
CLOCK
DATA
DB20
(MSB )
= DVDD = 3 V 10%, 5 V 10%; AVDD VP 6.0 V ; AGND = DGND = CPGND= 0 V;
DD
MAX
t
t
3
4
t
t
1
2
DB19
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
LE
LE
Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(
TA = 25°C, unless otherwise noted.)
1, 2
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
P
V
to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
P
Digital I/O Voltage to GND . . . . . . . . . –0.3 V to V
Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V
REF
, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V
IN
A to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV
RF
IN
+ 0.3 V
DD
+ 0.3 V
P
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . .150°C

ORDERING GUIDE

Model Temperature Range Package Description Package Option
ADF4001BRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-16 ADF4001BRU-REEL –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-16 ADF4001BRU-REEL7 –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-16 ADF4001BCP –40°C to +85°CLead Frame Chip Scale Package (LFCSP)* CP-20 ADF4001BCP-REEL –40°C to +85°CLead Frame Chip Scale Package (LFCSP)* CP-20 ADF4001BCP-REEL7 –40°C to +85°CLead Frame Chip Scale Package (LFCSP)* CP-20 EVAL-ADF4001EB2 Evaluation Board
*Contact factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
t
5
TSSOP θ LFCSP θ LFCSP θ
Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W
JA
Thermal Impedance (Paddle Soldered) . . 122°C/W
JA
Thermal Impedance (Paddle Not Soldered) 216°C/W
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
This device is a high performance RF integrated circuit with an ESD rating of
<2 kand it is ESD sensitive. Proper precautions should be taken for handling and assembly.
3
GND = AGND = DGND = 0 V.
–3–
ADF4001
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PIN CONFIGURATIONS

TSSOP
R
SET
CP
CPGND
AGND
RF
IN
RF
IN
AV
REF
1
2
3
4
B
5
A
6
7
DD
8
IN
ADF4001
TOP VIEW
(Not to Scale)
V
16
P
DV
15
DD
MUXOUT
14
LE
13
DATA
12
CLK
11
CE
10
DGND
9
NOTE: TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR)
CPGND 1
AGND 2 AGND 3
B 4
RF
IN
A 5
RF
IN

PIN FUNCTION DESCRIPTIONS

TSSOP LFCSP Pin No. Pin No. Mnemonic Function
119R
SET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the R between I
So, with R
and R
CP
= 4.7 k, I
SET
SET
I
CP AX
is
M
23 5.
=
R
SET
CP MAX
= 5 mA.
220CPCharge Pump Output. When enabled, this provides ±I
in turn, drives the external VCO or VCXO. 31CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 54RF
BComplementary Input to the N counter. This point must be decoupled to the ground
IN
plane with a small bypass capacitor, typically 100 pF. See Figure 3. 65RF 7 6, 7 AV
A Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
IN
DD
Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
88REF
same value as DV
IN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc
DD.
equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL
or CMOS crystal oscillator or can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump
output into three-state mode. Taking the pin high will power up the device, depending on
the status of the power-down bit F2. 11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The
data is latched into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control
bits. This input is a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is
loaded into one of the four latches, the latch being selected by using the control bits. 14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally. 15 16, 17 DV
DD
Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the
digital ground plane should be placed as close as possible to this pin. DV
16 18 V
same value as AV
P
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems
where V
is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning
DD
DD
.
range of up to 5 V.
LFCSP
DD
SET
19 R
20 CP
18 VP17 DVDD16 DV
PIN 1 INDICATOR
ADF4001
TOP VIEW
6
7
DD
DD
AV
AV
15 MUXOUT 14 LE 13 DATA 12 CLK 11 CE
8
IN
REF
DGND 9
DGND 10
pin is 0.66 V. The relationship
SET
to the external loop filter which,
CP
must have the
DD
must be the
DD
–4–
REV. A
Typical Performance Characteristics–ADF4001
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0
–5
–10
–15
–20
AMPLITUDE – dBm
–25
–30
–35
0
TA = +25C
50 100 150 200 250
FREQUENCY – MHz
TPC 1. Input Sensitivity, V
0
–5
–10
–15
–20
AMPLITUDE – dBm
–25
–30
0
510152025
FREQUENCY – MHz
TPC 2. Input Sensitivity, V
TA = +85C
TA = –40C
= 3.3 V, 100 pF on RF
DD
= 3.3 V, 100 pF on RF
DD
10dB/DIVISION R
–40
–50
–60
–70
–80
–90
–100
–110
PHASE NOISE – dBc/Hz
–120
–130
–140
100
FREQUENCY OFFSET FROM 200MHz CARRIER – Hz
IN
IN
TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
–80
–90
–100
REFERENCE LEVEL =
–200kHz –100kHz 0200MHz 100kHz 200kHz
TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)
= –40dBc/Hz rms NOISE = 0.229 DEGREES
L
0.229 rms
1k 10k 100k 1M
VDD = 3V, VP = 5V
= 2.5mA
I
CP
PFD FREQUENCY = 200kHz
–5.7dBm
LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 300Hz VIDEO BANDWIDTH = 300Hz SWEEP = 4.2 SECONDS AVERAGES = 20
–92.3dBc
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
–80
–90
–100
REFERENCE LEVEL =
–5.7dBm
–2kHz –1kHz 200MHz 1kHz 2kHz 0
VDD = 3V, VP = 5V
= 2.5mA
I
CP
PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 26
–99.2dBc/Hz
TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)
REV. A
–5–
ADF4001
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CIRCUIT DESCRIPTION Reference Input Section
The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
NC
100k
SW2
REF
IN
NC
SW1
SW3
NO
BUFFER
TO R COUNTER
Figure 2. Reference Input Stage

RF Input Stage

The RF input stage is shown in Figure 3. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the N counter buffer.
2k
1.6V
2k
AV
DD
BIAS
GENERATOR
A
RF
IN
FROM
N COUNTER LATCH
FROM RF
INPUT STAGE
13-BIT N
COUNTER
TO PFD
Figure 4. N Counter

R Counter

The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that no dead zone is in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse (see Table III).
V
P
CHARGE PUMP
UP
Q1
D1
HI
U1
R DIVIDER
CLR1
DELAY
U3
CP
RFINB
AGND
Figure 3. RF Input Stage

N Counter

The N CMOS counter allows a wide ranging division ratio in the PLL feedback counter. Division ratios of 1 to 8191 are allowed.
N and R Relationship
The N counter with the R counter make it possible to generate output frequencies that are spaced only by the reference fre­quency divided by R. The equation for the VCO frequency is
fNRf
VCO REFIN
f
is the output frequency of the external voltage cotrolled
VCO
oscillator (VCO).
N is the preset divide ratio of the binary 13-bit counter (1 to 8,191).
f
is the external reference frequency oscillator.
REFIN
R is the preset divide ratio of the binary 14-bit programmable
reference counter (1 to 16,383).
HI
N DIVIDER
R DIVIDER
N DIVIDER
CP OUTPUT
U2
CLR2
Q2
CPGND
DOWN
D2
Figure 5. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4001 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Table V shows the full truth table. Figure 6 shows the MUXOUT section in block diagram form.
–6–
REV. A
DV
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DD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
MUX
CONTROL MUXOUT
DGND
Figure 6. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than
ADF4001
25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 knominal. When lock has been detected, this output will be high with narrow low-going pulses.

INPUT SHIFT REGISTER

The ADF4001 digital section includes a 24-bit input shift regis­ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I. Table II shows a sum­mary of how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2 C1 Data Latch
00R Counter 01N Counter 10Function Latch 11Initialization Latch
RESERVED
DB21
DB22DB23
XXX
RESERVED
XX
RESERVED
XX
CP
GAIN
DB21
DB22DB23
POWER-
DB21
DB22DB23
Table II. ADF4001 Family Latch Summary
REFERENCE COUNTER LATCH
TEST
DETECT
PRECISION
MODE
BITS
T1
LOCK
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ANTI-
BACKLASH
WIDTH
ABP2
R12 R11 R10
14-BIT REFERENCE COUNTER
R8R9
CONTROL
C2 (0) C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6
N COUNTER LATCH
13-BIT N COUNTER
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
N2
N10N11
N8N9N12N13 N7G1
N6 N5 N4
N3
N1
XXXXXX
RESERVED
CONTROL
C2 (0)
FUNCTION LATCH
CPI3CPI4
CURRENT
SETTING
1
CURRENT
SETTING
DOWN 2
2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
TIMER COUNTER
CONTROL
TC3 TC2 TC1
MODE
FAST LOCK
ENABLE
FASTLOCK
F4F5
CP
THREE-
STAT E
PHASE
POLARITY
DETECTOR
MUXOUT
CONTROL
DOWN 1
POWER-
RESET
COUNTER
C2 (1) C1 (0)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2
CONTROL
BITS
BITS
C1 (1)
BITS
INITIALIZATION LATCH
RESERVED
DB21
DB22DB23
XX
X = DON’T CARE
CPI3CPI4
CURRENT
SETTING
1
CURRENT
SETTING
DOWN 2
POWER-
2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
TIMER COUNTER
CONTROL
TC3 TC2 TC1
REV. A
–7–
MODE
FAST LOCK
ENABLE
FASTLOCK
F4F5
CP
THREE-
STAT E
PHASE
POLARITY
DETECTOR
MUXOUT
CONTROL
DOWN 1
POWER-
RESET
COUNTER
C2 (1) C1 (1)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2
CONTROL
BITS
ADF4001
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Table III. Reference Counter Latch Map
RESERVED
DB21
DB22DB23
XXX
X = DON’T CARE
TEST
MODE
LOCK
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DETECT
PRECISION
BITS
T1
ANTI-
BACKLASH
WIDTH
ABP2
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
002.9ns
011.3ns
106.0ns
112.9ns
R12 R11 R10
R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO
000.......... 0011
000.......... 0102
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 10016380
111.......... 10116381
111.......... 11016382
111.......... 11116383
14-BIT REFERENCE COUNTER
R8R9
CONT ROL
BITS
C2 (0)
C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
LDP OPERATION
0THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
1FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
–8–
REV. A
Table IV. N Counter Latch Map
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ADF4001
RESERVED
CP GAIN
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21
DB22DB23
X
G1
X X
N13 N12 N11 N3 N2 N1 N COUNTER DIVIDE RATIO
000.......... 0011
000.......... 0102
000.......... 0113
000.......... 1004
............. ....
............. ....
............. ....
111.......... 1008188
111.......... 1018189
111.......... 1108190
111.......... 1118191
F4 (FUNCTION LATCH)
FASTLOCK ENABLE CP GAIN OPERATION
0 0CHARGE PUMP CURRENT SETTING
0 1CHARGE PUMP CURRENT SETTING
1 0CHARGE PUMP CURRENT SETTING
1 1CHARGE PUMP CURRENT IS
LATCH DESCRIPTION.
13-BIT N COUNTER
1 IS PERMANENTLY USED
2 IS PERMANENTLY USED
1 IS USED
SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION
N1N2N3N4N5N6N7N8N9N10N11N12N13
RESERVED
XXX X
X = DON’T CARE
C2 (0) C1 (1)
X
CONTROL
BITS
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON’T CARE BITS.
REV. A
–9–
ADF4001
www.BDTIC.com/ADI
Table V. Function Latch Map
RESERVED
DB22DB23
X
X
X = DON’T CARE
CURRENT
SETTING
POWER-
DB21
DOWN 2
2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CURRENT
SETTING
1
CPI3CPI4
TC4 TC3 TC2 TC1 (PFD CYCLES)
00003 00017 001011 001115 010019 010123 011027 011131 100035 100139 101043 101147 110051 110155 111059 111163
CPI1CPI2CPI5CPI6 TC4PD2
TIME R COUNTER
CONT ROL
TC3 TC2 TC1
TIME OUT
MODE
FASTLOCK
F4 F5 FASTLOCK MODE
0X FASTLOCK DISABLED 10 FASTLOCK MODE 1 11 FASTLOCK MODE 2
CP
STAT E
THREE-
ENABLE
FASTLOCK
F4F5
F3 CHARGE PUMP OUTPUT
0NORMAL
1THREE-STATE
M3 M2 M1 OUTPUT
000THREE-STATE OUTPUT 001DIGITAL LOCK DETECT 010N DIVIDER OUTPUT 011AVDD 100R DIVIDER OUTPUT 101N-CHANNEL OPEN-DRAIN
110SERIAL DATA OUTPUT 111DGND
PHASE
POLARITY
DETECTOR
F2
PHASE DETECTOR F2 POLARITY 0NEGATIVE 1POSITIVE
MUXOUT
CONT ROL
DOWN 1
POWER-
PD1
M1M2M3F3
COUNTER F1 OPERATION
0 NORMAL 1 R, N COUNTER
LOCK DETECT
CONT ROL
RESET
COUNTER
C2 (1) C1 (0)
F1
HELD IN RESET
BITS
CPI6 CPI5 CP14 ICP (mA)
CPI3 CPI2 CPI1 2.7k 4.7k 10k
0001.088 0.625 0.294
0012.176 1.25 0.588
0103.264 1.875 0.882
0114.352 2.5 1.176
1005.44 3.125 1.47
1016.528 3.75 1.764
1107.616 4.375 2.058
1118.704 5.0 2.352
CE PIN PD2 PD1 MODE
0 XXASYNCHRONOUS POWER-DOWN 1X0NORMAL OPERATION 101ASYNCHRONOUS POWER-DOWN 111SYNCHRONOUS POWER-DOWN
–10–
REV. A
Table VI. Initialization Latch Map
www.BDTIC.com/ADI
ADF4001
RESERVED
DB22DB23
XX
X = DON’T CARE
CURRENT
SETTING
POWER-
DB21
DOWN 2
2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CURRENT
SETTING
1
CPI3CPI4
TC4 TC3 TC2 TC1 (PFD CYCLES)
00003 00017 001011 001115 010019 010123 011027 011131 100035 100139 101043 101147 110051 110155 111059 111163
CPI1CPI2CPI5CPI6 TC4PD2
TIME R COUNTER
CONT ROL
TC3 TC2 TC1
TIME OUT
MODE
FAST LOCK
F4 F5 FASTLOCK MODE
0X FASTLOCK DISABLED 10 FASTLOCK MODE 1 11 FASTLOCK MODE 2
CP
STAT E
THREE-
ENABLE
FASTLOCK
F4F5
F3 CHARGE PUMP OUTPUT
0NORMAL
1THREE-STATE
M3 M2 M1 OUTPUT
000THREE-STATE OUTPUT 001DIGITAL LOCK DETECT 010N DIVIDER OUTPUT 011AVDD 100R DIVIDER OUTPUT 101N-CHANNEL OPEN-DRAIN
110SERIAL DATA OUTPUT 111DGND
PHASE
POLARITY
DETECTOR
F2
PHASE DETECTOR F2 POLARITY 0NEGATIVE 1POSITIVE
MUXOUT
CONT ROL
DOWN 1
POWER-
PD1
M1M2M3F3
COUNTER F1 OPERATION
0 NORMAL 1 R, N COUNTER
LOCK DETECT
CONT ROL
RESET
COUNTER
F1
C2 (1) C1 (1)
HELD IN RESET
BITS
CPI6 CPI5 CP14 ICP (mA)
CPI3 CPI2 CPI1 2.7k 4.7k 10k
0001.088 0.625 0.294
0012.176 1.25 0.588
0103.264 1.875 0.882
0114.352 2.5 1.176
1005.44 3.125 1.47
1016.528 3.75 1.764
1107.616 4.375 2.058
1118.704 5.0 2.352
CE PIN PD2 PD1 MODE
0 XXASYNCHRONOUS POWER-DOWN 1X0NORMAL OPERATION 101ASYNCHRONOUS POWER-DOWN 111SYNCHRONOUS POWER-DOWN
REV. A
–11–
ADF4001
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FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch will be pro­grammed. Table V shows the input data format for programming the function latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled, and the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.)

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF4001 family provide programmable power-down modes. They are enabled by the CE pin.
When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device pow­ers down immediately after latching a 1 into Bit PD1, with the condition that PD2 has been loaded with a 0.
In the programmed synchronous power-down, the device power­down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into Bit PD1 (on condition that a 1 has also been loaded to PD2), the device will go into power-down on the occurrence of the next charge pump event.
When a power-down is activated (either synchronous or asyn­chronous mode, including CE pin activated power-down), the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the ADF4001. Table V shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Only when this is 1 is fastlock enabled.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if the fastlock mode bit is 1, fastlock mode 2 is selected.
input is debiased.
IN
Fastlock Mode 1
The charge pump current is switched to the contents of Current Setting 2.
The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current Setting 2.
The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4–TC1, the CP gain bit in the N counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Table V for the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the RF output is stable and the system is in a static state. Cur­rent Setting 2 is meant to be used when the system is dynamic and in a state of change (i.e., when a new output frequency is programmed). The normal sequence of events is as follows.
The user initially decides what the preferred charge pump cur­rents are going to be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2.
At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. This is controlled by the Timer Counter Control Bits DB14 to DB11 (TC4–TC1) in the function latch. The truth table is given in Table V.
Now, when the user wishes to program a new output frequency, they can simply program the N counter latch with new value for N. At the same time, they can set the CP gain bit to a 1, which sets the charge pump with the value in CPI6–CPI4 for a period of time determined by TC4–TC1. When this time is up, the charge pump current reverts to the value set by CPI3–CPI1. At the same time, the CP gain bit in the N counter latch is reset to 0 and is now ready for the next time that the user wishes to change the frequency.
Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1.

Charge Pump Currents

CPI3, CPI2, CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, CPI4 program Current Setting 2 for the charge pump. The truth table is given in Table V.

PD Polarity

This bit sets the PD polarity bit (see Table V).

CP Three-State

This bit sets the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.
–12–
REV. A
ADF4001
R DIVIDER
RF
IN
PFD
CHARGE
PUMP
N DIVIDER
1
1
LOOP
FILTER
CP
VCXO
13MHz
SYSTEM
CLOCK
ADF4110 ADF4111 ADF4112 ADF4113
REF
IN
CP
RF
IN
A
LOOP
FILTER
VCO
ADF4001
13MHz
RF
IN
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INITIALIZATION LATCH

When C2, C1 = 1, 1, the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0).
However, when the initialization latch is programmed, there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at a load point when the N counter data is latched, and the device will begin counting in close phase alignment.
If the latch is programmed for synchronous power-down (the CE pin is high; PD1 bit is high; and PD2 bit is low), the internal pulse also triggers this power-down. The oscillator input buffer is unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the internal reset pulse is again activated. However, successive N counter loads will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After initially powering up the device, there are three ways to program the device.

Initialization Latch Method

Apply VDD.
Program the initialization latch (11 in 2 LSB of input word). Make sure that F1 bit is programmed to 0.
Do an R load (00 in 2 LSBs).
Do an N load (01 in 2 LSBs).
When the initialization latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, N, and timeout counters to load state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allow­ing close phase alignment when counting resumes.
3. Latching the first N counter data after the initialization word will activate the same internal reset pulse. Successive N loads will not trigger the internal reset pulse unless there is another initialization.

CE Pin Method

Apply VDD.
Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately.
Program the function latch (10). Program the R counter latch (00). Program the N counter latch (01).
Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state.
CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after V initially applied.
REV. A
DD
was

Counter Reset Method

Apply VDD.
Do a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset.
Do an R counter load (00 in 2 LSBs).
Do an N counter load (01 in 2 LSBs).
Do a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initial­ization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump but does not trigger synchronous power-down. The counter reset method requires an extra func­tion latch load compared to the initialization latch method.
APPLICATION Extremely Stable, Low Jitter Reference Clock for GSM Base Station Transmitter
Figure 7 shows the ADF4001 being used with a VCXO to pro­duce an extremely stable, low jitter reference clock for a GSM base station local oscillator (LO).
Figure 7. Low Jitter, Stable Clock Source for GSM Base Station Local Oscillator Circuit
The system reference signal is applied to the circuit at REFIN. Typical GSM systems would have a very stable OCXO as the clock source for the entire base station. However, distribution of this signal around the base station makes it susceptible to noise and spurious pickup. It is also open to pulling from the various loads it may need to drive.
The charge pump output of the ADF4001 (Pin 2 of the TSSOP) drives the loop filter and the 13 MHz VCXO. The VCXO output is fed back to the RF input of the ADF4001 and also drives the reference (REF 50 Ω matching between the VCXO output, the LO REF the RF
terminal of the ADF4001.
IN
) for the LO. A T-circuit configuration provides
IN
IN
, and
–13–
ADF4001
www.BDTIC.com/ADI

COHERENT CLOCK GENERATION

When testing A/D converters, it is often advantageous to use a coherent test system, that is, a system that ensures a specific relationship between the A/D converter input signal and the A/D converter sample rate. Thus, when doing an FFT on this data, there is no longer any need to apply the window weighting function. Figure 8 shows how the ADF4001 can be used to handle all the possible combinations of the input signal frequency and sampling rate. The first ADF4001 is phase locked to a VCO. The output of the VCO is also fed into the N divider of the second ADF4001. This results in both ADF4001s being coherent with the REF MUXOUT signal of the second ADF4001 is coherent with the f
. Since the REFIN comes from the signal generator, the
IN
IN
frequency to the ADC. This is used as fS, the sampling clock.
f
SINE
OUTPUT
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
REF
fS = (fIN N1)/(R1 N2)
IN
R1
ADF4001
N1
CP
RF
RF
IN
IN
LOOP
FILTER
A
IN
CONVERTER
SAMPLING
CLOCK
f
VCO
100MHz
A/D
UNDER
TEST
S
REF
R1
IN
4
1
N1
CP
RF
RF
LOOP
FILTER
IN
ADF4001
R2
REF
IN
52MHz
MASTER
CLOCK
1300
486
N2
CP
RF
RF
LOOP
FILTER
IN
ADF4001
R3
REF
IN
65
24
N3
CP
RF
RF
LOOP
FILTER
IN
ADF4001
Figure 9. Tri-Band System Clock Generation
V
P
VCXO 13MHz
VCXO
19.44MHz
VCXO
19.2MHz
13MHz SYSTEM
CLOCK FOR GSM
19.44MHz SYSTEM
CLOCK FOR WCDMA
19.2MHz SYSTEM
CLOCK FOR CDMA
RF
N2
IN
MUXOUT
NC7S04
ADF4001
Figure 8. Coherent Clock Generator

TRI-BAND CLOCK GENERATION CIRCUIT

In multiband applications, it is necessary to realize different clocks from one master clock frequency. For example, GSM uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to use the ADF4001 to generate GSM, WCDMA, and CDMA system clocks from a single 52 MHz master clock. The low RF
specification and the ability to program R and N values as
f
MIN
low as 1 makes the ADF4001 suitable for this. Other f
OUT
clock frequencies can be realized using the formula
f REF N R
÷
OUT IN
()

SHUTDOWN CIRCUIT

The circuit in Figure 10 shows how to shut down both the ADF4001 and the accompanying VCO. The ADG702 switch goes open circuit when a Logic 1 is applied to the IN input. The low cost switch is available in both SOT-23 and micro SOIC packages.
FREF
IN
V
DD
7
AV
CPGND
15
DV
DD
ADF4001
3
POWER-DOWN CONTROL
16
10
CE
V
DD
P
CP
1
R
SET
6
RFINA
5
RF
B
IN
AGND4DGND
9
V
S
DD
IN
ADG702
D
GND
V
GND
51
CC
VCO
OR
VCXO
2
LOOP
FILTER
10k
100pF
100pF
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM IN THE INTEREST OF GREATER CLARITY.
100pF
100pF
18
RF
18
18
OUT
–14–
Figure 10. Local Oscillator Shutdown Circuit
REV. A
ADF4001
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INTERFACING

The ADF4001 family has a simple SPI® compatible serial inter­face for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 ms. This is certainly more than adequate for systems with typical lock times in hundreds of microseconds.

ADuC812 Interface

Figure 11 shows the interface between the ADF4001 family and the ADuC812 MicroConverter
®
. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4001 family needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer.
On first applying power to the ADF4001 family, it needs three writes (one each to the R counter latch, the N counter latch, and the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control power­down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maxi­mum rate at which the output frequency can be changed will be 166 kHz.
ADuC812
SCLOCK
MOSI
I/O PORTS
ADF4001
SCLK
SDATA
LE
CE
MUXOUT (LOCK DETECT)
Figure 11. ADuC812 to ADF4001 Family Interface

ADSP-2181 Interface

Figure 12 shows the interface between the ADF4001 family and the ADSP-21xx digital signal processor. The ADF4001 family needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
ADSP-21xx
SCLK
DT
TFS
I/O FLAGS
ADF4001
SCLK
SDATA
LE
CE
MUXOUT (LOCK DETECT)
Figure 12. ADSP-21xx to ADF4001 Family Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. The lead should be centered on the pad to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edge of the pad pattern. This will ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via.
The user should connect the printed circuit board thermal pad to AGND.
REV. A
–15–
ADF4001
www.BDTIC.com/ADI

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
PIN 1
INDICATOR
1.00
0.90
0.80
SEATING
PLANE
0.15
0.05
4.50
4.40
4.30
PIN 1
16
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AB
0.10
0.30
0.19
9
81
1.20 MAX
6.40 BSC
SEATING
PLANE
0.20
0.09 8 0
20-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-20)
Dimensions shown in millimeters
0.60
MAX
0.75
0.55
0.35
0.08
0.60
MAX
16
15
11
10
BOTTOM
VIEW
0.30
0.23
0.18
20
1
5
6
4.0
BSC SQ
TOP
VIEW
12MAX
0.80 MAX
0.65 NOM
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
0.20 REF
3.75
BSC SQ
0.05
0.02
0.00
COPLANARITY
0.75
0.60
0.45
0.25 MIN
2.25
2.10 SQ
1.95
C02569–0–10/03(A)

Revision History

Location Page
10/03—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
–16–
REV. A
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