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ADE7953
Service Manual
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Service Manual
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ANALOG DEVICES ADE7953 Service Manual

Single Phase, Multifunction Metering IC
Data Sheet

FEATURES

Measures active, reactive, and apparent energy; sampled
waveform; current and voltage rms
Provides a second current input for neutral current
measurement
Less than 0.1% error in active and reactive energy
measurements over a dynamic range of 3000:1
Less than 0.2% error in instantaneous IRMS measurement
over a dynamic range of 1000:1
Provides apparent energy measurement and instantaneous
power readings
1.23 kHz bandwidth operation Flexible PGA gain stage (up to ×22) Includes internal integrators for use with Rogowski coil sensors
2
SPI, I
C, or UART communication

GENERAL DESCRIPTION

The ADE7953 is a high accuracy electrical energy measurement IC intended for single phase applications. It measures line voltage and current and calculates active, reactive, and apparent energy, as well as instantaneous rms voltage and current.

FUNCTIONAL BLOCK DIAGRAM

REF RESET VDD VINTA VINTD
with Neutral Current Measurement
ADE7953
The device incorporates three Σ- ADCs with a high accuracy energy measurement core. The second input channel simulta­neously measures neutral current and enables tamper detection and neutral current billing. The additional channel incorporates a complete signal path that allows a full range of measurements. Each input channel supports independent and flexible gain stages, making the device suitable for use with a variety of current sensors such as current transformers (CTs) and low value shunt resistors. Two on-chip integrators facilitate the use of Rogowski coil sensors.
The ADE7953 provides access to on-chip meter registers via a variety of communication interfaces including SPI, I Two configurable low jitter pulse output pins provide outputs that are proportional to active, reactive, or apparent energy, as well as current and voltage rms. A full range of power quality information such as overcurrent, overvoltage, peak, and sag detection are accessible via the external
IRQ
pin. Independent active, reactive, and apparent no-load detections are included to prevent “meter creep.” Dedicated reverse power (
REVP
), zero-crossing voltage (ZX), and zero-crossing current (ZX_I) pins are also provided. The ADE7953 energy metering IC operates from a 3.3 V supply voltage and is available in a 28-lead LFCSP package.
2
C, and UART.
1.2V REF
LOW
NOISE
PRE-AMP
IAP
IAN
VP
VN
IBP
IBN
AGND
DGND
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
PGA
PGA
PGA
ADC
ADC
ADC
CLKIN
CLKOUT
AIGAIN
HPF
VGAINAPHCAL
HPF
ACTIVE, REACT IVE AND
APPARENT ENERGIES AND
VOLTAGE/CURRENT RMS
CALCULATION F OR PHASE B
(SEE PHASE A FOR DETAILED
DATA PATH).
DIGITAL
INTEGRATOR
CONFIGURATIO N
AND CONTROL
IRQ
AIRMSOS
2
X
LPF
2
X
LPF
VRMSOS
AWG AIN
LPF
AVARGAIN
COMPUTATIONAL
BLOCK FOR TOTAL
REACTIVE PO WER
UART SPI INT ERFACE
CS SCLK
MISO/
SDA/Tx
AWATTOS
AVR MS
MOSI/
SCL/Rx
AIRMS
AVAROS
AVAGAIN
PHASE
A AND B
DATA
2
I
C
ADE7953
CF1DEN
DFC
:
CF2DEN
DFC
:
REVP
ZX
ZX_I
PEAK
ANGLE
POWER FACTOR
SAG
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
CF1
CF2
REVP
ZX
ZX_I
09320-001
ADE7953 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Test Circuit ...................................................................................... 16
Terminology .................................................................................... 17
ADE7953 Power-Up Procedure.................................................... 18
Required Register setting .......................................................... 18
Theory of Operation ...................................................................... 19
Analog Inputs.............................................................................. 19
Analog-to-Digital Conversion.................................................. 19
Current Channel ADCs............................................................ 21
Voltage Channel ADC ............................................................... 21
Reference Circuit........................................................................ 22
Root Mean Square Measurement ................................................. 23
Current Channel RMS Calculation.......................................... 23
Voltage Channel RMS Calculation........................................... 23
Active Power Calculation ..............................................................24
Sign of Active Power Calculation............................................. 24
Active Energy Calculation......................................................... 25
Active Energy Accumulation Modes....................................... 27
Reactive Power Calculation........................................................... 28
Sign of Reactive Power Calculation ......................................... 28
Reactive Energy Calculation ..................................................... 29
Reactive Energy Accumulation Modes ................................... 30
Apparent Power Calculation ......................................................... 31
Apparent Energy Calculation ................................................... 31
Ampere-Hour Accumulation.................................................... 32
Energy-to-Frequency Conversion................................................ 33
Pulse Output Characteristics ....................................................33
Energy Calibration ......................................................................... 34
Gain Calibration......................................................................... 34
Phase Calibration ....................................................................... 34
Offset Calibration....................................................................... 35
Period Measurement...................................................................... 36
Instantaneous Powers and Waveform Sampling........................ 37
Power Factor.................................................................................... 38
Using the Line Cycle Accumulation Mode to Determine the
Power Factor ............................................................................... 38
Power Factor with No-Load Detection ................................... 38
Angle Measurement................................................................... 39
No-Load Detection ........................................................................ 40
Setting the No-Load Thresholds .............................................. 40
Active Energy No-Load Detection........................................... 40
Reactive Energy No-Load Detection ....................................... 41
Apparent Energy No-Load Detection ..................................... 41
Zero-Crossing Detection............................................................... 43
Zero-Crossing Output Pins....................................................... 43
Zero-Crossing Interrupts.......................................................... 43
Zero-Crossing Timeout............................................................. 44
Zero-Crossing Threshold.......................................................... 44
Voltage Sag Detection .................................................................... 45
Setting the SAGCYC Register................................................... 45
Setting the SAGLVL Register.................................................... 45
Voltage Sag Interrupt ................................................................. 45
Peak Detection................................................................................ 46
Indication of Power Direction ...................................................... 47
Reverse Power............................................................................. 47
Sign Indication............................................................................ 47
Overcurrent and Overvoltage Detection..................................... 48
Setting the OVLVL and OILVL Registers ............................... 48
Overvoltage and Overcurrent Interrupts................................ 48
Alternative Output Functions....................................................... 49
ADE7953 Interrupts....................................................................... 50
Primary Interrupts (Voltage Channel and Current Channel
A).................................................................................................. 50
Current Channel B Interrupts .................................................. 50
Communicating with the ADE7953 ............................................ 51
Communication Autodetection ............................................... 51
Locking the Communication Interface................................... 51
SPI Interface................................................................................ 52
I2C Interface ................................................................................ 53
UART Interface........................................................................... 55
Communication Verification and Security ................................. 57
Rev. A | Page 2 of 68
Data Sheet ADE7953
Write Protection ..........................................................................57
Communication Verification.....................................................57
Checksum Register .....................................................................58
ADE7953 Registers .........................................................................60

REVISION HISTORY

11/11—Rev. 0 to Rev. A
Changes to Figure 1...........................................................................1
Changes to Table 1 ............................................................................3
Changes to Absolute Maximum Ratings Section..........................8
Changes to Table 5 ............................................................................9
Replaced Typical Performance Characteristics Section.............11
Changes to Figure 35 ......................................................................16
Added ADE7953 Power-Up Procedure Section..........................18
Changes to Voltage Channel Section............................................19
Changes to Current Channel RMS Calculation Section and
Voltage Channel RMS Calculation Section .................................23
Changes to Active Power Calculation Section ............................24
Changes to Active Energy Integration Time Under Steady
Load Section.....................................................................................25
ADE7953 Register Descriptions ...............................................62
Outline Dimensions........................................................................68
Ordering Guide...........................................................................68
Changes to Reactive Power Calculation Section ........................28
Changes to Reactive Energy Integration Time Under Steady
Load Section ....................................................................................29
Changes to Figure 65 ......................................................................47
Changes to Write Protection Section ...........................................57
Replaced Checksum Register Section and added Figure 75 and
Figure 76...........................................................................................58
Changes to Table 12 ........................................................................59
Changes to Table 14 ........................................................................60
Changes to Table 15 ........................................................................61
Replaced Interrupt Enable Section and Interrupt Status
Registers Section .............................................................................66
2/11—Revision 0: Initial Version
Rev. A | Page 3 of 68
ADE7953 Data Sheet

SPECIFICATIONS

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T set to 0x30, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
PHASE ERROR BETWEEN CHANNELS Line frequency = 45 Hz to 65 Hz, HPF on
Power Factor = 0.8 Capacitive ±0.05 Degrees Phase lead 37° Power Factor = 0.5 Inductive ±0.05 Degrees Phase lag 60°
ACTIVE ENERGY MEASUREMENT
Active Energy Measurement Error
(Current Channel A)
Active Energy Measurement Error
(Current Channel B)
AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Active Energy Measurement Bandwidth 1.23 kHz −3 db
REACTIVE ENERGY MEASUREMENT
Reactive Energy Measurement Error
(Current Channel A)
Reactive Energy Measurement Error
(Current Channel B)
AC Power Supply Rejection VDD = 3.3 V ± 120 mV rms, 100 Hz
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Reactive Energy Measurement
Bandwidth
RMS MEASUREMENT
IRMS and VRMS Measurement
Bandwidth
IRMS (Current Channel A) Measurement
Error
IRMS (Current Channel B) and VRMS
Measurement Error
ANALOG INPUTS
Maximum Signal Levels ±500 mV peak Differential inputs: IAP to IAN, IBP to IBN ±500 mV peak Single-ended input: VP to VN, IBP to IBN ±250 mV peak Single-ended input: IAP to IAN Input Impedance (DC)
IAP Pin 50 MΩ IAN Pin 50 MΩ IBP, IBN, VP, VN Pins 540 kΩ
ADC Offset Error
Current Channel B, Voltage Channel 0 ±10 mV Current Channel A −12 mV PGA = 1
−1 mV PGA = 16, PGA = 22
Gain Error External 1.2 V reference
Current Channel A ±3 % Current Channel B ±3 % Voltage Channel ±3 %
0.1 %
0.1 %
0.1 %
0.1 %
1.23 kHz −3 db
1.23 kHz
0.2 %
0.2 %
MIN
to T
= −40°C to +85°C, Register Address 0x120
MAX
Over a dynamic range of 3000:1, PGA = 1, PGA = 22, integrator off
Over a dynamic range of 1000:1, PGA = 1, PGA = 16, integrator off
Over a dynamic range of 3000:1, PGA = 1, PGA = 22, integrator off
Over a dynamic range of 1000:1, PGA = 1, PGA = 16, integrator off
Over a dynamic range of 1000:1, PGA = 1, PGA = 22, integrator off
Over a dynamic range of 500:1, PGA = 1, PGA = 16, integrator off
Uncalibrated error (see the Terminology section)
Rev. A | Page 4 of 68
Data Sheet ADE7953
Parameter Min Typ Max Unit Test Conditions/Comments
ANALOG PERFORMANCE
Signal-to-Noise Ratio
Current Channel A 74 dB Current Channel B 72 dB Voltage Channel 70
Signal-to-Noise-and-Distortion Ratio
Current Channel A, Current Channel B 68 dB Voltage Channel 65 dB
Bandwidth (−3 dB) 1.23 kHz
CF1 AND CF2 PULSE OUTPUTS
Maximum Output Frequency 206.9 kHz Duty Cycle 50 % CF1 or CF2 frequency > 6.25 Hz Active Low Pulse Width 80 ms CF1 or CF2 frequency < 6.25 Hz Jitter 0.04 % CF1 or CF2 frequency = 1 Hz Output High Voltage, VOH 2.4 V I Output Low Voltage, VOL 0.4 V I
REFERENCE Nominal 1.2 V at REF pin
REF Input Voltage Range 1.19 1.2 1.21 V T Input Capacitance 10 pF Reference Error ±0.9 mV TA = 25°C Output Impedance 1.2 kΩ Temperature Coefficient 10 50 ppm/°C
CLKIN/CLKOUT PINS All specifications CLKIN = 3.58 MHz
Input Clock Frequency 3.58 MHz Crystal Equivalent Series Resistance 30 200 Ω
LOGIC INPUTS—RESET, CLKIN, CS, SCLK,
MOSI/SCL/Rx, MISO/SDA/Tx Input High Voltage, V Input Low Voltage, V
2.4 V VDD = 3.3 V ± 10%
INH
0.8 V VDD = 3.3 V ± 10%
INL
Input Current, IIN V
MOSI/SCL/Rx, MISO/SDA/Tx, RESET
−10 μA
CS, SCLK 1 μA
Input Capacitance, CIN 10 pF
LOGIC OUTPUTS—IRQ, REVP, ZX, ZX_I,
VDD = 3.3 V ± 10% CLKOUT, MOSI/SCL/Rx, MISO/SDA/Tx Output High Voltage, VOH 3.0 V I Output Low Voltage, VOL 0.4 V I
POWER SUPPLY For specified performance
VDD 3.0 V 3.3 V − 10%
3.6 V 3.3 V + 10% IDD 7 9 mA
= 500 μA at 25°C
SOURCE
= 8 mA at 25°C
SINK
to T
Max
= 0 V
= 800 μA
= 2 mA
MIN
IN
SOURCE
SINK
Rev. A | Page 5 of 68
ADE7953 Data Sheet

TIMING CHARACTERISTICS

SPI Interface Timing

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T
Table 2.
Parameter Description Min1 Max1 Unit
tCS CS to SCLK edge 50 ns t
SCLK period 200 ns
SCLK
tSL SCLK low pulse width 80 ns tSH SCLK high pulse width 80 ns t
Data output valid after SCLK edge 80 ns
DAV
t
Data input setup time before SCLK edge 70 ns
DSU
t
Data input hold time after SCLK edge 5 ns
DHD
tDF Data output fall time 20 ns tDR Data output rise time 20 ns tSR SCLK rise time 20 ns tSF SCLK fall time 20 ns t
MISO disabled after CS rising edge 5 40 ns
DIS
t
CS high after SCLK edge 0 ns
SFS
t
SFS_LK
CS high after SCLK edge (when writing to
1200 ns
COMM_LOCK bit)
1
Min and max values are typical minimum and maximum values.

SPI Interface Timing Diagram

MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
CS
SCLK
MISO
MOSI
t
CS
t
DAV
t
SCLK
t
SL
t
SH
MSB OUT LSB OUT
MSB IN
t
DSU
t
DHD
INTERMEDIATE BITS
t
DF
INTERMEDIATE BITS
t
SFS_LK
t
SFS
t
DR
LSB IN
t
SR
t
DIS
09320-003
t
SF
Figure 2. SPI Interface Timing
Rev. A | Page 6 of 68
Data Sheet ADE7953

I2C Interface Timing

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, T
Table 3.
Standard Mode Fast Mode Parameter Description Min1 Max1 Min1 Max1 Unit
f
SCL clock frequency 0 100 0 400 kHz
SCL
t
Hold time for a start or repeated start condition 4.0 0.6 μs
HD;STA
t
Low period of SCL clock 4.7 1.3 μs
LOW
t
High period of SCL clock 4.0 0.6 μs
HIGH
t
Setup time for a repeated start condition 4.7 0.6 μs
SU;STA
t
Data hold time 0 3.45 0 0.9 μs
HD;DAT
t
SU;DAT
Data setup time 250 100 ns tR Rise time of SDA and SCL signals 1000 20 300 ns tF Fall time of SDA and SCL signals 300 20 300 ns t
SU;STO
t
Bus-free time between a stop and start condition 4.7 1.3 μs
BUF
Setup time for stop condition 4.0 0.6 μs
tSP Pulse width of suppressed spikes N/A 50 ns
1
Min and max values are typical minimum and maximum values.

I2C Interface Timing Diagram

MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
SDA
t
STOP
BUF
START
CONDITION
09320-002
SCL
CONDITION
START
t
F
t
t
LOW
HD;STA
t
HD;DAT
t
SU;DAT
t
R
t
HIGH
t
F
t
SU;STA
Figure 3. I
REPEATED START
CONDITIO N
2
C Interface Timing
t
HD;STA
t
SP
t
SU;STO
t
R
CONDITION
Rev. A | Page 7 of 68
ADE7953 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to AGND −0.3 V to +3.7 V VDD to DGND −0.3 V to +3.7 V Analog Input Voltage to AGND,
IAP, IAN, IBP, IBN, VP, VN Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V Operating Temperature
Industrial Range −40°C to +85°C Storage Temperature Range −65°C to +150°C
Note that regarding the temperature profile used in soldering RoHS-compliant parts, Analog Devices, Inc., advises that reflow profiles should conform to J-STD 20 from JEDEC. Refer to the JEDEC website for the latest revision.
−2 V to +2 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 68
Data Sheet ADE7953
A
x
x

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

K
OSI/SCL/R M
CS
27
28
CF1
IRQ
CF2
SCL
MISO/SDA/T
23
22
24
25
26
13
REF
14
PULL_LOW
21 ZX_I
20 REVP 19 CLKOUT
18 CLKIN
17 VDD
16 AGND
15 VINTA
09320-004
1ZX
2RESET
3VINTD
4DGND
5IAP
6IAN
7PULL_HIGH
NOTES
1. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPO SED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB TO CONFER MECHANIC
PADS TO AGND.
L STRENG TH TO THE PACKAGE. DO NOT CONNECT THE
ADE7953
TOP VIEW
(Not to Scale)
8
9
10
H
IBP
IBN
PULL_HIG
11
12
VP
VN
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 ZX
Voltage Channel Zero-Crossing Output Pin. See the Voltage Channel Zero Crossing section. This pin can be configured to output a range of alternative power quality signals (see the Alternative Output Functions section).
2
RESET
3 VINTD
Active Low Reset Input. To initiate a hardware reset, this pin must be brought low for at minimum of 10 μs. This pin provides access to the 2.5 V digital LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor. 4 DGND Ground Reference for the Digital Circuitry. 5, 6 IAP, IAN
Analog Input for Current Channel A (Phase Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The maximum pin voltage for single-ended use is ±250 mV. The PGA associated
with this input has a maximum gain stage of 22 (see the Analog Inputs section). 7, 8 PULL_HIGH These pins should be connected to VDD for proper operation. 9, 10 IBP, IBN
Analog Input for Current Channel B (Neutral Current Channel). This differential voltage input has a maximum
input range of ±500 mV. The PGA associated with this input has a maximum gain of 16 (see the Analog
Inputs section). 11, 12 VN, VP
Analog Input for Voltage Channel. This differential voltage input has a maximum input range of ±500 mV. The
PGA associated with this input has a maximum gain of 16 (see the Analog Inputs section). 13 REF
This pin provides access to the on-chip voltage reference. The internal reference has a nominal voltage
of 1.2 V. This pin should be decoupled with a 4.7 μF capacitor in parallel with a 100 nF ceramic capacitor.
Alternatively, an external reference voltage of 1.2 V can be applied to this pin (see the Reference Circuit
section). 14 PULL_LOW This pin should be connected to AGND for proper operation. 15 VINTA
This pin provides access to the 2.5 V analog LDO. This pin should be decoupled with a 4.7 μF capacitor in
parallel with a 100 nF ceramic capacitor. 16 AGND Ground Reference for the Analog Circuitry. 17 VDD
Power Supply (3.3 V) for the ADE7953. For specified operation, the input to this pin should be within
3.3 V ± 10%. This pin should be decoupled with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.
18 CLKIN
Master Clock Input for the ADE7953. An external clock can be provided at this input. Alternatively, a parallel
resonant AT crystal can be connected across the CLKIN and CLKOUT pins to provide a clock source for the
ADE7953. The clock frequency for specified operation is 3.58 MHz. Ceramic load capacitors of a few tens of
picofarads should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for
the load capacitance requirements. 19 CLKOUT A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7953.
Rev. A | Page 9 of 68
ADE7953 Data Sheet
Pin No. Mnemonic Description
20
21 ZX_I
22 23 CF1 Calibration Frequency Output 1. 24 CF2 Calibration Frequency Output 2. 25 SCLK
26 MISO/SDA/Tx Data Output for SPI Interface/Bidirectional Data Line for I2C Interface/Transmit Line for UART Interface. 27 MOSI/SCL/Rx Data Input for SPI Interface/Serial Clock Input for I2C Interface/Receive Line for UART Interface. 28 CS Chip Select for SPI Interface. This pin must be pulled high if using the I2C or UART interface. EPAD
Reverse Power Output Indicator. See the Reverse Power section. This pin can be configured to output a
REVP
range of alternative power quality signals (see the Alternative Output Functions section). Current Channel Zero-Crossing Output Pin. See the Current Channel Zero Crossing section. This pin can be
configured to output a range of alternative power quality signals (see the Alternative Output Functions section).
IRQ
Interrupt Output. See the ADE7953 Interrupts section.
Serial Clock Input for the Serial Peripheral Interface. All serial communications are synchronized to the clock (see the SPI Interface section). If using the I2C interface, this pin must be pulled high. If using the UART interface, this pin must be pulled to ground.
Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the PCB to confer mechanical strength to the package. Do not connect the pads to AGND.
Rev. A | Page 10 of 68
Data Sheet ADE7953

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
09320-101
Figure 5. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 1) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.5 PF = +0.5 PF = +1.0
0
0.01 0. 1
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-102
Figure 6. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-103
Figure 7. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 22, Power Factor = 1) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.5 PF = +0.5 PF = +1.0
0
0.01 0. 1
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-104
Figure 8. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 22, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1
VDD = 3.30V VDD = 2.97V VDD = 3.63V
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-105
Figure 9. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 22, Temperature = 25°C, Power Factor = 1) over Supply Voltage
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING)
–0.6
–0.8
– 1.0
45 50 55
PF = –0.5 PF = +0.5 PF = +1.0
FREQUENC Y (Hz)
60 65
09320-106
Figure 10. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 22, Temperature = 25°C) over Frequency and Power Factor
with Internal Reference, Integrator Off
Rev. A | Page 11 of 68
ADE7953 Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-107
Figure 11. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 0) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1
PF = –0.866 PF = 0 PF = +0.866
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-110
Figure 14. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 22, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0. 1
PF = –0.866 PF = 0 PF = +0.866
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-108
Figure 12. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% O F READI NG)
–0.6
–0.8
–1.0
0.01 0. 1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
09320-109
Figure 13. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 22, Power Factor = 0) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING)
–0.6
–0.8
– 1.0
45 50 55
PF = –0.866 PF = 0 PF = +0.866
FREQUENC Y (Hz)
60 65
09320-111
Figure 15. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 22, Temperature = 25°C) over Frequency and Power Factor
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.1 1 10 100
GAIN = 1 GAIN = 22
CURRENT CHANNE L (% FULL SCALE)
09320-112
Figure 16. Current Channel A IRMS Error as a Percentage of Reading
(Temperature = 25°C, Power Factor = 1) over Gain with Internal Reference,
Integrator Off
Rev. A | Page 12 of 68
Data Sheet ADE7953
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.1
–40°C +25°C +85°C
1
CURRENT CHANNE L (% FULL SCALE)
10 100
09320-113
Figure 17. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 1) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
– 1.0
45 50 55
PF = –0.5 PF = +0.5 PF = +1.0
FREQUENCY (Hz)
60 65
09320-116
Figure 20. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Frequency and Power Factor
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.5 PF = +0.5 PF = +1.0
0
0.1
1
CURRENT CHANNE L (% FULL SCALE)
10 100
09320-114
Figure 18. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.1
VDD = 3.30V VDD = 2.97V VDD = 3.63V
1
CURRENT CHANNE L (% FULL SCALE)
10 100
09320-115
Figure 19. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C, Power Factor = 1) over Supply Voltage
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
09320-117
Figure 21. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 1, Power Factor = 0) over Temperature with Internal Reference,
Integrator Off
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.866 PF = 0 PF = +0.866
0
0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE)
09320-118
Figure 22. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator Off
Rev. A | Page 13 of 68
ADE7953 Data Sheet
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING)
–0.6
–0.8
– 1.0
45 50 55
PF = –0.866 PF = 0 PF = +0.866
FREQUENC Y (Hz)
60
09320-219
65
Figure 23. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C) over Frequency and Power Factor
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING )
–0.6
–0.8
–1.0
0.01 0. 1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
09320-122
Figure 26. Current Channel A Active Energy Error as a Percentage of Reading
(Gain = 16, Power Factor = 1) over Temperature with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% O F READI NG)
–0.6
–0.8
–1.0
0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE)
Figure 24. Current Channel B IRMS Error as a Percentage of Reading
(Gain = 1, Temperature = 25°C, Power Factor = 1)
with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING)
–0.6
–0.8
0.1 1 10 100
VOLTAG E CHANNEL (% FULL SCALE)
Figure 25. VRMS Error as a Percentage of Reading (Temperature = 25°C,
Power Factor = 1) with Internal Reference, Integrator Off
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READING )
–0.6
–0.8
–1.0
09320-220
Figure 27. Current Channel A Active Energy Error as a Percentage of Reading
PF = –0.5 PF = +0.5 PF = +1.0
0
0.01 0. 1
CURRENT CHANNE L (% FULL SCALE)
1
10 100
09320-123
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING )
–0.6
–0.8
–1.0
0.1
09320-121
–40°C +25°C +85°C
1
CURRENT CHANNE L (% FULL SCALE)
10 100
09320-124
Figure 28. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 16, Power Factor = 1) over Temperature with Internal Reference,
Integrator On
Rev. A | Page 14 of 68
Data Sheet ADE7953
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READING )
–0.6
–0.8
–1.0
PF = –0.5 PF = +0.5 PF = +1.0
0
0.1 1 10 100
CURRENT CHANNEL (% F ULL SCALE)
09320-225
Figure 29. Current Channel B Active Energy Error as a Percentage of Reading
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READING )
–0.6
–0.8
–1.0
0.1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNEL (% F ULL SCALE)
09320-228
Figure 32. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 16, Power Factor = 0) over Temperature with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
0.01 0.1 1 10 100
–40°C +25°C +85°C
CURRENT CHANNE L (% FULL SCALE)
09320-126
Figure 30. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 16, Power Factor = 0) over Temperature with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.866 PF = 0 PF = +0.866
0
0.01 0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE)
09320-227
Figure 31. Current Channel A Reactive Energy Error as a Percentage of Reading
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
–0.2
–0.4
ERROR (% OF READI NG)
–0.6
–0.8
–1.0
PF = –0.866 PF = 0 PF = +0.866
0
0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE)
09320-129
Figure 33. Current Channel B Reactive Energy Error as a Percentage of Reading
(Gain = 16, Temperature = 25°C) over Power Factor with Internal Reference,
Integrator On
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
ERROR (% O F READI NG)
–0.6
–0.8
–1.0
CHANNEL A CHANNEL B
0.1 1 10 100
CURRENT CHANNE L (% FULL SCALE)
09320-130
Figure 34. IRMS Error as a Percentage of Reading (Gain = 16,
Temperature = 25°C) with Internal Reference, Integrator On
Rev. A | Page 15 of 68
ADE7953 Data Sheet
V

TEST CIRCUIT

3.3
+ +
110V
1MΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
1kΩ
33nF
33nF
33nF
33nF
10kΩ
33nF
33nF
3.3V
1µF
4.7µF
3.3V
0.1µF
RESET
2
IAP
5
6
IAN
9
IBP
10
IBN
11
VN
12
VP
7
PULL_HIGH
8
PULL_HIGH
14
PULL_LOW
17
15
VDD
VINTA
MOSI/SCL/Rx
MISO/ SDA/Tx
ADE7953
DGND
416
4.7µF
3
VINTD
CLKOUT
AGND
ZX
REVP
ZX_I
CS
SCLK
CF2
CF1
IRQ
REF
CLKIN
0.1µF
1
20
21
28
27
10kΩ
3.3V
3.3V
500Ω
+
0.1µF
26
25
24
SAME AS
23
CF2
20pF
3.58MHz
20pF
10kΩ
4.7µF
22
13
19
18
09320-099
Figure 35. Test Circuit
Rev. A | Page 16 of 68
Data Sheet ADE7953
r
t

TERMINOLOGY

Measurement Error ADC Offset Error
The error associated with the energy measurement made by the ADE7953 is defined by
Measuremen (1)
Phase Error Between Channels
The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current channels and the voltage channel. The all-digital design ensures that the phase matching between the current channels and the voltage channel is within ±0.05° over a range of 45 Hz to 65 Hz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers.
Power Supply Rejection (PSR)
PSR quantifies the ADE7953 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (120 mV rms/100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition). For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied by ±10%. Any error introduced is again expressed as a percentage of reading.
= Erro
−
EnergyTrue ADE7953 by Registered Energy
EnergyTrue
%100×
The ADC offset error refers to the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection. However, the offset is removed from the current and voltage channels by a high-pass filter (HPF), and the power calculation is not affected by this offset.
Gain Error
The gain error in the ADCs of the ADE7953 is defined as the per-channel difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADCS section and the Voltage Channel ADC section). The difference is expressed as a percentage of the ideal code.
Rev. A | Page 17 of 68
ADE7953 Data Sheet

ADE7953 POWER-UP PROCEDURE

The ADE7953 contains an on-chip power supply monitor that supervises the power supply (VDD). While the voltage applied to the VDD pin is below 2 V ± 10%, the chip is in an inactive state. Once VDD crosses the 2 V ± 10% threshold, the power supply monitor keeps the ADE7953 in an inactive state for an additional 26 ms. This time delay allows VDD to reach the minimum specified operating voltage of 3.3 V – 10%. Once the minimum specified operating voltage is met, the internal circuitry is enabled; this is accomplished in approximately 40 ms.
Once the start-up sequence is complete and the ADE7953 is ready to receive communication from a microcontroller, the reset flag is set in the IRQSTATA register (Address 0x22D and Address 0x32D). An external interrupt is triggered on the IRQ pin. The reset interrupt is enabled by default and cannot be disabled, hence an external interrupt always occurs at the end of a power-up procedure, hardware or software reset.
It is highly recommended that the reset interrupt is used by the microcontroller to gate the first communication with the
ADE7953. If the interrupt is not used, a timeout can be
implemented; however, as the start-up sequence can vary part­to-part and over temperature, a timeout of a least 100 ms is recommended. The reset interrupt provides the most efficient way of monitoring the completion of the ADE7953 start-up sequence.
Once the start-up sequence is complete, communication with the ADE7953 can begin. See the Communicating with the ADE7953 section for further details.

REQUIRED REGISTER SETTING

For optimum performance, Register Address 0x120 must be configured by the user after powering up the ADE7953. This register ensures that the optimum timing configuration is selected to maximize the accuracy and dynamic range. This register is not set by default and thus must be written by the user each time the ADE7953 is powered up. Register 0x120 is a protected register and thus a key must be written to allow the register to be modified. The following sequence should be followed:
• Write 0xAD to Register Address 0xFE: This unlocks
the register 0x120
•
Write 0x30 to Register Address 0x120: This configures the optimum settings
The above two instructions must be performed in succession to be successful.
Rev. A | Page 18 of 68
Data Sheet ADE7953
R

THEORY OF OPERATION

ANALOG INPUTS

The ADE7953 includes three analog inputs that form two current channels and one voltage channel. In a standard configuration, Current Channel A is used to measure the phase current, and Current Channel B is used to measure the neutral current. The voltage channel input measures the difference between the phase voltage and the neutral voltage. The ADE7953 can, however, be used with alternative voltage and current combinations as long as the analog input specifications described in this section are met.

Current Channel A

Current Channel A is a fully differential voltage input that is designed to be used with a current sensor. This input is driven by two pins: IAP (Pin 5) and IAN (Pin 6). The maximum differ­ential voltage that can be applied to IAP and IAN is ±500 mV. A common-mode voltage of less than ±25 mV is recommended. Common-mode voltages in excess of this recommended value may limit the available dynamic range. A programmable gain amplifier (PGA) stage is provided on Current Channel A with gain options of 1, 2, 4, 8, 16, and 22 (see Tab l e 6 ).
The maximum full-scale input of Current Channel A is ±250 mV when using a single-ended configuration and, therefore, when using a gain setting of 1, the dynamic range is limited. The Current Channel A gain is configured by writing to the PGA_IA register (Address 0x008). By default, the Current Channel A PGA is set to 1. A gain option of 22 is offered exclusively on Current Channel A, allowing high accuracy measurement for signals of very small amplitude. This configuration is particularly useful when using small value shunt resistors or Rogowski coils.

Current Channel B

Current Channel B is a fully differential voltage input that is designed to be used with a current sensor. This input is driven by two pins: IBP (Pin 9) and IBN (Pin 10). The maximum differ­ential voltage that can be applied to IBP and IBN is ±500 mV. A common-mode voltage of less than ±25 mV is recommended. Common-mode voltages in excess of this recommended value may limit the available dynamic range. A PGA gain stage is provided on Current Channel B with gain options of 1, 2, 4, 8, and 16 (see Tabl e 6 ). The Current Channel B gain is configured by writing to the PGA_IB register (Address 0x009). By default, the Current Channel B PGA is set to 1.

Voltage Channel

The voltage channel input a full differential input driven by two pins: VP (Pin 12) and VN (Pin 11). The voltage channel is typically connected in a single-ended configuration. The maximum single-ended voltage that can be applied to VP is ±500 mV with respect to VN. A common-mode voltage of less than ±25 mV is recommended. Common-mode voltages in excess of this recommended value may limit the dynamic range capabilities of the ADE7953. A PGA gain stage is provided on
the voltage channel with gain options of 1, 2, 4, 8, and 16 (see Tabl e 6 ).
The voltage channel gain is configured by writing to the PGA_V register (Address 0x007). By default, the voltage channel PGA is set to 1.
Table 6. PGA Gain Settings
Full-Scale
Gain
1
Differential Input (mV)
1 ±500 0001 000 000 2 ±250 001 001 001 4 ±125 010 010 8 ±62.5 011 011 16 ±31.25 100 100 22 ±22.7 101 N/A N/A
When a gain of 1 is selected on Current Channel A, the maximum pin input is
limited to ±250 mV. Therefore, when using a single-ended configuration, the maximum input is ±250 mV with respect to AGND.
PGA_IA[2:0] (Addr 0x008)
PGA_IB[2:0] (Addr 0x009)
PGA_V[2:0] (Addr 0x007)
010 011 100

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7953 is performed by three second-order Σ- modulators. For the sake of clarity, the block diagram in Figure 36 shows the operation of a first­order Σ- modulator. The analog-to-digital conversion consists of a Σ- modulator followed by a low-pass filter stage.
CLKIN/4
ANALOG
LOW-PASS FILTE
R
C
INTEGRATOR
+
–
Figure 36. Σ-Δ Conversion
+V
REF
–V
REF
+
–
.....10100101... ..
1-BIT DAC
LATCHED COMPARATOR
The Σ- modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. The ADE7953 sampling clock is equal to 895 kHz (CLKIN/4). The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and, therefore, the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. A meaningful result is obtained only when a large number of samples is averaged. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low­pass filter can produce 24-bit data-words that are proportional to the input signal level. The
Σ-∆ converter uses two techniques—
oversampling and noise shaping—to achieve high resolution from what is essentially a 1-bit conversion technique.
DIGITAL
LOW-PASS
FILTER
24
09320-013
Rev. A | Page 19 of 68
ADE7953 Data Sheet
A

Oversampling

Oversampling is the first technique used to achieve high resolution. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7953 is 895 kHz, and the bandwidth of interest is 40 Hz to 1.23 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see Figure 37).

ANTIALIASI NG FILTER

SIGNAL
SIGNAL
NOISE
0 3 447. 5
DIGITAL FILTER
FREQUENCY (kHz)
HIGH RESOLUTION OUTPUT FROM DIGITAL LPF
(RC)
SHAPED NOISE
895
SAMPLING FREQUENCY

Noise Shaping

Noise shaping is the second technique used to achieve high resolution. In the
Σ-∆ modulator, the noise is shaped by the
integrator, which has a high-pass-type response for the quanti­zation noise due to feedback. The result is that most of the noise is at the higher frequencies, where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 37.
Antialiasing Filter
As shown in Figure 36, an external low-pass RC filter is required on the input to each modulator. The role of this filter is to prevent aliasing. Aliasing refers to the frequency components in the input signal that are folded back and appear in the sampled signal. This effect occurs with signals that are higher than half the sampling rate of the ADC (also known as the Nyquist frequency) appear­ing in the sampled signal at a frequency below half the sampling rate. This concept is depicted in Figure 38.
LIASING E FFECTS
SAMPLING
FREQUENCY
NOISE
0 3 447. 5
FREQUENCY (kHz)
895
09320-014
Figure 37. Noise Reduction due to Oversampling and
Noise Shaping in the Analog Modulator
However, oversampling alone is not sufficient to improve the signal-to-noise ratio (SNR) in the bandwidth of interest. For example, an oversampling ratio of 4 is required to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies (see the following section.
DSP
IxP
V
IN
IxN
PGA_x BITS
×1, ×2, ×4, ×8, ×16,
×22 (FOR IA ONLY)
PGA
REFERENCE
ADC
xIGAIN
Figure 39. Current Channel ADC and Signal Path
0 1.23 3 447.5
IMAGE
FREQUENCIES
FREQUENCY (kHz)
Figure 38. Aliasing Effect
The arrows shown in Figure 38 depict the frequency compo­nents above the Nyquist frequency (447.5 kHz in the case of the ADE7953) being folded back down. Aliasing occurs with all ADCs, regardless of the architecture.
ZX_I DETECTION
9320-019
HPFEN BIT
CONFIG[2]
HPF
INTENx BIT
CONFI G[1:0]
DIGITAL
INTEGRATOR
LPF1
CURRENT PEAK, OVERCURRENT DETECTIO N
CURRENT RMS (IRMS) CALCULATION
Ix WAVEFORM SAMPLING REGISTER
ACTIVE AND REACTIVE POWER CALCUL ATION
895
09320-015
Rev. A | Page 20 of 68
Data Sheet ADE7953

CURRENT CHANNEL ADCs

Figure 39 shows the ADC signal path and signal processing for Current Channel A, which is accessed through the IAP and IAN pins. The signal path for Current Channel B is identical and is accessed through the IBP and IBN pins. The ADC output is a twos complement, 24-bit data-word that is available at a rate of
6.99 kSPS (thousand samples per second). With the specified full­scale analog input of ±250 mV and a PGA_Ix gain setting of 2, the ADC produces its maximum output code. The ADC output swings between −6,500,000 LSBs (decimal) and +6,500,000 LSBs. This output varies from part to part.
As shown in Figure 39, there is a high-pass filter (HPF) in each current channel signal path. The HPF is enabled by default and removes any dc offset in the ADC output. It is highly recom­mended that this filter be enabled at all times, but it can be disabled by clearing the HPFEN bit (Bit 2) in the CONFIG register (Address 0x102). Clearing the HPFEN bit disables the filters in both current channels and in the voltage channel.

di/dt Current Sensor and Digital Integrator

As shown in Figure 39, the current channel signal path for both Channel A and Channel B includes an internal digital integrator. This integrator is disabled by default and is required only when interfacing with a di/dt sensor, such as a Rogowski coil. When using either a shunt resistor or a current transformer (CT), this integrator is not required and should remain disabled.
A di/dt sensor detects changes in the magnetic field caused by ac current. Figure 40 shows the principle of a di/dt current sensor.
MAGNETIC F IELD CREATED BY CURRENT (DIRECTLY PROPORT IONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
Figure 40. Principle of a di/dt Current Sensor
09320-020
The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. Changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the differential of the current over time (di/dt). The voltage output from the di/dt sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal must be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form.
The ADE7953 has a built-in digital integrator on each current channel that recovers the current signal from the di/dt sensor. Both digital integrators are disabled by default. The digital integrator on Current Channel A is enabled by setting the INTENA bit (Bit 0) in the CONFIG register (Address 0x102). The digital integrator on Current Channel B is enabled by setting the INTENB bit (Bit 1) in the CONFIG register (Address 0x102).

VOLTAGE CHANNEL ADC

Figure 41 shows the ADC signal path and signal processing for the voltage channel input, which is accessed through the VP and VN pins. The ADC output is a twos complement, 24-bit data­word that is available at a rate of 6.99 kSPS (thousand samples per second). With the specified full-scale analog input of ±500 mV and a PGA_V gain setting of 1, the ADC produces its maximum output code. The ADC output swings between −6,500,000 LSBs (decimal) and +6,500,000 LSBs. Note that this output varies from part to part.
As shown in Figure 41, there is a high-pass filter (HPF) in the voltage channel signal path. The HPF is enabled by default and removes any dc offset in the ADC output. It is highly recom­mended that this filter be enabled at all times, but it can be disabled by clearing the HPFEN bit (Bit 2) in the CONFIG register (Address 0x102). Clearing the HPFEN bit disables the filters in both current channels and in the voltage channel.
Rev. A | Page 21 of 68
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