ANALOG DEVICES ADE7878 Service Manual

Polyphase Multifunction Energy Metering IC

with per Phase Active and Reactive Powers

FEATURES

Highly accurate; supports EN 50470-1, EN 50470-3,

IEC 62053-21, IEC 62053-22, and IEC 62053-23 standards

Compatible with 3-phase, 3- or 4-wire (delta or wye), and

other 3-phase services

Supplies total (fundamental and harmonic) active/reactive/

apparent energy and fundamental active/reactive energy on each phase and on the overall system

Less than 0.1% error in active and reactive energy over a

dynamic range of 1000 to 1 at T

Less than 0.2% error in active and reactive energy over a

dynamic range of 3000 to 1 at T Supports current transformer and di/dt current sensors Dedicated ADC channel for neutral current input Less than 0.1% error in voltage and current rms over a

dynamic range of 1000 to 1 at T Supplies sampled waveform data on all three phases and on

neutral current Selectable no load threshold levels for total and

fundamental active and reactive powers, as well as for

apparent powers Low power battery mode monitors phase currents for

antitampering detection Battery supply input for missing neutral operation Phase angle measurements in both current and voltage

channels with a typical 0.3° error Wide-supply voltage operation: 2.4 V to 3.7 V Reference: 1.2 V (drift 10 ppm/°C typical) with external

overdrive capability Single 3.3 V supply 40-lead lead frame chip scale package (LFCSP), Pb-free Operating temperature: −40° to +85°C Flexible I

C, SPI, and HSDC serial interfaces

APPLICATIONS

Energy metering systems

= 25°C

ADE7878

GENERAL DESCRIPTION

The ADE78781 is a high accuracy, 3-phase electrical energy measurement IC with serial interfaces and three flexible pulse outputs. The ADE7878 incorporates second-order sigma-delta (Σ-∆) analog-to-digital converters (ADCs), a digital integrator, reference circuitry, and all the signal processing required to perform total (fundamental and harmonic) active, reactive, and apparent energy measurement and rms calculations, as well as fundamental only active and reactive energy measurement and rms calculations. A fixed function digital signal processor (DSP) executes this signal processing. The DSP program is stored into internal ROM memory.

The ADE7878 is suitable for measuring active, reactive, and apparent energy in various 3-phase configurations, such as wye or delta services, with both three and four wires. The ADE7878 provides system calibration features for each phase, that is, rms offset correction, phase calibration, and gain calibration. The CF1, CF2, and CF3 logic outputs provide a wide choice of power information: total active, reactive, and apparent powers, or the sum of the current rms values, and fundamental active and reactive powers.

The ADE7878 contains waveform sample registers that allow access to all ADC outputs. The device also incorporates power quality measurements, such as short duration low or high voltage detections, short duration high current variations, line voltage period measurement, and angles between phase voltages and currents. Two serial interfaces, SPI and I communicate with the ADE7878. A dedicated high speed interface, the high speed data capture (HSDC) port, can be used in conjunction with I

C to provide access to the ADC outputs and real-time power information. The ADE7878 also has two interrupt request pins,

IRQ0

and

IRQ1 enabled interrupt event has occurred. For the ADE7878, three specially designed low power modes ensure the continuity of energy accumulation when the ADE7878 is in a tampering situation.

The ADE7878 is available in a 40-lead LFCSP, Pb-free package.

C, can be used to

, to indicate that an

U.S. patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infrin gements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADE7878

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings .......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution ................................................................................ 11

Pin Configuration and Function Descriptions ........................... 12

Typical Performance Characteristics ........................................... 14

Test Circuit ...................................................................................... 17

Terminolog y .................................................................................... 18

Power Management ........................................................................ 19

PSM0—Normal Power Mode ................................................... 19

PSM1—Reduced Power Mode.................................................. 19

PSM2—Low Power Mode ......................................................... 19

PSM3—Sleep Mode .................................................................... 20

Power-Up Procedure .................................................................. 20

Hardware Reset ........................................................................... 21

Software Reset Functionality .................................................... 21

Theory of Operation ...................................................................... 24

Analog Inputs .............................................................................. 24

Analog-to-Digital Conversion .................................................. 24

Antialiasing Filter ................................................................... 25

ADC Transfer Function ......................................................... 25

Current Channel ADC ............................................................... 25

Current Waveform Gain Registers ....................................... 26

Current Channel HPF ........................................................... 26

Current Channel Sampling ................................................... 27

di/dt Curent Sensor and Digital Integrator ............................. 27

Voltage Channel ADC ................................................................ 28

Voltage Waveform Gain Registers ........................................ 28

Voltage Channel HPF ............................................................ 28

Voltage Channel Sampling .................................................... 28

Changing Phase Voltage Datapath ........................................... 29

Power Quality Measurements ................................................... 29

Zero Crossing Detection ....................................................... 29

Zero-Crossing Timeout ......................................................... 30

Phase Sequence Detection .................................................... 30

Time Interval Between Phases ............................................. 31

Period Measurement .............................................................. 32

Phase Voltage Sag Detection ................................................. 32

Peak Detection ........................................................................ 33

Overvoltage and Overcurrent Detection ............................ 34

Neutral Current Mismatch ................................................... 35

Phase Compensation ................................................................. 35

Reference Circuit ........................................................................ 37

Digital Signal Processor ............................................................. 37

Root Mean Square Measurement ............................................. 37

Current RMS Calculation ..................................................... 38

Current Mean Absolute Value Calculation ......................... 39

Voltage Channel RMS Calculation ...................................... 40

Voltage RMS Offset Compensation ..................................... 41

Active Power Calculation .......................................................... 41

Total Active Power Calculation ............................................ 41

Fundamental Active Power Calculation .............................. 43

Active Power Gain Calibration ............................................. 43

Active Power Offset Calibration .......................................... 43

Sign of Active Power Calculation ......................................... 43

Active Energy Calculation .................................................... 44

Integration Time Under Steady Load .................................. 45

Energy Accumulation Modes ............................................... 46

Line Cycle Active Energy Accumulation Mode ................. 46

Reactive Power Calculation ...................................................... 47

Reactive Power Gain Calibration ......................................... 48

Reactive Power Offset Calibration ....................................... 48

Sign of Reactive Power Calculation ..................................... 48

Reactive Energy Calculation ................................................. 49

Integration Time Under A Steady Load .............................. 51

Energy Accumulation Modes ............................................... 51

Line Cycle Reactive Energy Accumulation Mode ............. 51

Apparent Power Calculation ..................................................... 52

Apparent Power Gain Calibration ....................................... 53

Apparent Power Offset Calibration ..................................... 53

Rev. 0 | Page 2 of 92

ADE7878

Apparent Power Calculation Using VNOM ........................ 53

Apparent Energy Calculation ................................................ 53

Integration Time Under Steady Load ................................... 54

Energy Accumulation Mode .................................................. 54

Line Cycle Apparent Energy Accumulation Mode ............. 54

Waveform Sampling Mode ........................................................ 55

Energy-to-Frequency Conversion ............................................ 55

Synchronizing Energy Registers with CFx Outputs ........... 57

CF Outputs for Various Accumulation Modes ................... 57

Sign of Sum-of-Phase Powers in the CFx Datapath ........... 59

No Load Condition ..................................................................... 59

No Load Detection Based On Total Active, Reactive Powers

................................................................................................... 59

No Load Detection Based on Fundamental Active and

Reactive Powers ....................................................................... 60



No Load Detection Based on Apparent Power ................... 60

Checksum Register ..................................................................... 60

Interrupts ..................................................................................... 62

Using the Interrupts with an MCU ...................................... 62

Serial Interfaces ........................................................................... 63

Serial Interface Choice ........................................................... 63

I2C-Compatible Interface ....................................................... 63

SPI-Compatible Interface ...................................................... 65

HSDC Interface ....................................................................... 65

ADE7878 Evaluation Board ...................................................... 69

Die Version .................................................................................. 69

Registers List .................................................................................... 70

Outline Dimensions ........................................................................ 90

Ordering Guide ........................................................................... 90

REVISION HISTORY

2/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 92

ADE7878

FUNCTIONAL BLOCK DIAGRAM

PM0

PM1

ADE7878

AVAGAIN

AIRMS

AIRMSOS

AVR MS

LPF

08510-201

CF1

CF1DEN

DFC

AWGAIN

AVR MSO S

AWATTO S

CF2

CF2DEN

DFC

PHASE

C DATA

A, B AND

AVARGAINAVAROS

LPF

CF3DEN

COMPUTATI ONAL

CF3/HSCLK

IRQ0

IRQ1

SCLK/SCL

MOSI/SDA

MISO/HSD

SS/HSA

COMPUTATIONAL

SPI/I

AFVARG AINAFVAROS

BLOCK FOR

ACTIVE AND

FUNDAMENTAL

REACTIVE PO WER

DFC

AFWGAINAFWATTO S

TOTAL

BLOCK FOR

REACTIVE PO WER

HSDC

PROCESSOR

DIGITAL SIGNAL

NIRMS

NIRMSOS

LPF

VDD AGND AVDD DVDD DGND

IN/OUT

REF

RESET

DIGITAL

52426 25174

CLKIN

INTEGRATOR

HPF

[23:0]

HPFDIS

AIGAIN

POR LDO LDO

REF

1.2V

CLKOUT

[23:0]

HPFDIS

ADC

PGA1

IAP

IAN

HPF

ACTIVE/REACT IVE/

AVGAINAPHCAL

ADC

PGA3

VAP

ADC

PGA1

IBP

DATA PATH)

(SEE PHASE A FO R DETAILED

RMS CALCULATI ON FOR PHASE B

APPARENT/TO TAL/F UNDAMENTAL

ENERGIES AND VO LTAGE/ CURRENT

ADC

PGA3

IBN

VBP

ACTIVE/REACT IVE/

RMS CALCULATI ON FOR PHASE C

APPARENT/TO TAL/F UNDAMENTAL

ENERGIES AND VO LTAGE/ CURRENT

ADC

PGA1

ICP

ICN

DIGITAL

INTEGRATOR

[23:0]

HPFDIS

DATA PATH)

(SEE PHASE A FO R DETAILED

ADC

PGA3

VCP

HPF

NIGAIN

ADC

PGA2

INP

INN

Figure 1.

Rev. 0 | Page 4 of 92

ADE7878

SPECIFICATIONS

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T

MIN

to T

= −40°C to +85°C.

MAX

Table 1.

1, 2

Parameter

Min Typ Max Unit Test Conditions/Comments

ACCURACY

Active Energy Measurement

Active Energy Measurement Error

(per Phase) Total Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;

integrator off

0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off

0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on

Fundamental Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;

integrator off

0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off

0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on

Phase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on

PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60°

AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =

± 100 mV rms

Output Frequency Variation 0.01 % DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 % Total Active Energy Measurement

2 kHz

Bandwidth

REACTIVE ENERGY MEASUREMENT

Reactive Energy Measurement Error

(per Phase) Total Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;

integrator off

0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off

0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on

Fundamental Active Power 0.1 % Over a dynamic range of 1000 to 1, PGA = 1, 2, 4;

integrator off

0.2 % Over a dynamic range of 3000 to 1, PGA = 1, 2, 4; integrator off

0.1 % Over a dynamic range of 500 to 1, PGA = 8, 16; integrator on

Phase Error Between Channels Line frequency = 45 Hz to 65 Hz, HPF on

PF = 0.8 Capacitive ±0.05 Degrees Phase lead 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag 60°

AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz, IPx = VPx =

± 100 mV rms

Output Frequency Variation 0.01 %

Rev. 0 | Page 5 of 92

ADE7878

Parameter

1, 2

Min Typ Max Unit Test Conditions/Comments

DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc Output Frequency Variation 0.01 % Total Reactive Energy Measurement

2 kHz

Bandwidth

RMS MEASUREMENTS

I rms and V rms Measurement

2 kHz

Bandwidth

I rms and V rms Measurement Error

0.1 % Over a dynamic range of 1000 to 1, PGA = 1

(PSM0 Mode)

MEAN ABSOLUTE VALUE (MAV)

MEASUREMENT Imav Measurement Bandwidth (PSM1

260 Hz

Mode)

Imav Measurement Error (PSM1 Mode) 0.5 % Over a dynamic range of 100 to 1, PGA = 1

ANALOG INPUTS

Maximum Signal Levels ±500 mV peak Differential inputs between the following

pins: IAP and IAN, IBP and IBN, ICP and ICN; single-ended inputs between the following pins: VAP and VN, VBP and VN, VCP and VN

Input Impedance (DC)

IAP, IAN, IBP, IBN, ICP, ICN, VAP, VBP,

400 kΩ

VCP Pins

VN Pin 130 kΩ

ADC Offset Error ±20 mV PGA = 1, uncalibrated error, see the

Terminology section

Gain Error ±4 % External 1.2 V reference

WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 =

8 kSPS

Current and Voltage Channels See Waveform Sampling Mode section

Signal-to-Noise Ratio, SNR 70 dB PGA = 1 Signal-to-Noise-and-Distortion Ratio,

65 dB PGA = 1

SINAD

Bandwidth (−3 dB) 2 kHz

TIME INTERVAL BETWEEN PHASES

Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on

CF1, CF2, CF3 PULSE OUTPUTS

Maximum Output Frequency 8 kHz WTHR = VARTHR = VATHR = PMAX = 33,516,139 Duty Cycle 50 % If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is even and > 1

(1 + 1/CFDEN)

× 50%

If CF1, CF2, or CF3 frequency > 6.25 Hz and

CFDEN is odd and > 1 Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and

nominal phase currents are larger than 10%

of full scale

REFERENCE INPUT

REF

Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum = 1.2 V + 8%

IN/OUT

Input Capacitance 10 pF

ON-CHIP REFERENCE Nominal 1.2 V at REF

pin at TA = 25°C

IN/OUT

PSM0 and PSM1 Modes

Reference Error ±0.9 mV max Output Impedance 1.4 kΩ min Temperature Coefficient 10 50 ppm/°C

Rev. 0 | Page 6 of 92

ADE7878

Parameter

1, 2

Min Typ Max Unit Test Conditions/Comments

CLKIN All specifications CLKIN of 16.384 MHz

Input Clock Frequency 16.384 MHz Crystal Equivalent Series Resistance 30 50 k CLKIN Input Capacitance 20 pF CLKOUT Output Capacitance 20 pF

LOGIC INPUTS—MOSI/SDA, SCLK/SCL,

CLKIN,

Input High Voltage, V Input Low Voltage, V

, PM0, AND PM1

RESET

2.0 V VDD = 3.3 V ± 10%

INH

0.8 V VDD = 3.3 V ± 10%

INL

Input Current, IIN −7.5 µA Input = 0 V, VDD = 3.3 V

3 A Input = VDD = 3.3 V 100 nA Input = VDD = 3.3 V Input Capacitance, CIN 10 pF

LOGIC OUTPUTS—

IRQ0, IRQ1

, MISO/HSD,

DVDD = 3.3 V ± 10%

AND CLKOUT

Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 10%

800 µA

SOURCE

Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10%

2 mA

SINK

CF1, CF2, CF3/HSCLK

Output High Voltage, V

500 µA

SOURCE

2.4 V VDD = 3.3 V ± 10%

Output Low Voltage, VOL 0.4 V VDD = 3.3 V ± 10%

2 mA

SINK

POWER SUPPLY For specified performance

PSM0 Mode

VDD Pin 3.0 3.6 V Minimum = 3.3 V − 10%; maximum = 3.3 V +

10%

IDD 22 24.29 mA PSM1 and PSM2 Modes

VDD Pin 2.4 3.7 V

IDD

PSM1 Mode 4.85 5.61 mA PSM2 Mode 0.2 0.259 mA

PSM3 Mode For specified performance

VDD Pin 2.4 3.7 V

IDD in PSM3 Mode 1.62 A

See the Typical Performance Characteristics section.

See the Terminology section for a definition of the parameters.

Rev. 0 | Page 7 of 92

ADE7878

TIMING CHARACTERISTICS

VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T

MIN

to T

= −40°C to +85°C.

MAX

Table 2. I

C-Compatible Interface Timing Parameter

Standard Mode Fast Mode Parameter Symbol Min Max Min Max Unit

SCL Clock Frequency f Hold Time (Repeated) Start Condition t Low Period of SCL Clock t High Period of SCL Clock t Set-Up Time for Repeated Start Condition t Data Hold Time t Data Setup Time t

0 100 0 400 kHz

SCL

4.0 0.6 s

HD;STA

4.7 1.3 µs

LOW

4.0 0.6 µs

HIGH

4.7 0.6 µs

SU;STA

0 3.45 0 0.9 µs

HD;DAT

250 100 ns

SU;DAT

Rise Time of Both SDA and SCL Signals tr 1000 20 300 ns Fall Time of Both SDA and SCL Signals tf 300 20 300 ns Setup Time for Stop Condition t Bus Free Time Between a Stop and Start Condition t Pulse Width of Suppressed Spikes tSP N/A

N/A means not applicable.

4.0 0.6 µs

SU;STO

4.7 1.3 µs

BUF

50 ns

SDA

LOW

SU;DAT

HD;STA

BUF

SCL

START

CONDITIO N

HD;STA

HD;DAT

HIGH

Figure 2. I

SU;STA

REPEATED START

CONDITIO N

C-Compatible Interface Timing

SU;STO

STOP

CONDITIO N

START

CONDITION

08510-002

Rev. 0 | Page 8 of 92

ADE7878

Table 3. SPI Interface Timing Parameters

Parameter Symbol Min Max Unit

to SCLK Edge

SCLK Period 400 ns SCLK Low Pulse Width tSL 175 ns SCLK High Pulse Width tSH 175 ns Data Output Valid After SCLK Edge t Data Input Setup Time Before SCLK Edge t Data Input Hold Time After SCLK Edge t Data Output Fall Time tDF 20 ns Data Output Rise Time tDR 20 ns SCLK Rise Time tSR 20 ns SCLK Fall Time tSF 20 ns MISO Disable After SS Rising Edge

High After SCLK Edge

50 ns

100 ns

DAV

100 ns

DSU

5 ns

DHD

200 ns

DIS

0 ns

SFS

SCLK

MISO

MOSI

DAV

DSU

MSB LSB

MSB IN

DHD

INTERMEDIATE BITS

Figure 3. SPI Interface Timing

LSB IN

DIS

08510-003

Rev. 0 | Page 9 of 92

ADE7878

Table 4. HSDC Interface Timing Parameter

Parameter Symbol Min Max Unit

HSA to SCLK Edge t HSCLK Period 125 ns HSCLK Low Pulse Width tSL 50 ns HSCLK High Pulse Width tSH 50 ns Data Output Valid After HSCLK Edge t Data Output Fall Time tDF 20 ns Data Output Rise Time tDR 20 ns HSCLK Rise Time tSR 10 ns HSCLK Fall Time tSF 10 ns HSD Disable After HSA Rising Edge t HSA High After HSCLK Edge t

HSA

HSCL

DAV

0 ns

40 ns

DAV

5 ns

DIS

0 ns

SFS

DIS

HSD

MSB LSBINTERMEDIATE BITS

08510-004

Figure 4. HSDC Interface Timing

TO OUTPUT

50pF

2mA I

800µA I

1.6V

08510-005

Figure 5. Load Circuit for Timing Specifications

Rev. 0 | Page 10 of 92

ADE7878

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5. Absolute Maximum Ratings

Parameter Rating

VDD to AGND −0.3 V to +3.7 V VDD to DGND −0.3 V to +3.7 V Analog Input Voltage to AGND, IAP, IAN,

I BP, I B N, IC P, I CN , VA P, V B P, V CP, VN

Analog Input Voltage to INP and INN −2 V to +2 V Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V Operating Temperature

Industrial Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C

Lead Temperature Range

(Soldering, 10 sec)

−2 V to +2 V

300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified equal to 29.3°C/W; θJC is specified equal to

1.8°C/W.

Table 6. Thermal Resistance

Package Type θJA θ

40-Lead LFCSP 29.3 1.8 °C/W

Unit

ESD CAUTION

Rev. 0 | Page 11 of 92

ADE7878

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

/HSD

I/SDA

CF1

CF2

CF3/HSCLK

SCLK/SCL

MISO

MOS

SS/HSA

PIN 1

1NC

INDICATOR

2PM0 3PM1 4

RESET

5DVDD 6DG ND 7IAP 8IAN 9IBP

10NC

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND.

ADE7878

TOP VIEW

(Not to Scale)

ICP

IBN

ICN

Figure 6. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1, 10, 11, 20,

NC No Connect. These pins are not connected internally.

21, 30, 31, 40 2 PM0 Power Mode Pin 0. This pin, combined with PM1, defines the power mode of the ADE7878, as

described in Table 8.

3 PM1 Power Mode Pin 1. This pin defines the power mode of the ADE7878 when combined with PM0, as

described in Table 8.

RESET

Reset Input, Active Low. In PSM0 mode, this pin should stay low for at least 10 µs to trigger a hardware reset.

5 DVDD This pin provides access to the on-chip 2.5 V digital LDO. Do not connect any external active

circuitry to this pin. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 220 nF

capacitor. 6 DGND Ground Reference. This pin provides the ground reference for the digital circuitry. 7, 8 IAP, IAN Analog Inputs for Current Channel A. This channel is used with the current transducers and is

referenced in this document as Current Channel A. These inputs are fully differential voltage inputs with a maximum differential level of ±0.5 V. This channel also has an internal PGA, equal to the ones on Channel B and Channel C.

9, 12 IBP, IBN Analog Inputs for Current Channel B. This channel is used with the current transducers and is

referenced in this document as Current Channel B. These inputs are fully differential voltage inputs

with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones

on Channel C and Channel A. 13, 14 ICP, ICN Analog Inputs for Current Channel C. This channel is used with the current transducers and is

referenced in this document as Current Channel C. These inputs are fully differential voltage inputs

with a maximum differential level of ±0.5 V. This channel also has an internal PGA equal to the ones

on Channel A and Channel B. 15, 16 INP, INN Analog Inputs for Neutral Current Channel N. This channel is used with the current transducers and

is referenced in this document as Current Channel N. These inputs are fully differential voltage

inputs with a maximum differential level of ±0.5 V. This channel also has an internal PGA, different

from the ones found on the A, B, and C channels. 17 REF

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal

IN/OUT

value of 1.2 V. An external reference source with 1.2 V ± 8% can also be connected at this pin. In

either case, decouple this pin to AGND with a 4.7 µF capacitor in parallel with a ceramic 100 nF

capacitor. After reset, the on-chip reference is enabled.

IRQ1

30 NC 29

IRQ0 28 CL KOUT 27 CL KIN 26 VDD 25 AG ND 24 AVDD 23 VAP 22 VBP 21 NC

INP

INN

VCP

IN/OUT

REF

08510-106

Rev. 0 | Page 12 of 92

ADE7878

Pin No. Mnemonic Description

18, 19, 22, 23 VN, VCP, VBP, VAP Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is

referenced as the voltage channel in this document. These inputs are single-ended voltage inputs with a maximum signal level of ±0.5 V with respect to VN for specified operation. This channel also has an internal PGA.

24 AVDD This pin provides access to the on-chip 2.5 V analog low dropout regulator (LDO). Do not connect

external active circuitry to this pin. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 220 nF capacitor.

25 AGND Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the

analog ground plane or to the quietest ground reference in the system. Use this quiet ground reference for all analog circuitry, for example, antialiasing filters, current, and voltage transducers.

26 VDD Suppy Voltage. This pin provides the supply voltage. In PSM0 (normal power mode), maintain the

supply voltage at 3.3 V ± 10% for specified operation. In PSM1 (reduced power mode), PSM2 (low power mode), and PSM3 (sleep mode), when the ADE7878 is supplied from a battery, maintain the supply voltage between 2.4 V and 3.7 V. Decouple this pin to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

27 CLKIN Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant

AT-cut crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7878. The clock frequency for specified operation is 16.384 MHz. Use ceramic load capacitors of a few tens of picofarad with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements.

28 CLKOUT A crystal can be connected across this pin and CLKIN (as previously described with Pin 27 in this

table) to provide a clock source for the ADE7878. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.

29, 32

33, 34, 35 CF1, CF2,

36 SCLK/SCL Serial Clock Input for SPI Port/Serial Clock Input for I2C Port. All serial data transfers are synchronized

37 MISO/HSD Data Out for SPI Port/Data Out for HSDC Port. 38 MOSI/SDA Data In for SPI Port/Data Out for I2C Port. 39

EP Exposed Pad Connect the exposed pad to AGND.

IRQ1

IRQ0

CF3/HSCLK

/HSA

Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a detailed presentation of the events that may trigger interrupts.

Calibration Frequency (CF) Logic Outputs. These outputs provide power information based on the CF1SEL, CF2SEL, and CF3SEL bits in the CFMODE register. These outputs are used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the CF1DEN, CF2DEN, and CF3DEN registers, respectively (see the Energy-to-Frequency Conversion section). CF3 is multiplexed with the serial clock output of the HSDC port.

to this clock (see the Serial Interfaces section). This pin has a Schmidt trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator outputs.

Slave Select for SPI Port/HSDC Port Active.

Rev. 0 | Page 13 of 92

ADE7878

TYPICAL PERFORMANCE CHARACTERISTICS

0.10

0.05

–0.05

–0.10

–0.15

–0.20

ERROR (%)

–0.25

–0.30

–0.35

–0.40

0.01 0.1 1 10

FULL-SCAL E CURRENT (%)

Figure 7. Total Active Energy Error As Percentage of Reading (Gain = +1,

pF = 1) over Temperature with Internal Reference and Integrator Off

0.15

0.10

0.05

–0.05

ERROR (%)

–0.10

–0.15

–0.20

–0.25

45 47 49 51 53 55 57 59 61 63 65

LINE FREQUENCY (Hz)

Figure 8. Total Active Energy Error As Percentage of Reading (Gain = +1,

pF = 1) over Frequency with Internal Reference and Integrator Off

0.15

VDD = 2.97V V

0.10

0.05

ERROR (%)

–0.05

= 3.30V

VDD = 3.63V

–40°C, pf = 1.0 +25°C, pf = 1.0 +85°C, pf = 1.0

pf = 1 pf = +0.5 pf = –0.5

100

08510-301

08510-305

0.80

0.60

0.40

0.20

ERROR (%)

–0.20

–0.40

–0.60

0.1 1 10 100

FULL-SCAL E CURRENT (%)

–40°C, pf = 1.0 +25°C, pf = 1.0 +85°C, pf = 1.0

08510-308

Figure 10. Total Active Energy Error As Percentage of Reading (Gain = +16)

over Temperature with Internal Reference and Integrator On

0.40

0.30

0.20

0.10

–0.10

ERROR (%)

–0.20

–0.30

–0.40

–0.50

0.01 0.1 1 10 100

–40°C, pf = 0 +25°C, pf = 0 +85°C, pf = 0

FULL-SCAL E CURRENT (%)

08510-311

Figure 11. Total Reactive Energy Error As Percentage of Reading (Gain = +1,

pF = 0) over Temperature with Internal Reference and Integrator Off

0.10

pf = 0 pf = +0.5 pf = –0.5

ERROR (%)

0.05

–0.05

–0.10

–0.15

–0.10

–0.15

0.01 0.1 1 10 100

FULL-SCAL E CURRENT (%)

Figure 9. Total Active Energy Error As Percentage of Reading (Gain = +1,

pF = 1) over Power Supply with Internal Reference and Integrator Off

Rev. 0 | Page 14 of 92

–0.20

–0.25

45 47 49 51 53 55 57 59 61 63 65

08510-306

LINE FREQ UENCY (Hz)

08510-315

Figure 12. Total Reactive Energy Error As Percentage of Reading (Gain = +1)

over Frequency with Internal Reference and Integrator Off

ADE7878

0.30

0.20

0.10

VDD = 2.97V VDD = 3.30V

VDD = 3.63V

0.15

0.10

0.05

ERROR (%)

–0.10

–0.20

–0.30

0.01 0. 1 1 10 100

FULL-SCAL E CURRENT (%)

08510-316

Figure 13. Total Reactive Energy Error As Percentage of Reading (Gain = +1)

over Power Supply with Internal Reference and Integrator Off

0.60

0.50

0.40

–40°C, pf = 1.0 +25°C, pf = 1.0 +85°C, pf = 1.0

0.1 1 10 100

FULL-SCAL E CURRENT (%)

08510-318

ERROR (%)

0.30

0.20

0.10

–0.10

–0.20

–0.30

–0.40

Figure 14. Total Reactive Energy Error As Percentage of Reading (Gain = +16)

over Temperature with Internal Reference and Integrator On

0.20

0.15

0.10

0.05

–0.05

ERROR (%)

–0.10

–0.15

–0.20

–0.25

45 47 49 51 53 55 57 59 61 63 65

pf = 1.0 pf = +0.5 pf = –0.5

LINE FREQUENCY (Hz)

08510-335

Figure 15. Fundamental Active Energy Error As Percentage of Reading (Gain = +1) over Frequency with Internal Reference and Integrator Off

ERROR (%)

–0.05

–0.10

–0.15

0.01 0. 10 1.00 10.00 100. 00

FULL-SCAL E CURRENT (%)

08510-337

Figure 16. CF Fundamental Active Energy Error As a Percentage of Reading

(Gain = +1) with Internal Reference and Integrator Off

0.70

0.60

0.50

0.40

0.30

0.20

0.10

ERROR (%)

–0.10

–0.20

–0.30

0.10 1. 00 10.00 100.00

+25°C, pf = 1.0 –40°C, pf = 1.0 +85°C, pf = 1.0

FULL-SCAL E CURRENT (%)

Figure 17. Fundamental Active Energy Error As Percentage of Reading

(Gain = +16) over Temperature with Internal Reference and Integrator On

0.15

0.10

0.05

–0.05

ERROR (%)

–0.10

–0.15

–0.20

–0.25

45 47 49 51 53 55 57 59 61 63 65

LINE FREQUENCY (Hz)

pf = 1.0 pf = +0.5 pf = –0.5

08510-345

Figure 18. Fundamental Reactive Energy Error As Percentage of Reading

(Gain = +1) over Frequency with Internal Reference and Integrator Off

08510-338

Rev. 0 | Page 15 of 92

ADE7878

0.15

0.10

0.05

ERROR (%)

–0.05

–0.10

ERROR (%)

0.50

0.40

0.30

0.20

0.10

–0.10

–0.20

–0.30

+25°C, pf = 1.0 –40°C, pf = 1.0 +85°C, pf = 1.0

–0.15

0.01 0.10 1.00 10.00 100. 00

FULL-SCAL E CURRENT (%)

08510-347

Figure 19. CF Fundamental Reactive Energy Error As a Percentage of Reading

(Gain = +1) with Internal Reference and Integrator Off

–0.40

0.10 1.00 10.00 100.00

FULL-SCAL E CURRENT (%)

Figure 20. Fundamental Reactive Energy Error As Percentage of Reading

(Gain = +16) over Temperature with Internal Reference and Integrator On

08510-348

Rev. 0 | Page 16 of 92

ADE7878

TEST CIRCUIT

1kΩ

10kΩ

1.8nF

3.3V

SAME AS

IAP, IAN

SAME AS

IAP, IAN

SAME AS

VCP

SAME AS

VCP

+ +

0.22µF

PM0

PM1

RESET

IAP

IAN

IBP

IBN

ICP

ICN

VCP

VBP

VAP

4.7µF

1µF

Figure 21. Test Circuit

3.3

VDD

AVD D

ADE7858

AGND

DGND

10µF

DVDD

SS/HSA

MOSI/SDA

MISO/HSD

SCLK/SCL

CF3/HSCLK

CF2

CF1

IRQ1

IRQ0

REF

IN/OUT

CLKOUT

CLKIN

PAD

0.1µF

SAME AS

CF2

SAME AS

IRQ0_N

20pF

16.384MHz

20pF

10kΩ

4.7µF

10kΩ

3.3V

1.5kΩ

0.1µF

08510-099

Rev. 0 | Page 17 of 92

ADE7878

−

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the ADE7878 is defined by

Measurement Error =

Registere

Energ

EnergyTrue

Phase Error Between Channels

The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel. The all digital design ensures that the phase matching between the current channels and voltage channels in all three phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range of 40 Hz to 1 kHz. This internal phase mismatch can be combined with the external phase error (from current sensor or component tolerance) and calibrated with the phase calibration registers.

Power Supply Rejection (PSR)

This quantifies the ADE7878 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac signal (120 mV rms at 100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the power supplies are varied ±10%. Any error introduced is expressed as a percentage of the reading.

7878×−

TrueADEb

Energ

%100

(1)

ADC Offset Error

This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typical Perfor m a n c e Characte r istics section). However, a HPF removes the offset from the current and voltage channels and the power calculation remains unaffected by this offset.

Gain Error

The gain error in the ADCs of the ADE7878 is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Volt age C han nel AD C section). The difference is expressed as a percentage of the ideal code.

CF Jitter

The period of pulses at one of the CF1, CF2, or CF3 pins is continuously measured. The maximum, minimum, and average values of four consecutive pulses are computed as follows:

Maximum = max(Period

Minimum = min(Period

Average =

, Period1, Period2, Period3)

PeriodPeriodPeriodPeriod ++

3210

The CF jitter is then computed as

JITTER

aximum

Average

inimum

%100×

(2)

Rev. 0 | Page 18 of 92

ADE7878

POWER MANAGEMENT

The ADE7878 has four modes of operation, determined by the state of the PM0 and PM1 pins (see Table 8). These pins provide complete control of the ADE7878 operation and can easily be connected to an external microprocessor I/O. The PM0 and PM1 pins have internal pull-up resistors. Tab le 1 0 and Tab l e 11 list actions that are recommended before and after setting a new power mode.

Table 8. ADE7878 Power Supply Modes

Power Supply Modes PM1 PM0

PSM0, Normal Power Mode 0 1 PSM1, Reduced Power Mode 0 0 PSM2, Low Power Mode 1 0 PSM3, Sleep Mode 1 1

PSM0—NORMAL POWER MODE

In PSM0 mode, the ADE7878 is fully functional. The PM0 pin is set to high and the PM1 pin is set to low for the ADE7878 to enter this mode. If the ADE7878 is in one of PSM1, PSM2, or PSM3 modes and is switched into PSM0 mode, then all control registers take the default values with the exception of the threshold register, LPOILVL[7:0], which is used in PSM2 mode, and the CONFIG2[7:0] register, both of which maintain their values.

The ADE7878 signals the end of the transition period by triggering

IRQ1

the the STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition is finished. The status bit is cleared and the STATUS1[31:0] register with the corresponding bit set to 1. Bit 15 (RSTDONE) in the interrupt mask register does not have any functionality attached even if the Bit 15 (RSTDONE) in the STATUS1[31:0] register is set to 1. This makes the RSTDONE interrupt unmaskable.

interrupt pin low and setting Bit 15 (RSTDONE) in

IRQ1

pin is set back to high by writing

IRQ1

pin goes low when

PSM1—REDUCED POWER MODE

In this mode, the ADE7878 measures the mean absolute values (mav) of the 3-phase currents and stores the results in the AIMAV[19:0], BIMAV[19:0], and CIMAV[19:0] 20-bit registers. This mode is useful in missing neutral cases in which the voltage supply of the ADE7878 is provided by an external battery. The serial ports, I and the active port can be used to read the AIMAV, BIMAV, and CIMAV registers. It is not recommended to read any of the other registers because their values are not guaranteed in this mode.

Similarly, a write operation is not taken into account by the ADE7878 in this mode. In summary, in this mode, it is not recommended to access any register other than AIMAV, BIMAV, and CIMAV. The circuit that measures these estimates of rms values is also active during PSM0; therefore, its calibration can be completed in either PSM0 mode or in PSM1 mode. Note

C or SPI, are enabled in this mode

Rev. 0 | Page 19 of 92

that the ADE7878 does not provide any register to store or process the corrections resulting from the calibration process. The external microprocessor should store the gain values in connection with these measurements and use them during PSM1 (see the Current Mean Absolute Value Calculation section for more details on the xIMAV registers).

The 20-bit mean absolute value measurements done in PSM1, although available also in PSM0, are different from the rms measurements of phase currents and voltages executed only in PSM0 and stored in xIRMS and xVRMS 24-bit registers. See the Current Mean Absolute Value Calculation section for details.

If the ADE7878 is set in PSM1 mode while still in PSM0, the ADE7878 immediately begins the mean absolute value calculations without any delay. The xIMAV registers can be accessed at any time; however, if the ADE7878 is set in PSM1 mode while still in PSM2 or PSM3 modes, the ADE7878 signals the start of

IRQ1

the mean absolute value computations by triggering the pin low. The xIMAV registers can be accessed only after this moment.

PSM2—LOW POWER MODE

In this mode, the ADE7878 compares all phase currents against a threshold for a period of 0.02 × (LPLINE + 1) seconds, independent of the line frequency. LPLINE are Bits[7:3] of the LPOILVL[7:0] register (see Tab l e 9).

Table 9. LPOILVL Register

Bit Mnemonic Default Description

[2:0] LPOIL 111 Threshold is put at a value

corresponding to full scale multiplied by LPOIL/8.

[7:3] LPLINE 00000 The measurement period is

(LPLINE + 1)/50 sec.

The threshold is derived from Bits[2:0] (LPOIL) of the LPOILVL[7:0] register as LPOIL/8 of full scale. Every time one phase current becomes greater than the threshold, a counter is incremented. If every phase counter remains below LPLINE + 1 at the end of the measurement period, then the IRQ0

pin is triggered low. If a single phase counter becomes greater or equal to LPLINE + 1 at the end of the measurement period, the the ADE7878 behaves in PSM2 mode when LPLINE = 2 and LPOIL = 3. The test period is three 50 Hz cycles (60 ms), and the Phase A current rises above the LPOIL threshold three times. At the end of the test period, the

The I PSM2 mode reduces the power consumption required to monitor the currents when there is no voltage input and the voltage supply of the ADE7878 is provided by an external battery. If the

IRQ1

pin is triggered low. illustrates how

C or SPI port is not functional during this mode. The

Figure 22

IRQ1

pin is triggered low.

ADE7878

0IRQ pin is triggered low at the end of a measurement period, this signifies all phase currents stayed below threshold and, therefore, there is no current flowing through the system. At this point, the external microprocessor should set the ADE7878

in Sleep Mode PSM3. If the end of the measurement period, this signifies that at least one current input is above the defined threshold and current is flowing through the system, although no voltage is present at the ADE7878 pins. This situation is often called missing neutral and is considered a tampering situation, at which point the external microprocessor should set the ADE7878 in PSM1 mode, measure mean absolute values of phase currents, and integrate the energy based on their values and the nominal voltage.

It is recommended to use the ADE7878 in PSM2 mode when Bits[2:0] (PGA1) of the Gain[15:0] register are equal to 1 or 2. These bits represent the gain in the current channel datapath. It is not recommended to use the ADE7878 in PSM2 mode when the PGA1 bits are equal to 4, 8, or 16.

IA CURREN

PHASE COUNTER = 1

IRQ 1

Figure 22. PSM2 Mode Triggering

1IRQ pin is triggered low at the

LPLINE = 2

PHASE COUNTER = 2

IRQ1

PHASE COUNTER = 3

Pin for LPLINE = 2, 50 Hz Systems

LPOIL

THRESHOLD

PSM3—SLEEP MODE

In this mode, the ADE7878 has most of the internal circuits turned off and the current consumption is at its lowest level.

C, HSDC, and SPI ports are not functional during this

The I mode, and the

RESET

, SCLK/SCL, MOSI/SDA, and SS/HSA

pins should be set high.

POWER-UP PROCEDURE

The ADE7878 contains an on-chip power supply monitor that supervises the power supply (VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is in an inactive state. As VDD crosses this threshold, the power supply monitor keeps the chip in this inactive state for an additional 26 ms, allowing VDD to achieve 3.3 V − 10%, the minimum recommended supply voltage. Because the PM0 and PM1 pins have internal pull-up resistors and the external microprocessor keeps them high, the ADE7878 always powers-up in sleep mode (PSM3). Then, an external circuit (that is, a microprocessor) sets the PM1 pin to a low level, allowing the ADE7878 to enter normal mode (PSM0). The passage from PSM3 mode, in which most of the internal circuitry is turned off, to PSM0 mode, in which all functionality is enabled, is accomplished in less than 40 ms (see Figure 23 for details).

When the ADE7878 enters PSM0 mode, the I active serial port. If the SPI port is used, then the must be toggled three times high to low. This action selects the SPI port for further use. If I

C is the active serial port, Bit 1 (I2C_LOCK) of CONFIG2[7:0] must be set to 1 to lock it in. From this moment, the ADE7878 ignores spurious toggling of

the

/HSA pin, and an eventual switch to use the SPI port is no longer possible. Likewise, if SPI is the active serial port, any write to the CONFIG2[7:0] register locks the port, at which time a

08510-008

switch to use the I

C port is no longer possible.

C port is the

/HSA pin

3.3V – 10%

2.0V ± 10%

40ms26ms

ADE7878

POWERED UP

POR TIMER

TURNED ON

ADE7878

ENTER PSM3

Figure 23. Power-Up Procedure

Rev. 0 | Page 20 of 92

MICROPROCESSOR

SETS ADE7878

IN PSM0

RSTDONE

INTERRUPT

TRIGGERED

ADE7878

PSM0 READY

MICROPROCESSOR MAKES THE CHOICE BETWE EN

C AND SPI

08510-009

ADE7878

Only a power-down or setting the ADE7878 to use the I

C port. Once locked, the serial port choice is

RESET

pin low can reset the

maintained when the ADE7878 changes PSMx power modes.

Immediately after entering PSM0, theADE7878 sets all registers to their default values, including CONFIG2[7:0] and LPOILVL[7:0].

The ADE7878 signals the end of the transition period by triggering the

IRQ1

interrupt pin low and setting Bit 15 (RSTDONE) in the STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and the

IRQ1

pin is returned high by writing the STATUS1[31:0] register with the corresponding bit set to 1. Because the RSTDONE is an unmaskable interrupt, Bit 15 (RSTDONE) in the STATUS1[31:0] register must be cancelled for the to wait until the

IRQ1

pin to return high. It is recommended

IRQ1

pin goes low before accessing the STATUS1[31:0] register to test the state of the RSTDONE bit. At this point, as a good programming practice, it is also recommended to cancel all other status flags in the STATUS1[31:0] and STATUS0[31:0] registers by writing the corresponding bits with 1.

Initially, the DSP is in idle mode, which means it does not execute any instruction. This is the moment to initialize all ADE7878 registers and then write 0x0001 into the Run[15:0] register to start the DSP (see the Digital Signal Processor section for details on the Run[15:0] register).

If the supply voltage, VDD, drops lower than 2 V ± 10%, the ADE7878 enters an inactive state, which means that no measurements and computations are executed.

HARDWARE RESET

The ADE7878 has a mode and the the hardware reset state. The ADE7878 must be in PSM0 mode for a hardware reset to be considered. Setting the low while the ADE7878 is in PSM1, PSM2, and PSM3 modes

does not have any effect.

If the ADE7878 is in PSM0 mode and the from high to low and then back to high after at least 10 µs, all the registers are set to their default values, including CONFIG2[7:0] and LPOILVL[7:0]. The ADE7878 signals the end of the transi-

RESET

pin. If the ADE7878 is in PSM0

RESET

pin is set low, then the ADE7878 enters

RESET

pin is toggled

tion period by triggering the Bit 15 (RSTDONE) in the STATUS1[31:0] register to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and the returned high by writing to the STATUS1[31:0] register with the corresponding bit set to 1.

After a hardware reset, the DSP is in idle mode, which means it does not execute any instruction.

Because the I

C port is the default serial port of theADE7878, it becomes active after a reset state. If SPI is the port used by the external microprocessor, the procedure to enable it must be repeated immediately after the high (see the section for details). Serial Interfaces

At this point, it is recommended to initialize all of the ADE7878 registers and then write 0x0001 into the Run[15:0] register to start the DSP. See the Digital Signal Processor section for details on the Run[15:0] register.

SOFTWARE RESET FUNCTIONALITY

Bit 7 (SWRST) in the CONFIG[15:0] register manages the software reset functionality in PSM0 mode. The default value of this bit is 0. If this bit is set to 1, then the ADE7878 enters a software reset state. In this state, almost all internal registers are set to their default values. In addition, the choice of what serial port,

C or SPI, is in use remains unchanged if the lock-in procedure

I has been previously executed (see the Serial Interfaces for details). The registers that maintain their values despite the SWRST bit being set to 1 are CONFIG2[7:0] and LPOILVL[7:0]. When the software reset ends, Bit 7 (SWRST) in CONFIG[15:0] is cleared

IRQ1

to 0, the in the STATUS1[31:0] register is set to 1. This bit is 0 during the transition period and becomes 1 when the transition ends. The status bit is cleared and the the STATUS1[31:0] register with the corresponding bit set to 1.

After a software reset ends, the DSP is in idle mode, which means it does not execute any instruction. It is recommended to initialize all the ADE7878 registers and then write 0x0001 into the Run[15:0] register to start the DSP (see the Digital Signal Processor section for details on the Run[15:0] register).

Software reset functionality is not available in PSM1, PSM2, or PSM3 mode.

interrupt pin is set low, and Bit 15 (RSTDONE)

IRQ1

interrupt pin low and setting

IRQ1

pin is

RESET

pin is toggled back to

IRQ1

pin is set back high by writing to

Rev. 0 | Page 21 of 92

ADE7878

Table 10. Power Modes and Related Characteristics

LPOILVL,

Power Mode All Registers1

PSM0

State After Hardware Reset Set to default Set to default I2C enabled All circuits are active and

State After Software Reset Set to default Unchanged Active serial port is unchanged if lock

PSM1 Not available Values set

PSM2 Not available Values set

PSM3 Not available Values set

Setting for all registers except the LPOILVL and CONFIG2 registers.

CONFIG2 I2C/SPI Functionality

DSP is in idle mode. All circuits are active and

in procedure has been previously

DSP is in idle mode.

executed

Enabled Current mean absolute during PSM0 unchanged.

values are computed and the results are stored in the AIMAV, BIMAV, and CIMAV registers. The I SPI serial port is enabled with limited functionality.

Disabled Compares phase currents during PSM0 unchanged

against the threshold set in LPOILVL. Triggers

pins accordingly.

IRQ1 The serial ports are not available.

Disabled Internal circuits shut down during PSM0 unchanged

and the serial ports are not available.

C or

IRQ0

Rev. 0 | Page 22 of 92

ADE7878

Table 11. Recommended Actions When Changing Power Modes

Initial Power Mode

PSM0

PSM1

PSM2

PSM3

Recommended Actions Before Setting Next Power Mode

Stop DSP by setting Run[15:0] = 0x0000.

Disable HSDC by clearing Bit 6 (HSDEN) to 0 in the CONFIG[15:0] register.

Mask interrupts by setting MASK0[31:0] = 0x0 and MASK1[31:0] = 0x0.

Erase interrupt status flags in the STATUS0[31:0] and STATUS1[31:0] registers.

No action necessary.

Next Power Mode

PSM0 PSM1 PSM2 PSM3

Current mean absolute

values (mav) computed immediately.

Wait until the

pin is triggered

IRQ1 accordingly.

IRQ0

No action necessary.

xIMAV[19:0] registers may be accessed immediately.

Wait until the

IRQ1

pin is triggered low. Poll the STATUS1[31:0]

Wait until the

pin is triggered

IRQ1

IRQ0

accordingly.

No action necessary.

Wait until the

IRQ1

pin is triggered low. Poll the STATUS1[31:0]

Wait until the

IRQ1

pin triggered low. Current mean absolute

values are computed beginning this moment.

No action

necessary.

xIMAV[19:0] registers may

be accessed from this moment.

Wait until the

IRQ1

pin is triggered low. Poll the STATUS1[31:0]

Wait until the

IRQ1

pin is

triggered low. Current mav circuit begins

computations at this time.

Wait until the

pin is triggered

IRQ1 accordingly.

IRQ0

(RSTDONE) is set to 1. xIMAV[19:0] registers can

be accessed from this moment.

Rev. 0 | Page 23 of 92

ADE7878

–

THEORY OF OPERATION

ANALOG INPUTS

The ADE7878 has seven analog inputs forming current and voltage channels. The current channels consist of four pairs of fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP and ICN, and INP and INN. These voltage input pairs have a maximum differential signal of ±0.5 V. In addition, the maximum signal level on analog inputs for IxP/IxN is ±0.5 V with respect to AGND. The maximum common-mode signal allowed on the inputs is ±25 mV. Figure 24 presents a schematic of the current channels inputs and their relation to the maximum common-mode voltage.

All inputs have a programmable gain amplifier (PGA) with a possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and IC inputs is set in Bits[2:0] (PGA1) of the Gain[15:0] register. The gain of the IN input is set in Bits[5:3] (PGA2) of the Gain[15:0] register; thus, a different gain from the IA, IB, or IC inputs is possible. See Tabl e 38 for details on the Gain[15:0] register.

The voltage channel has three single-ended voltage inputs: VAP, VBP, and VCP. These single-ended voltage inputs have a maximum input voltage of ±0.5 V with respect to VN. In addition, the maximum signal level on analog inputs for VxP and VN is ±0.5 V with respect to AGND. The maximum common-mode signal allowed on the inputs is ±25 mV. Figure 26 presents a schematic of the voltage channels inputs and their relation to the maximum common-mode voltage.

All inputs have a programmable gain with a possible gain selection of 1, 2, 4, 8, or 16. The setting is done using Bits[8:6] (PGA3) in the Gain[15:0] register (see Tabl e 38 ).

Figure 25 shows how the gain selection from the Gain[15:0] register works in both current and voltage channels.

DIFFERENTIAL INPU

V1 + V2 = 500mV MAX PEAK

V1+ V

500m

Figure 24. Maximum Input Level, Current Channels, Gain = 1

ANALOG-TO-DIGITAL CONVERSION

The ADE7878 has seven sigma-delta (Σ-) analog-to-digital converters (ADCs). In PSM0 mode, all ADCs are active. In PSM1 mode, the ADCs that measure the Phase A, Phase B, and Phase C currents only are active. The ADCs that measure the neutral current and the A, B, and C phase voltages are turned

COMMON MODE

= ±25mV MAX

IAP, IBP,

ICP OR INP

IAN, IBN,

ICN OR INN

08510-010

off. In PSM2 and PSM3 modes, the ADCs are powered down to minimize power consumption.

For simplicity, the block diagram in Figure 27 shows a firstorder Σ- ADC. The converter is made up of the Σ- modulator and the digital low-pass filter.

A Σ- modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7878, the sampling clock is equal to 1.024 MHz (CLKIN/16). The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and therefore the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples is averaged is a meaningful result obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.

GAIN SELECTION

IxP, VyP

IxN, VN

NOTES

1. x = A, B, C, N y = A, B, C.

K × V

08510-011

Figure 25. PGA in Current and Voltage Channels

DIFFERENTIAL INPUT

+ V2 = 500mV MAX PEAK

COMMON MODE

= ±25mV MAX

VAP, V BP

OR VCP

08510-012

500m

Figure 26. Maximum Input Level, Voltage Channels, Gain = 1

REF

CLKIN/16

LATCHED COMPARATOR

–

.....10100101.....

1-BIT DAC

-Δ ADC

DIGITAL

LOW-PASS

FILTER

ANALOG

LOW-PASS FILTER

INTEGRATO R

–

Figure 27. First-Order

08510-013

Rev. 0 | Page 24 of 92

ADE7878

The Σ- converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7878 is 1.024 MHz, and the bandwidth of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered, as shown in Figure 28. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ- modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. This is the second technique used to achieve high resolution. The result is that most of the noise is at the higher frequencies where it can be removed by the digital lowpass filter. This noise shaping is shown in Figure 28.

ANTIALIAS FILTER

SIGNAL

NOISE

SIGNAL

NOISE

Figure 28. Noise Reduction Due to Oversampling and

DIGITAL FILTER

0 2 4 512

FREQUENCY (kHz)

HIGH RESOLUTION OUTPUT FROM DIGITAL LPF

FREQUENCY (kHz)

Noise Shaping in the Analog Modulator

(RC)

SHAPED NOISE

1024

SAMPLING FREQUENCY

08510-014

Antialiasing Filter

Figure 27 also shows an analog low-pass filter (RC) on the input to the ADC. This filter is placed outside the ADE7878, and its role is to prevent aliasing. Aliasing is an artifact of all sampled systems and is illustrated in Figure 29. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Frequency components above half the sampling frequency (also known as the Nyquist frequency, that is, 512 kHz) are imaged or folded back down below 512 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only

Rev. 0 | Page 25 of 92

frequencies near the sampling frequency, that is, 1.024 MHz, move into the band of interest for metering, that is, 40 Hz to 2 kHz. To attenuate the high frequency (near 1.024 MHz) noise and prevent the distortion of the band of interest, a low-pass filer (LPF) must be introduced. For conventional current sensors, it is recommended to use one RC filter with a corner frequency of 5 kHz for the attenuation to be sufficiently high at the sampling frequency of 1.024 MHz. The 20 dB per decade attenuation of this filter is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the 20 dB per decade attenuation produced by the LPF. Therefore, when using a di/dt sensor, take care to offset the 20 dB per decade gain. One simple approach is to cascade one additional RC filter; thus, a −40 dB per decade attenuation is produced.

LIASING E FFECTS

0 2 4 512

IMAGE

FREQUENCIES

FREQUENCY (kHz)

Figure 29. Aliasing Effects

SAMPLING

FREQUENCY

1024

08510-015

ADC Transfer Function

All ADCs in the ADE7878 are designed to produce the same 24-bit signed output code for the same input signal level. With a full-scale input signal of 0.5 V and an internal reference of 1.2 V, the ADC output code is nominally 5,928,256 (0x5A7540). The code from the ADC may vary between 0x800000 (−8,388,608) and 0x7FFFFF (+8,388,607); this is equivalent to an input signal level of ±0.707 V. However, for specified performance, it is recommended not to exceed the nominal range of ±0.5 V. The ADC performance is guaranteed only for input signals lower than ±0.5 V.

CURRENT CHANNEL ADC

Figure 30 shows the ADC and signal processing path for Input IA of the current channels (it is the same for IB and IC). The ADC outputs are signed twos complement 24-bit datawords and are available at a rate of 8 kSPS (thousand samples per second). With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value. Figure 30 shows a full-scale voltage signal applied to the differential inputs (IAP and IAN). The ADC output swings between

−5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540). The input, IN, corresponds to the neutral current of a 3-phase system. If no neutral line is present, then connect this input to AGND. The datapath of the neutral current is similar to the path of the phase currents and is presented in Figure 31.

ADE7878

ZX DETECTION

CURRENT CHANNE L DATA RANGE AFTER

INTEGRATION

0x5A7540 =

+5,928,256

0xA58AC0 =

–5,928,256

×1, ×2, ×4, ×8, ×16

IAP

PGA1

IAN

+0.5V/GAIN

–0.5V/GAIN

DSP

PGA1 BITS

GAIN[2:0]

ANALOG INPUT RANGE ANALOG OUTPUT RANGE

REFERENCE

ADC

AIGAIN[23:0]

0x5A7540 =

+5,928,256

0xA58AC0 =

–5,928,256

HPFDIS

[23:0]

HPF

CURRENT CHANNE L

DATA RANGE

INTEN BIT

CONFIG [0]

DIGITAL

INTEGRATOR

LPF1

CURRENT PEAK, OVERCURRENT DETECT

CURRENT RMS ( IRMS) CALCULATION

IAWV WAVEF ORM SAMPLE REGISTER

TOTAL/FUNDAMENTAL ACTIVE AND REACT IVE POWER CALCULATION

0x5A7540 =

+5,928,256

0xA58AC0 =

–5,928,256

ZX SIGN DATA RANGE

08510-019

Figure 30. Current Channel Signal Path

DSP

PGA2 BITS

GAIN[5:3]

×1, ×2, ×4, ×8, ×16

INP

PGA2

INN

REFERENCE

ADC

NIGAIN[23:0]

HPF

INTEN BIT CONFIG[0]

DIGITAL

INTEGRATOR

CURRENT RMS (IRMS) CALCULATION

INWV WAVEFORM SAMPLE REGISTER

08510-120

Figure 31. Neutral Current Signal Path

Current Waveform Gain Registers

There is a multiplier in the signal path of each phase and neutral current. The current waveform can be changed by ±100% by writing a correspondent twos complement number to the 24-bit signed current waveform gain registers (AIGAIN[23:0], BIGAIN[23:0], CIGAIN[23:0], and NIGAIN[23:0]). For example, if 0x400000 is written to those registers, the ADC output is scaled up by 50%. To scale the input by −50%, write 0xC00000 to the registers. Equation 3 describes mathematically the function of the current waveform gain registers.

Current Waveform =

⎛

OutputADC (3)

⎜

+×

⎜ ⎝

RegisterGainCurrentofContent

⎞ ⎟

⎟ ⎠

Changing the content of AIGAIN[23:0], BIGAIN[23:0], CIGAIN[23:0], or INGAIN[23:0] affects all calculations based on its current; that is, it affects the corresponding phase active/ reactive/apparent energy and current rms calculation. In addition, waveform samples scale accordingly.

Note that the serial ports of the ADE7878 work on 32-, 16-, or 8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN, BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit

registers with the four most significant bits (MSBs) padded with 0s and sign extended to 28 bits. See Figure 32 for details.

31 28 27 24 23 0

24-BIT NUMBER0000

BITS[27:24] ARE

EQUAL TO BIT 23

BIT 23 IS A SIGN BI T

08510-016

Figure 32. 24-Bit xIGAIN Transmitted as 32-Bit Words

Current Channel HPF

The ADC outputs can contain a dc offset. This offset can create errors in power and rms calculations. High-pass filters (HPFs) are placed in the signal path of the phase and neutral currents and of the phase voltages. If enabled, the HPF eliminates any dc offset on the current channel. All filters are implemented in the DSP and, by default, they are all enabled: the 24-bit HPFDIS[23:0] register is cleared to 0x00000000. All filters are disabled by setting HPHDIS[23:0] to any non zero value.

As previously stated, the serial ports of the ADE7878 work on 32-, 16- or 8-bit words. The HPFDIS register is accessed as a 32-bit register with eight MSBs padded with 0s. See Figure 33 for details.

31 24 23 0

24-BIT NUMBER0000 0000

Figure 33. 24-Bit HPFDIS Register Transmitted as 32-Bit Word

08510-017

Rev. 0 | Page 26 of 92

ADE7878

–

Current Channel Sampling

The waveform samples of the current channel are taken at the output of HPF and stored into the IAWV, IBWV, ICWV, and INWV 24-bit signed registers at a rate of 8 kSPS. All power and rms calculations remain uninterrupted during this process. Bit 17 (DREADY) in the STATUS0[31:0] register is set when the IAWV, IBWV, ICWV, and INWV registers are available to be

read using the I

C or SPI serial port. Setting Bit 17 (DREADY) in the MASK0[31:0] register enables an interrupt to be set when the DREADY flag is set. See the Digital Signal Processor section for more details on Bit DREADY.

As previously stated, the serial ports of the ADE7878 work on 32-, 16-, or 8-bit words. When the IAWV, IBWV, ICWV, and INWV 24-bit signed registers are read from the ADE7878, they are transmitted sign extended to 32 bits. See Figure 34 for details.

31 24 23 22 0

24-BIT SIG NED NUMBER

BITS[31:24] ARE

EQUAL TO BI T 23

Figure 34. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word

BIT 23 IS A SIGN BI T

08510-018

The ADE7878 contains a high speed data capture (HSDC) port that is specially designed to provide fast access to the waveform sample registers. See the HSDC Interface section for more details.

di/dt CURENT SENSOR AND DIGITAL INTEGRATOR

The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 35 shows the principle of a di/dt current sensor.

MAGNETIC F IELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)

grator is disabled by default when the ADE7878 is powered up and after reset. Setting Bit 0 (INTEN) of the CONFIG[15:0] register turns on the integrator. Figure 36 and Figure 37 show the magnitude and phase response of the digital integrator.

Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. An antialiasing filter of at least the second order is needed to avoid noise aliasing back in the band of interest when the ADC is sampling (see the Antialiasing Filter section).

–50

MAGNITUDE (d B)PHASE (Degrees)

0.01 0.1 1 10 100 1000

–50

–100

0 500 1000 1500 2000 2500 3000 3500 4000

Figure 36. Combined Gain and Phase Response of the

FREQUENCY (Hz)

Digital Integrator

08510-116

The DICOEFF[23:0] 24-bit signed register is used in the digital integrator algorithm. At power-up or after a reset, its value is 0x000000. Before turning on the integrator, this register must be initialized with 0xFF8000. DICOEFF[23:0] is not used when the integrator is turned off and can remain at 0x000000 in that case.

+ EMF (ELE CTROMOT IVE FORCE ) – INDUCED BY CHANGES IN

MAGNETIC FLUX DENSITY (di/dt)

Figure 35. Principle of a di/dt Current Sensor

The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor

08510-020

–20

–25

MAGNITUDE (dB)PHASE (Degrees)

–30

30 35 40 45 50 55 60 65 70

–89.96

–89.97

FREQUENCY (Hz)

loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor.

Due to the di/dt sensor, the current signal needs to be filtered before it can be used for power measurement. On each phase and neutral current datapath, there is a built-in digital integrator to recover the current signal from the di/dt sensor. The digital inte-

Rev. 0 | Page 27 of 92

–89.98

–89.99

30 35 40 45 50 55 60 65 70

Figure 37. Combined Gain and Phase Response of the

Digital Integrator (40 Hz to 70 Hz)

FREQUENCY (Hz)

8510-101

As previously stated, the serial ports of the ADE7878 work on 32-, 16-, or 8-bit words. Similar to the registers shown in Figure 32, the

ADE7878

DICOEFF[23:0] 24-bit signed register is accessed as a 32-bit register with four MSBs padded with 0s and sign extended to 28 bits, which practically means it is transmitted equal to 0xFFF8000.

When the digital integrator is switched off, the ADE7878 can be used directly with a conventional current sensor, such as a current transformer (CT).

energy and voltage rms calculation. In addition, waveform samples are scaled accordingly.

As previously stated, the serial ports of the ADE7878 work on 32-, 16-, or 8-bit words, and the DSP works on 28 bits. As presented in Figure 32, the AVGAIN, BVGAIN, and CVGAIN registers are accessed as 32-bit registers with four MSBs padded with 0s and sign extended to 28 bits.

VOLTAGE CHANNEL ADC

Figure 38 shows the ADC and signal processing chain for Input VA in the voltage channel. The VB and VC channels have similar processing chains. The ADC outputs are signed twos complement 24-bit words and are available at a rate of 8 kSPS. With the specified full-scale analog input signal of ±0.5 V, the ADC produces its maximum output code value. Figure 38 shows a full-scale voltage signal being applied to the differential inputs (VA and VN). The ADC output swings between −5,928,256 (0xA58AC0) and +5,928,256 (0x5A7540).

Voltage Waveform Gain Registers

There is a multiplier in the signal path of each phase voltage. The voltage waveform can be changed by ±100% by writing a corresponding twos complement number to the 24-bit signed current waveform gain registers (AVGAIN[23:0], BVGAIN[23:0], and CVGAIN[23:0]). For example, if 0x400000 is written to those registers, the ADC output is scaled up by 50%. To scale the input by −50%, write 0xC00000 to the registers. Equation 4 describes mathematically the function of the current waveform gain registers.

Voltage Waveform =

⎛

OutputADC (4)

⎜

+×

⎜ ⎝

RegisterGainVoltageofContent

Changing the content of AVGAIN[23:0], BVGAIN[23:0], and CVGAIN[23:0] affects all calculations based on its voltage; that is, it affects the corresponding phase active/reactive/apparent

⎞ ⎟

⎟ ⎠

Voltage Channel HPF

As explained in the Current Channel HPF section, the ADC outputs can contain a dc offset that can create errors in power and rms calculations. HPFs are placed in the signal path of the phase voltages, similar to the ones in the current channels. The HPFDIS[23:0] register can enable or disable the filters. See the Current Channel HPF section for more details.

Voltage Channel Sampling

The waveform samples of the current channel are taken at the output of HPF and stored into VAWV, VBWV, and VCWV 24-bit signed registers at a rate of 8 kSPS. All power and rms calculations remain uninterrupted during this process. Bit 17 (DREADY) in the STATUS0[31:0] register is set when the VAWV, VBWV, and VCWV registers are available to be read

using the I

As previously stated, the serial ports of the ADE7878 work on 32-, 16-, or 8-bit words. Similar to registers presented in Figure 34, the VAWV, VBWV, and VCWV 24-bit signed registers are transmitted sign extended to 32 bits.

The ADE7878 contains an HSDC port that is specially designed to provide fast access to the waveform sample registers. See the HSDC Interface section for more details.

Rev. 0 | Page 28 of 92

+ 64 hidden pages

ANALOG DEVICES ADE7878 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUIT

TERMINOLOGY

POWER MANAGEMENT

PSM0—NORMAL POWER MODE

PSM1—REDUCED POWER MODE

PSM2—LOW POWER MODE

PSM3—SLEEP MODE

POWER-UP PROCEDURE

HARDWARE RESET

SOFTWARE RESET FUNCTIONALITY

THEORY OF OPERATION

ANALOG INPUTS

ANALOG-TO-DIGITAL CONVERSION

Antialiasing Filter

ADC Transfer Function

CURRENT CHANNEL ADC

Current Waveform Gain Registers

Current Channel HPF

Current Channel Sampling

di/dt CURENT SENSOR AND DIGITAL INTEGRATOR

VOLTAGE CHANNEL ADC

Voltage Waveform Gain Registers

Voltage Channel HPF

Voltage Channel Sampling