High accuracy supports 50 Hz/60 Hz IEC 62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Compatible with 3-phase, 3-wire delta and 3-phase, 4-wire
Wye configurations
Supplies average active power on the frequency outputs F1
and F2
High frequency output (CF) is intended for calibration and
supplies instantaneous active power
Logic output REVP indicates a potential miswiring or
negative power on the sum of all phases
Dropout indication for each phase on LED driver pins
Phase sequence error detection
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and over time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.4 V ± 8% (25 ppm/°C typical) with
external overdrive capability
Single 5 V supply, low power (42.5 mW typical)
Low cost CMOS process
with Phase Drop Indication
ADE7762
GENERAL DESCRIPTION
The ADE77621 is a high accuracy polyphase electrical energy
measurement IC. The ADE7762 specifications surpass the
accuracy requirements as quoted in the IEC62053-21 standard.
The only analog circuitry used in the ADE7762 is in the
analog-to-digital converters (ADCs) and reference circuit. All
other signal processing (for example, multiplication, filtering,
and summation) is carried out in the digital domain. This
approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7762 supplies average active power information on
the low frequency outputs, F1 and F2. These logic outputs can
be used to directly drive an electromechanical counter or to
interface with a microcontroller (MCU). The CF logic output
gives instantaneous active power information. This output is
intended to be used for calibration purposes.
The ADE7762 includes a power supply monitoring circuit on the
pin. The ADE7762 remains inactive until the supply voltage
V
DD
on V
reaches 4 V. If the supply falls below 4 V, the ADE7762
DD
resets and no pulses are issued on F1, F2, and CF.
A multiple multiplexed logic output provides phase dropout per
phase, reverse polarity per phase, and a phase sequence error.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no load
threshold ensures that the ADE7762 does not exhibit any creep
when there is no load.
The ADE7762 is available in a 28-lead SOIC package.
1
U.S. Patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Gain Error External 2.5 V reference, IA = IB = IC = 500 mV dc ±9 % ideal
REFERENCE INPUT
REF
Input Voltage Range 2.4 V + 8% 2.6 V
IN/OUT
2.4 V − 8% 2.2 V
Input Impedance 3.3 kΩ
Input Capacitance 10 pF
ON-CHIP REFERENCE Nominal 2.4 V
Reference Error ±200 mV
Temperature Coefficient 25 ppm/°C
CLKIN (INPUT CLOCK FREQUENCY) All specifications for CLKIN of 10 MHz 10 MHz
LOGIC INPUTS3
ACF, S0, S1, and ABS
Input High Voltage, V
Input Low Voltage, V
V
INH
V
INL
= 5 V ± 5% 2.4 V
DD
= 5 V ± 5% 0.8 V
DD
Input Current, IIN Typically 10 nA, VIN = 0 V to VDD ±3 μA
Input Capacitance, CIN 10 pF
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH I
Output Low Voltage, VOL I
= 10 mA, V
SOURCE
= 10 mA, VDD = 5 V 0.5 V
SINK
= 5 V 4.5 V
DD
CF and REVP
Output High Voltage, VOH V
Output Low Voltage, VOL V
= 5 V, I
DD
= 5 V, I
DD
= 5 mA 4.5 V
SOURCE
= 5 mA 0.5 V
SINK
LED_CTRL VDD = 5 V, CLKIN = 10 MHz
Output Frequency 17.39 kHz
Output High Voltage VDD = 5 V, I
Output Low Voltage VDD = 5 V, I
= 10 mA 4.5 V
SOURCE
= 10 mA 0.4 V
SINK
LED_A, LED_B, LED_C
Output Low I
V
SINK
= 4.75 V 8 mA
DD
Output High Source VDD = 4.75 V 6 mA
MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
0.1 % reading
0.01 % reading
0.1 % reading
V peak
difference
Rev. 0 | Page 4 of 28
ADE7762
www.BDTIC.com/ADI
Parameter Conditions Min Typ Max Unit
POWER SUPPLY For specified performance
VDD 5 V ± 5% 4.75 5.25 V
IDD 8.5 10 mA
1
See the Terminology section for explanation of specifications.
2
See the plots in the Typical Performance Characteristics section.
3
Sample tested during initial release and after any redesign or process changes that might affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, T
MIN
to T
= −40°C to +85°C, unless otherwise noted.
MAX
Table 2.
Parameter
3
t
F1 and F2 pulse width (logic high) 120 ms
1
1,2
Conditions Value Unit
t2 Output pulse period (see the Transfer Function section) See Figure 2 sec
t3 Time between F1 rising edge and F2 rising edge ½ t2 sec
3, 4
t
CF pulse width (logic high) 90 ms
4
5
t
CF pulse period (see the Transfer Function section) See Table 7 sec
5
t6 Minimum time between F1 and F2 pulse 4/CLKIN sec
t7 LED_CTRL pulse width 28.8 μs
t8 LED_CTRL period 57.5 μs
t9 LED pulse width 7.2 μs
1
Sample tested during initial release and after any redesign or process changes that might affect this parameter.
2
See Figure 2.
3
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section).
4
CF is not synchronous to F1 or F2 frequency outputs.
5
The CF pulse is always 1 μs in the high frequency mode (see the Frequency Outputs section).
t
1
F1
t
6
t
2
t
F2
t
4
CF
3
t
5
05757-002
Figure 2. Timing Diagram for Frequency Outputs
t
8
t
7
LED1
LED2
LED3
t
9
Figure 3. Timing Diagram for LED Drivers
Rev. 0 | Page 5 of 28
NOT
LED4
USED
NOT
LED5
LED6
USED
05757-003
ADE7762
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to AGND −0.3 V to +7 V
VDD to DGND −0.3 V to +7 V
Analog Input Voltage to AGND
VA P, V BP, V C P, VN , I A P, IA N, IB P, I BN , I CP,
and ICN
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
28-Lead SOIC, Power Dissipation 63 mW
θJA Thermal Impedance 55°C/W
Lead Temperature, Soldering
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 28
ADE7762
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 LED_CTRL
LED Control Output. The LED_CTRL signal multiplexes the indication of phase drop, phase sequence
error, and per phase reverse power on the LED_A, LED_B, and LED_C pins.
2 LED_A
Phase A Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on Phase A (see the Phase Monitor section).
3 CF
Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information.
This output is intended to be used for calibration purposes.
4 DGND
This provides the ground reference for the digital circuitry in the ADE7762, that is, multipliers, filters,
and digital-to-frequency converters. Because the digital return currents in the ADE7762 are small, it is
acceptable to connect this pin to the analog ground plane of the whole system.
5 V
DD
Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7762. The supply
voltage should be maintained at 5 V ± 5% for a specified operation. This pin should be decoupled to
DGND with a 10 μF capacitor in parallel with a 100 nF ceramic capacitor.
6 REVP
This logic output goes logic high when negative power is detected on the sum of the three phase
powers. This output is not latched and resets when positive power is once again detected (see the
Negative Total Power Detection section).
7, 8;
9, 10;
11, 12
IAP, IAN;
IBP, IBN;
ICP, ICN
Analog Inputs for Current Channels. These channels are intended for use with current transducers and
are referenced in this document as current channels. These inputs are fully differential voltage inputs
with maximum differential input signal levels of ±0.5 V (see the Analog Inputs section). Both inputs
have internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.
13 AGND
This pin provides the ground reference for the analog circuitry in the ADE7762 (ADCs and reference).
This pin should be tied to the analog ground plane or the quietest ground reference in the system. This
quiet ground reference should be used for all analog circuitry, such as antialiasing filters and current
and voltage transducers. To keep ground noise around the ADE7762 to a minimum, the quiet ground
plane should connect to the digital ground plane at only one point. It is acceptable to place the entire
device on the analog ground plane.
14 REF
IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.4 V ± 8% and a typical temperature coefficient of 25 ppm/°C. An external reference source can also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic
capacitor.
15, 16, 17,
18
VN, VCP, VBP, VAP
Analog Inputs for the Voltage Channels. These channels are intended for use with voltage transducers
and are referenced in this document as voltage channels. These inputs are single-ended voltage inputs
with a maximum signal level of ±0.5 V with respect to VN for a specified operation. All inputs have
internal ESD protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.
19
This logic input is used to select the method by which the three active energies from each phase are
ABS
summed. It selects between the arithmetical sum of the three energies (ABS
the absolute values (ABS
section.
20 SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table 7 shows how the calibration frequencies are selected.
LED_CTRL
LED_A
DGND
V
REVP
IAP
IAN
IBP
IBN
ICP
ICN
AGND
REF
IN/OUT
CF
DD
1
2
3
4
5
ADE7762
6
TOP VIEW
7
(Not to Scale)
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LED_B
LED_C
F1
F2
S1
S0
CLKOUT
CLKIN
SCF
ABS
VAP
VBP
VCP
VN
05757-004
Figure 4. Pin Configuration
logic high) or the sum of
logic low). See the Mode Selection of the Sum of the Three Active Energies
Rev. 0 | Page 7 of 28
ADE7762
www.BDTIC.com/ADI
Pin No. Mnemonic Description
21 CLKIN
22 CLKOUT
23, 24 S0, S1
25, 26 F2, F1
27 LED_C
28 LED_B
Master Clock for the ADCs and Digital Signal Processing. An external clock can be provided at this logic
input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to
provide a clock source for the ADE7762. The clock frequency for the specified operation is 10 MHz.
Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer
to the crystal manufacturer’s data sheet for the load capacitance requirements.
A crystal can be connected across this pin and CLKIN as described for Pin 21 to provide a clock source
for the ADE7762. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN
or when a crystal is used.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion for design flexibility.
Low Frequency Logic Outputs. F1 and F2 supply average active power information. These logic outputs
can be used to drive electromechanical counters and 2-phase stepper motors directly (see the Transfer
Function section).
Phase C Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on Phase C (see the Phase Monitor section).
Phase B Phase Monitor Output. LEDs are connected to this pin to indicate phase drop or reverse power
on Phase B (see the Phase Monitor section).
Rev. 0 | Page 8 of 28
ADE7762
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
% ERROR
–0.1
–0.2
–0.3
–0.4
–0.5
PHASE C
PHASE A + B + C
PHASE B
0
PHASE A
0.1110100
CURRENT CHANNEL (% of Full Scale)
Figure 5. Error As a Percent of Reading
with Internal Reference (Wye Connection)
1.0
05757-007
0.5
0.4
0.3
0.2
+25°C, POW ER FACTOR = 1
0.1
0
% ERROR
–0.1
–40°C, POW ER FACTOR = 1
–0.2
–0.3
–0.4
–0.5
0.1110100
CURRENT CHANNEL (% of Full Scale)
+85°C, POW ER FACTOR = 1
Figure 8. Error As a Percent of Reading over Temperature
with External Reference (Wye Connection)
1.0
05757-010
0.8
0.6
0.4
0.2
% ERROR
0
–0.2
–0.4
0.1110100
–40°C, POW ER FACTO R = 0.5
+25°C, POW ER FACTOR = 1
+25°C, POW ER FACTOR = 0.5
+85°C, POWER FACTO R = 0.5
CURRENT CHANNEL (% of Full Scale)
Figure 6. Error As a Percent of Reading over Power Factor
with Internal Reference (Wye Connection)
1.0
0.8
0.6
0.4
0.2
0
% ERROR
–0.2
–0.4
–0.5
–0.8
–1.0
0.1110100
–40°C, POW ER FACTOR = 1
+25°C, POW ER FACTOR = 1
+85°C, POW ER FACTOR = 1
CURRENT CHANNEL (% of Full Scale)
Figure 7. Error As a Percent of Reading over Temperature
with Internal Reference (Wye Connection)
0.5
0
% ERROR
–0.5
–1.0
05757-008
–1.5
POWER FACT OR = 1
POWER FACT OR = 0.5
4550556065
LINE FREQ UENCY (Hz)
05757-011
Figure 9. Error As a Percent of Reading over Frequency
with an Internal Reference (Wye Connection)
0.5
0.4
0.3
0.2
0.1
% ERROR
–0.1
–0.2
–0.3
–0.4
05757-009
–0.5
5V
0
5.25V
0.1110100
CURRENT CHANNEL (% of Full Scale)
4.75V
05757-012
Figure 10. Error As a Percent of Reading over Power Supply
with Internal Reference (Wye Connection)
Rev. 0 | Page 9 of 28
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