Analog Devices ADE7759 a Datasheet

Active Energy Metering IC with

a

FEATURES
High Accuracy, Supports IEC 687/1036
On-Chip Digital Integrator Allows Direct Interface with

Current Sensors with di/dt Output Such as Rogowski Coil
Less Than 0.1% Error over a Dynamic Range of 1000 to 1
On-Chip User-Programmable Threshold for Line Voltage

SAG Detection and PSU Supervisory
Supplies Sampled Waveform Data
(40 Bits)
Digital Power, Phase, and Input DC Offset Calibration
On-Chip Temperature Sensor (Typical 1 LSB/C Resolution)
SPI Compatible Serial Interface
Pulse Output with Programmable Frequency
Interrupt Request Pin (IRQ) and IRQ Status Register
Proprietary ADCs and DSP provide High Accuracy over

Large Variations in Environmental Conditions and Time
Reference 2.4 V  8% (20 ppm/C Typical) with External

Overdrive Capability
Single 5 V Supply, Low Power Consumption (25 mW

Typical)

GENERAL DESCRIPTION

The ADE7759 is an accurate active power and energy measure­ment IC with a serial interface and a pulse output. The ADE7759
incorporates two second-order Σ-∆ ADCs, a digital integrator
(on CH1), reference circuitry, temperature sensor, and all the
signal processing required to perform active power and energy
measurement.

An on-chip digital integrator allows direct interface to di/dt
current sensors such as a Rogowski coil. The digital integrator
eliminates the need for an external analog integrator and pro­vides excellent long-term stability and precise phase matching
between the current and the voltage channels. The integrator

and Active Energy

AV

FUNCTIONAL BLOCK DIAGRAM

DD

RESET

di/dt Sensor Interface

ADE7759

can be switched off if the ADE7759 is used with conventional
current sensors.

The ADE7759 contains a sampled waveform register and an
active energy register capable of holding at least 11.53 seconds
of accumulated power at full ac load. Data is read from the
ADE7759 via the serial interface. The ADE7759 also provides a
pulse output (CF) with frequency that is proportional to the
active power.

In addition to active power information, the ADE7759 also
provides various system calibration features, i.e., channel offset
correction, phase calibration, and power offset correction. The
part also incorporates a detection circuit for short duration
voltage drop (SAG). The voltage threshold and the duration (in
number of half-line cycles) of the drop are user programmable.
An open-drain logic output (SAG) goes active low when a sag
event occurs.

A zero crossing output (ZX) produces an output that is synchro­nized to the zero crossing point of the line voltage. This output
can be used to extract timing or frequency information from the
line. The signal is also used internally to the chip in the line
cycle energy accumulation mode; i.e., the number of half-line
cycles in which the energy accumulation occurs can be con­trolled. Line cycle energy accumulation enables a faster and
more precise energy accumulation and is especially useful dur­ing calibration. This signal is also useful for synchronization of
relay switching with a voltage zero crossing.

The interrupt request output is an open drain, active low logic
output. The interrupt status register indicates the nature of the
interrupt, and the interrupt enable register controls which event
produces an output on the IRQ pin. The ADE7759 is available
in a 20-lead SSOP package.

DV

DGND

DD

*

V1P

V1N

TEMP

SENSOR

V2P

V2N

2.4V

REFERENCE

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

AGND

4k

ADC

ADC

IN/OUT

MULTIPLIER

HPF1

APGAIN[11:0]

LPF1

DIN DOUT SCLKREF

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

LPF2

CFDEN[11:0]

CLKIN

ADE7759

APOS[15:0]

DFC

CLKOUT

INTEGRATOR

PHCAL[7:0]



REGISTERS AND

SERIAL INTERFACE

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2002 Analog Devices, Inc. All rights reserved.

MULTIPLIER

dt

CFNUM[11:0]

CS IRQ

ZX

SAG

CF

ADE7759

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8

PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8

POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8

ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

TYPICAL PERFORMANCE CHARACTERISTICS (TPC) . . 9

TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

di/dt CURRENT SENSOR AND DIGITAL

INTEGRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13

LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14

Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the ADE7759 Interrupts with an MCU . . . . . . . . . 15

Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16

ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16

Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18

Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CHANNEL 1 AND CHANNEL 2 WAVEFORM

SAMPLING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 19

ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 20

ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 21

Integration Time under Steady Load . . . . . . . . . . . . . . . . 22

POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 22

ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 22

LINE CYCLE ENERGY ACCUMULATION MODE . . . 24

CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24

Calculating the Average Active Power . . . . . . . . . . . . . . . 24

Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 25

Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

SUSPENDING THE ADE7759 FUNCTIONALITY . . . . 26

APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 26

SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

CHECKSUM REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 28

REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 30

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 30

Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Interrupt Status Register (04H) . . . . . . . . . . . . . . . . . . . . 32

Reset Interrupt Status Register (05H) . . . . . . . . . . . . . . . 32

CH1OS Register (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . 33

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 34

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

–2–

REV. A

ADE7759

(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,

SPECIFICATIONS

Parameter Spec Unit Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth 14 kHz CLKIN = 3.579545 MHz
Measurement Error

Channel 1 Range = 0.5 V Full-Scale

Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 16 0.2 % typ Over a Dynamic Range 1000 to 1

Channel 1 Range = 0.25 V Full-Scale

Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.2 % typ Over a Dynamic Range 1000 to 1
Gain = 16 0.2 % typ Over a Dynamic Range 1000 to 1

Channel 1 Range = 0.125 V Full-Scale

Gain = 1 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 2 0.1 % typ Over a Dynamic Range 1000 to 1
Gain = 4 0.2 % typ Over a Dynamic Range 1000 to 1
Gain = 8 0.2 % typ Over a Dynamic Range 1000 to 1

Gain = 16 0.4 % typ Over a Dynamic Range 1000 to 1
Phase Error
AC Power Supply Rejection

Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V

DC Power Supply Rejection

Output Frequency Variation (CF) ±0.3 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V

ANALOG INPUTS

Maximum Signal Levels ± 0.5 V max V1P, V1N, V2N, and V2P to AGND
Input Impedance (DC) 390 kW min
Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545 MHz
Gain Error

Channel 1

Channel 2 ± 4% typ V2 = 0.5 V dc

Gain Error Match

Channel 1

Channel 2 ± 0.3 % typ Gain = 1, 2, 4, 8, 16

Offset Error

Channel 1 ± 20 mV max Gain = 1
Channel 2 ± 20 mV max Gain = 1

WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS

Channel 1 See Channel 1 Sampling

Signal-to-Noise plus Distortion 62 dB typ 150 mV rms/60 Hz, Range = 0.5 V, Gain = 2
Bandwidth (–3 dB) 14 kHz CLKIN = 3.579545 MHz

Channel 2 See Channel 2 Sampling

Signal-to-Noise plus Distortion 52 dB typ 150 mV rms/60 Hz, Gain = 2
Bandwidth (–3 dB) 156 Hz CLKIN = 3.579545 MHz

1

1, 3

Range = 0.5 V Full-Scale ± 4% typ V1 = 0.5 V dc

Range = 0.25 V Full-Scale ± 4% typ V1 = 0.25 V dc

Range = 0.125 V Full-Scale ± 4% typ V1 = 0.125 V dc

Range = 0.5 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16

Range = 0.25 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16

Range = 0.125 V Full-Scale ± 0.3 % typ Gain = 1, 2, 4, 8, 16

1

on Channel 1 Channel 2 = 300 mV rms/60 Hz, Gain = 1

between Channels ± 0.05 ∞ max Line Frequency = 45 Hz to 65 Hz, HPF on

3

1

1

1

T

to T

MIN

1

1

= –40C to +85C, unless otherwise noted.)

MAX

AVDD = DVDD = 5 V + 175 mV rms/120 Hz

Channel 2 = 300 mV rms/60 Hz, Gain = 1
AVDD = DVDD = 5 V ± 250 mV dc

Channel 2 = 300 mV rms/60 Hz, Gain = 1

External 2.5 V Reference, Gain = 1 on Channels 1 and 2

External 2.5 V Reference

REV. A

–3–

ADE7759–SPECIFICATIONS

(continued)

Parameter Spec Unit Test Conditions/Comments

REFERENCE INPUT

REF

Input Voltage Range 2.6 V max 2.4 V + 8%

IN/OUT

2.2 V min 2.4 V – 8%

Input Capacitance 10 pF max

ON-CHIP REFERENCE Nominal 2.4 V at REF

IN/OUT

Pin
Reference Error ± 200 mV max
Current Source 10 mA max
Output Impedance 4 kW min
Temperature Coefficient 20 ppm/∞C typ

CLKIN Note All Specifications CLKIN of 3.579545 MHz

Input Clock Frequency 4 MHz max

1 MHz min

LOGIC INPUTS

RESET, DIN, SCLK, CLKIN, and CS
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

INL

IN

IN

INH

2.4 V min DVDD = 5 V ± 5%

0.8 V max DVDD = 5 V ± 5%
± 3 mA max Typically 10 nA, VIN = 0 V to DV
10 pF max

DD

LOGIC OUTPUTS

SAG and IRQ Open Drain Outputs, 10 kW pull-up resistor

Output High Voltage, V
Output Low Voltage, V

OL

OH

4V minI

0.4 V max I

SOURCE

= 0.8 mA

SINK

= 5 mA

ZX and DOUT

Output High Voltage, V
Output Low Voltage, V

OL

OH

4V minI

0.4 V max I

SOURCE

= 0.8 mA

SINK

= 5 mA

CF

Output High Voltage, V
Output Low Voltage, V

OL

OH

4V minI
1V maxI

SOURCE

= 7 mA

SINK

= 5 mA

POWER SUPPLY For Specified Performance

AV

DD

4.75 V min 5 V – 5%

5.25 V max 5 V + 5%

DV

DD

4.75 V min 5 V – 5%

5.25 V max 5 V + 5%

AI

DD

DI

DD

NOTES

1

See Terminology section for explanation of specifications.

2

See plots in Typical Performance Characteristics.

3

See Analog Inputs section.

Specifications subject to change without notice.

3 mA max Typically 2.0 mA
4 mA max Typically 3.0 mA

–4–

REV. A

ADE7759

(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

TIMING CHARACTERISTICS

Parameter A, B Versions Unit Test Conditions/Comments

Write Timing

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

Read Timing

t

9

t

10

3

t

11

4

t

12

4

t

13

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.

2

See Figures 2 and 3 and Serial Interface section of this data sheet.

3

Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.

20 ns (min) CS Falling Edge to First SCLK Falling Edge
150 ns (min) SCLK Logic High Pulsewidth
150 ns (min) SCLK Logic Low Pulsewidth
10 ns (min) Valid Data Setup Time before Falling Edge of SCLK
5 ns (min) Data Hold Time after SCLK Falling Edge

6.4 ms (min) Minimum Time between the End of Data Byte Transfers
4 ms (min) Minimum Time between Byte Transfers during a Serial Write
100 ns (min) CS Hold Time after SCLK Falling Edge

4 ms (min) Minimum Time between Read Command (i.e., a Write to Communications

4 ms (min) Minimum Time between Data Byte Transfers during a Multibyte Read
30 ns (min) Data Access Time after SCLK Rising Edge following a Write to the Communica-

100 ns (max) Bus Relinquish Time after Falling Edge of SCLK
10 ns (min)
100 ns (max) Bus Relinquish Time after Rising Edge of CS
10 ns (min)

1, 2

XTAL, T

MIN

to T

= –40C to +85C, unless otherwise noted.)

MAX

Register) and Data Read

tions Register

CS

SCLK

DIN

CS

SCLK

DIN

DOUT

I

OL

2.1V

I

OH

OUTPUT

PIN

TO

50pF

200A

C

L

1.6mA

Figure 1. Load Circuit for Timing Specifications

t

t

1

2

1 DB0 DB7 DB0

00

t

3

t

4

A4 A3 A2 A1 A0 DB7

COMMAND BYTE

t

5

t

7

MOST SIGNIFICANT BYTE

t

7

LEAST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

t

1

A4 A3 A2 A1 A0000

t

9

t

11

DB7

MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTECOMMAND BYTE

t

10

t

11

DB0 DB7 DB0

Figure 3. Serial Read Timing

t

8

t

6

t

13

t

12

REV. A

–5–

ADE7759

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25∞C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

DD

DV

to AVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

Analog Input Voltage to AGND

,

V1P, V1N, V2P

Reference Input Voltage to AGND . . –0.3 V to AV

Digital Input Voltage to DGND . . . . –0.3 V to DV

Digital Output Voltage to DGND . . . –0.3 V to DV

and V2N . . . . . . . . . . . . . . . . –6 V to +6 V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Model Package Option*

ADE7759ARS RS-20
ADE7759ARSRL RS-20
EVAL-ADE7759EB ADE7759 Evaluation Board

*RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small

Outline Package in reel.

ORDERING GUIDE

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C

20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 112∞C/W

q

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215∞C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADE7759 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. A

PIN CONFIGURATION

ADE7759

1

RESET

2

DV

DD

3

AV

DD

4

V1P

5

V1N CLKOUT

ADE7759

TOP VIEW

6

V2N

(Not to Scale)

7

V2P

8

AGND

REF

9

IN/OUT

10

DGND CF

20

19

18

17

16

15

14

13

12

11

DIN

DOUT

SCLK

CS

CLKIN

IRQ

SAG

ZX

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 RESET Reset Pin for the ADE7759. A logic low on this pin will hold the ADCs and digital circuitry

(including the serial interface) in a reset condition.

2DV

DD

Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7759.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled to DGND with a 10 mF capacitor in parallel with a ceramic 100 nF capacitor.

3AV

DD

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7759.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling method.
This pin should be decoupled to AGND with a 10 mF capacitor in parallel with a ceramic 100 nF
capacitor.

4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with the di/dt current transducers

such as Rogowski coil, or other current sensors such as shunt or current transformer (CT). These
inputs are fully differential voltage inputs with maximum differential input signal levels of ± 0.5 V,
± 0.25 V, and ± 0.125 V, depending on the full-scale selection—see Analog Inputs section.
Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these
pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry. In addi­tion, an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage.

6, 7V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs

are fully differential voltage inputs with a maximum differential signal level of ± 0.5 V. Channel 2
also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins
with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and an over­voltage of ±6V can be sustained on these inputs without risk of permanent damage.

8 AGND This pin provides the ground reference for the analog circuitry in the ADE7759, i.e., ADCs and

reference. This pin should be tied to the analog ground plane or the quietest ground reference in
the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing
filters, current and voltage transducers. To keep ground noise around the ADE7759 to a minimum,
the quiet ground plane should be connected to the digital ground plane at only one point. It is
acceptable to place the entire device on the analog ground plane—see Application Information section.

9 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal
value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/∞C. An external reference
source may be connected at this pin. In either case, this pin should be decoupled to AGND with
a 1 mF capacitor in parallel with a 100 nF capacitor.

10 DGND This provides the ground reference for the digital circuitry in the ADE7759, i.e., multiplier, filters,

and frequency output (CF). Because the digital return currents in the ADE7759 are small, it is
acceptable to connect this pin to the analog ground plane of the system—see Application Information
section. However, high bus capacitance on the DOUT pin may result in noisy digital current that
affects performance.

11 CF Calibration Frequency Logic Output. The CF logic output gives Active Power information. This

output is intended to be used for operational and calibration purposes. The full-scale output fre­quency can be adjusted by writing to the APGAIN, CFNUM, and CFDEN registers—see Energy
to Frequency Conversion section.

REV. A

–7–

ADE7759

PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Description

12 ZX Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at

the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section.

13 SAG This open-drain logic output goes active low when either no zero crossings are detected or a low

voltage threshold (Channel 2) is crossed for a specified duration—see Line Voltage Sag Detec­tion section.

14 IRQ Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts

include active energy register rollover, active energy register at half-full, zero crossing, SAG, and
arrivals of new waveform samples—see Interrupts section.

15 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this

logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and
CLKOUT to provide a clock source for the ADE7759. The clock frequency for specified opera­tion is 3.579545 MHz. Ceramic load capacitors of between 10 pF and 30 pF should be used with
the gate oscillator circuit. Refer to crystal manufacturer’s data sheet for load capacitance requirements.

16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source

for the ADE7759. The CLKOUT pin can drive one CMOS load when either an external clock is
supplied at CLKIN or a crystal is being used.

17 CS Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7759 to

share the serial bus with several other devices—see Serial Interface section.

18 SCLK Serial Clock Input for the Synchronous serial interface. All serial data transfers are synchronized to

this clock—see Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock
source that has a slow edge transition time, e.g., opto-isolator outputs.

19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK.

This logic output is normally in a high impedance state unless it is driving data onto the serial data
bus—see Serial Interface section.

20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see

Serial Interface section.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by the
ADE7759 is defined by the following formula:

Percentage Error

Energy registered by the ADE True Energy

PHASE ERROR BETWEEN CHANNELS

The digital integrator and the HPF1 (High-Pass Filter) in
Channel 1 have nonideal phase response. To offset this phase
response and equalize the phase response between channels, two
phase correction networks are placed in Channel 1: one for the
digital integrator and the other for the HPF1. Each phase cor­rection network corrects the phase response of the corresponding
component and ensures a phase match between Channel 1
(current) and Channel 2 (voltage) to within ±0.1∞ over a range
of 45 Hz to 65 Hz and ± 0.2∞ over a range 40 Hz to 1 kHz.

POWER SUPPLY REJECTION

This quantifies the ADE7759 measurement error as a percent­age of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A second reading is obtained with the same input
signal levels when an ac (175 mV rms/120 Hz) signal is intro­duced onto the supplies. Any error introduced by this ac signal
is expressed as a percentage of reading—see Measurement Error
definition above. For the dc PSR measurement a reading at

=

7759 –

True Energy

nominal supplies (5 V) is taken. A second reading is obtained
with the same input signal levels when the supplies are varied ±5%.
Any error introduced is again expressed as a percentage of reading.

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a dc analog input signal. The magni­tude of the offset depends on the gain and input range selection—see
Typical Performance Characteristics. However, when HPF1 is
switched on, the offset is removed from Channel 1 (current) and
the power calculation is not affected by this offset. The offsets
may be removed by performing an offset calibration—see Analog
Inputs section.

GAIN ERROR

The gain error in the ADE7759 ADCs is defined as the difference
between the measured ADC output code (minus the offset)
and the ideal output code—see Channel 1 ADC and Channel
2 ADC. It is measured for each of the input ranges on Channel
1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a
percentage of the ideal code.

GAIN ERROR MATCH

The Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 (for each of
the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a
percentage of the output ADC code obtained under a gain of 1.
This gives the gain error observed when the gain selection is
changed from 1 to 2, 4, 8, or 16.

–8–

REV. A

0.5

CURRENT – A

0.5

0.01

ERROR – %

0.1 1 10 100

0.4

0.3

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

FULL SCALE = 0.5V
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE

–40C, PF = 0.5

+25C, PF = 1

+85C, PF = 0.5

+25C, PF = 0.5

CURRENT – A

0.5

0.01

ERROR – %

0.1 1 10 100

0.4

0.3

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

FULL SCALE = 0.5V
GAIN = 1
INTEGRATOR OFF

EXTERNAL REFERENCE

–40C, PF = 0.5

+25C, PF = 1

+85C, PF = 0.5

+25C, PF = 0.5

CURRENT – A

0.5

0.01

ERROR – %

0.1 1 10 100

0.4

0.3

0.2

0.1

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

FULL SCALE = 0.5V
GAIN = 4
INTEGRATOR OFF
INTERNAL REFERENCE

–40C, PF = 0.5

+25C, PF = 1

+85C, PF = 0.5

+25C, PF = 0.5

0.4

0.3

0.2

0.1

0.0

ERROR – %

–0.1

–0.2

–0.3

–0.4

–0.5

0.01 0.1 1 10 100

+85C, PF = 1

FULL SCALE = 0.5V
GAIN = 1
INTEGRATOR OFF
INTERNAL REFERENCE

–40C, PF = 1

+25C, PF = 1

CURRENT – A

TPC 1. Error as a % of Reading

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

ERROR – %

–0.2

–0.3

–0.4

–0.5

0.01 0.1 1 10 100

+25C, PF = 1

FULL SCALE = 0.5V
GAIN = 1
INTEGRATOR OFF

EXTERNAL REFERENCE

–40C, PF = 1

+85C, PF = 1

CURRENT – A

Typical Performance Characteristics–

TPC 4. Error as a % of Reading

ADE7759

TPC 2. Error as a % of Reading

0.5

0.4

0.3

0.2

0.1

0.0

ERROR – %

–0.1

–0.2

–0.3

–0.4

–0.5

0.01

REV. A

+85C, PF = 1

FULL SCALE = 0.5V
GAIN = 4
INTEGRATOR OFF
INTERNAL REFERENCE

0.1 1 10 100

TPC 3. Error as a % of Reading

TPC 5. Error as a % of Reading

–40C, PF = 1

+25C, PF = 1

CURRENT – A

TPC 6. Error as a % of Reading

–9–

ADE7759

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

ERROR – %

–0.2

FULL SCALE = 0.5V

–0.3

GAIN = 4
INTEGRATOR OFF

–0.4

EXTERNAL REFERENCE

–0.5

0.01

TPC 7. Error as a % of Reading

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

ERROR – %

–0.2

FULL SCALE = 0.5V

–0.3

GAIN = 4
INTEGRATOR ON

–0.4

INTERNAL REFERENCE

–0.5

0.01

TPC 8. Error as a % of Reading

–40C, PF = 1

+25C, PF = 1

+85C, PF = 1

0.1 1 10 100
CURRENT – A

–40C, PF = 1

+25C, PF = 1

+85C, PF = 1

0.1 1 10 100
CURRENT – A

–0.1

ERROR – %

–0.2

–0.3

–0.4

–0.5

ERROR – %

–0.1

–0.3

–0.5

0.5

0.4

0.3

0.2

0.1

0.0

0.01

+85C, PF = 0.5

+25C, PF = 1

–40C, PF = 0.5

+25C, PF = 0.5

0.1 1 10 100
CURRENT – A

TPC 10. Error as a % of Reading

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

+25C, PF = 1

0.01

–40C, PF = 0.5

+85C, PF = 0.5

+25C, PF = 0.5

0.1 1 10 100
CURRENT – A

TPC 11. Error as a % of Reading

FULL SCALE = 0.5V
GAIN = 4
INTEGRATOR OFF
EXTERNAL REFERENCE

FULL SCALE = 0.5V
GAIN = 4
INTEGRATOR ON
INTERNAL REFERENCE

0.5

0.4

0.3

0.2

0.1

0.0

–0.1

ERROR – %

–0.2

–0.3

–0.4

–0.5

0.01

FULL SCALE = 0.5V
GAIN = 4
INTEGRATOR ON

–40C, PF = 1

0.1 1 10 100
CURRENT – A

EXTERNAL REFERENCE

+25C, PF = 1

+85C, PF = 1

TPC 9. Error as a % of Reading

–10–

1.5

1.3

1.1

0.9

0.7

0.5

0.3

ERROR – %

+25C, PF = 1

0.1

–0.1

–0.3

–0.5

0.01 0.1 1 10 100

+85C, PF = 0.5

CURRENT – A

FULL SCALE = 0.5V
GAIN = 4

INTEGRATOR ON
EXTERNAL REFERENCE

–40C, PF = 0.5

+25C, PF = 0.5

TPC 12. Error as a % of Reading

REV. A

ADE7759

Test Circuits

I

110V

CT TURN RATIO = 1800:1
CHANNEL 2 GAIN = 1

GAIN (CH1) RB

10F10F

1k

33nF

RB

1k

33nF

1k 33nF

600k

33nF

1k

100nF

10F

1

10

4

2.5

V

DD

100nF 100nF

AV

DDDVDD

V1P

V1N

V2N

V2P

REF

U1

ADE7759

CLKOUT

IN/OUT

AGND DGND

RESET

DIN

DOUT

SCLK

CS

CLKIN

IRQ

SAG

ZX

CF

TO SPI BUS
(USED ONLY FOR
CALIBRATION)

22pF

U3

PS2501-1

22pF

TO
FREQUENCY
COUNTER

Y1

3.58MHz

NOT CONNECTED

Test Circuit 1. Performance Curve (Integrator OFF)

ANALOG INPUTS

The ADE7759 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N are ±0.5 V. In addition, the maximum signal
level on analog inputs for V1P/V1N and V2P/V2N are ±0.5 V
with respect to AGND.

Each analog input channel has a PGA (Programmable Gain
Amplifier) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see
Figure 5. Bits 0 to 2 select the gain for the PGA in Channel 1 and
the gain selection for the PGA in Channel 2 is made via Bits 5
to 7. Figure 4 shows how a gain selection for Channel 1
is made using the gain register.

GAIN[7:0]

GAIN (K)
SELECTION

V1P

V

IN

V1N

CH1OS[7:0]
BIT 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION

BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT ON)

K  V

IN

+

OFFSET ADJUST
(50mV)

Figure 4. PGA in Channel 1

V

DD

I

di/dt CURRENT
SENSOR

110V

CHANNEL 1 GAIN = 4
CHANNEL 2 GAIN = 1

10F10F

100 1k

33nF 33nF

100 1k

33nF

1k

600k

1k

10F

100nF 100nF

AV

DDDVDD

V1P

33nF

33nF

33nF

100nF

V1N

ADE7759

V2N

V2P

REF

IN/OUT

AGND DGND

U1

RESET

DIN

DOUT

SCLK

CS

CLKOUT

CLKIN

IRQ

SAG

ZX

CF

TO SPI BUS
(USED ONLY FOR
CALIBRATION)

22pF

U3

PS2501-1

22pF

TO
FREQUENCY
COUNTER

Y1

3.58MHz

NOT CONNECTED

Test Circuit 2. Performance Curve (Integrator ON)

In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 5. As
mentioned previously the maximum differential input voltage is

0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or

0.125 V. This is achieved by adjusting the ADC reference—see
Reference Circuit section. Table I summarizes the maximum
differential input signal level on Channel 1 for the various ADC
range and gain selections.

Table I. Maximum Input Signal Levels for Channel 1

Max Signal ADC Input Range Selection
Channel 1 0.5 V 0.25 V 0.125 V

0.5 V Gain = 1

0.25 V Gain = 2 Gain = 1

0.125 V Gain = 4 Gain = 2 Gain = 1

0.0625 V Gain = 8 Gain = 4 Gain = 2

0.0313 V Gain = 16 Gain = 8 Gain = 4

0.0156 V Gain = 16 Gain = 8

0.00781 V Gain = 16

CHANNEL 1 AND CHANNEL 2 PGA CONTROL

PGA 2 GAIN SELECT
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16

*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

GAIN REGISTER*

ADDR:
0AH

PGA 1 GAIN SELECT
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16

CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V

REV. A

Figure 5. Analog Gain Register

–11–