Analog Devices ADE7757EB, ADE7757ARN Datasheet
PRELIMINARY TECHNICAL DATA
Energy Metering IC
a
Preliminary Technical Data
FEATURES
On Chip Oscillator as clock source
High Accuracy, Supports 50 Hz/60 Hz IEC 521/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
The ADE7757 Supplies
Average Real Power
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for
Calibration and Supplies
Instantaneous Real Power
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ⴞ 8% (30 ppm/ⴗC Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
AC Input only
GENERAL DESCRIPTION
The ADE7757 is a high accuracy electrical energy measurement IC. It is a pin reduction version of AD7755
with an enhancement of a precise oscillator circuit that
serves as a clock source to the chip. The ADE7757
eliminates the cost of an external crystal or resonator,
thus reducing the overall cost of a meter built with this
IC. The chip directly interfaces with shunt resistor and
only operates with AC input.
on the
with Integrated Oscillator
ADE7757*
The ADE7757 specifications surpass the accuracy requirements as quoted in the IEC1036 standard. Due to the
similarity between the ADE7757 and AD7755, the Application Note AN-559 can be used as a basis for a description of an IEC1036 low cost watt-hour meter reference
design.
The only analog circuitry used in the ADE7757 is in the
sigma-delta ADCs and reference circuit. All other signal
processing (e.g., multiplication and filtering) is carried
out in the digital domain. This approach provides superior
stability and accuracy over time and extreme environmental conditions.
The ADE7757 supplies average real power information on
the low frequency outputs F1 and F2. These outputs may
be used to directly drive an electromechanical counter or
interface with an MCU. The high frequency CF logic
output, ideal for calibration purposes, provides instantaneous real power information.
The ADE7757 includes a power supply monitoring circuit
on the V
mode until the supply voltage on V
mately 4 V. If the supply falls below 4 V, the ADE7757
will also reset and the F1, F2 and CF outputs will be in
their non-active modes.
Internal phase matching circuitry ensures that the voltage
and current channels are phase matched while the HPF in
the current channel eliminates dc offsets. An internal noload threshold ensures that the ADE7757 does not exhibit
creep when no load is present.
The ADE7757 is available in 16-lead SOIC narrow-body
package.
supply pin. The ADE7757 will remain in reset
DD
reaches approxi-
DD
FUNCTIONAL BLOCK DIAGRAM
V
AGND
DD
POWER
SUPPLY MONITOR
V2P
V2N
V1N
V1P
2.5V
REFERENCE
*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469; other pending.
4kV
REF
ADC
ADC
IN/OUT
...
110101
...
11011001
RCLKIN
...
CORRECTION
...
INTERNAL
OSCILLATOR
∆∑
∆∑
REV. PrC.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADE7757
MULTIPLIER
PHASE
Φ
RESERVED
DGND
SIGNAL
PROCESSING
BLOCK
LPF
HPF
DIGITAL-TO-FREQUENCY
CONVERTER
F1
CF
S1
SCF
S0
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, USA.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., February 2002
F2
PRELIMINARY TECHNICAL DATA
(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, r
T
to T
ADE7757–SPECIFICATIONS
MIN
= –40ⴗC to +85ⴗC)
MAX
Parameter Value Units Test Conditions/Comments
ACCURACY
1, 2
Measurement Error1 on Channel V1 Channel V2 with Full-Scale Signal (±165 mV),+25°C
TB D % Reading typ Over a Dynamic Range 500 to 1
Phase Error
1
Between Channels Line Frequency = 45 Hz to 65 Hz
V1 Phase Lead 37°
(PF = 0.8 Capacitive) ±0.1 Degrees(°) max
V1 Phase Lag 60°
(PF = 0.5 Inductive) ±0.1 Degrees(°) max
AC Power Supply Rejection
1
S0 = S1 = 1,
Output Frequency Variation (CF) TBD % Reading typ V1 = V2 = 100 mV rms, @50 Hz
DC Power Supply Rejection
1
Output Frequency Variation (CF)
TBD
Ripple on V
S0 = S1 = 1,
% Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
V
5 V ±250 mV
DD =
of 200 mV rms @ 100 Hz
DD
ANALOG INPUTS See A nalog Inputs Section
Channel V1 Maximum Signal Level ± 30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level ±165 mV m ax V2N and V2P to AGND
Input Impedance (DC) TBD kΩ min
Bandwidth (–3 dB) 7 kHz typ
ADC Offset Error
Frequency Output Error
Gain Error
1, 2
1
1
±25 mV max See Terminology and Performance Graphs
TBD % Ideal typ External 2.5 V Reference,
±7 % Ideal typ External 2.5 V Reference, Gain = 1
r
= 5 kΩ 0.1% 5ppm/°C
CKLIN
r
= 5 kΩ 0.1% 5ppm/°C
CKLIN
V1 = 30 mV DC, V2 = 165 mV dc
V1 = 30 mV dc, V2 = 165 mV dc
REFERENCE INPUT
REF
Input Voltage Range 2.7 V max 2.5 V + 8%
IN/OUT
2.3 V min 2.5 V – 8%
Input Impedance TBD kΩ min
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.5 V
Reference Error ±200 mV ma x
Temperature Coefficient 30 ppm/°C typ
ppm/°C max
LOGIC INPUTS
3
SCF, S0, S1,
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C
LOGIC OUTPUTS
INH
INL
IN
IN
3
2.4 V min VDD = 5 V ± 5%
0.8 V max VDD = 5 V ± 5%
±3 µA max Typically 10 nA, VIN = 0 V to V
10 pF max
F1 and F2
Output High Voltage, V
Output Low Voltage, V
OL
OH
4.5 V min V
0.5 V max V
I
SOURCE
DD
I
SINK
DD
= 10 mA
= 5 V
= 10 mA
= 5 V
CF
I
Output High Voltage, V
Output Low Voltage, V
OL
OH
4 V min V
SOURCE
DD
I
SINK
= 5 mA
= 5 V
= 5 mA
0.5 V max VDD = 5 V
POWER SUPPLY For Specified Performance
V
DD
4.75 V min 5 V – 5%
5.25 V max 5 V + 5%
I
DD
NOTES
1
See Terminology Section for explanation of specifications.
2
See Plots in Typical Performance Graphs.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TBD TBD TBD
–2–
= 5 kΩ 0.1% 5ppm/°C,
CKLIN
DD
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
TIMING CHARACTERISTICS
1, 2
(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, r
T
to T
MIN
= –40ⴗC to +85ⴗC)
MAX
Parameter A, B Versions Units Test Conditions/Comments
3
t
1
t
2
t
3
3, 4
t
4
t
5
t
6
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4
The CF pulse is always 18 µs in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.
550 ms F1 and F2 Pulsewidth (Logic Low)
See Table II sec Output Pulse Period. See Transfer Function Section
1/2 t
2
sec Time Between F1 Falling Edge and F2 Falling Edge
180 ms CF Pulsewidth (Logic High)
See Table III sec CF Pulse Period. See Transfer Function Section
TB D sec Minimum Time Between F1 and F2 Pulse
t
1
F1
F2
t
CF
.t
6
.t
2
.t
3
.t
4
5
= 5 kΩ 0.1% 5ppm/°C,
CKLIN
Figure 1. Timing Diagram for Frequency Outputs
ORDERING GUIDE
Model Package Description Package Options
ADE7757ARN SOIC narrow-body RN-16
EVAL-ADE7757EB Evaluation Board Evaluation Board
REV. PrC.
–3–
ADE7757
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
Analog Input Voltage to AGND
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . . –0.3 V to V
Digital Input Voltage to DGND . . . . . –0.3 V to V
Digital Output Voltage to DGND . . . . –0.3 V to V
+ 0.3 V
DD
+ 0.3 V
DD
+ 0.3 V
DD
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C
16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350mW
Thermal Impedance** . . . . . . . . . . . . . . . . . 124.9°C/W
θ
JA
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
**JEDEC 1S Standard (2 layer) Board Data
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADE7757 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TERMINOLOGY
ADC OFFSET ERROR
This refers to the small dc signal (offset) associated with the
MEASUREMENT ERROR
The error associated with the energy measurement made by the
ADE7757 is defined by the following formula:
−
Error
=
7757
EnergyTrue
EnergyTrueADEbyregisteredEnergy
×
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power calculation is not affected by this offset.
FREQUENCY OUTPUT ERROR
%% 100
The frequency output error of the ADE7757 is defined as
the difference between the measured output frequency (mi-
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel (Channel
V1) has a phase lead response. To offset this phase response
and equalize the phase response between channels, a phase
correction network is also placed in Channel V1. The phase
correction network matches the phase to within ±0.1° over a
range of 45 Hz to 65 Hz and ±0.2° over a range 40 Hz to 1
kHz. See Figures 19 and 20.
POWER SUPPLY REJECTION
This quantifies the ADE7757 measurement error as a percentage of reading when the power supplies are varied.
nus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7757 transfer function—see Transfer Function section.
GAIN ERROR
The gain error of the ADE7757 is defined as the difference between the measured output frequency (minus the
offset) and the ideal output frequency. It is measured with
a gain of 1 in channel V1. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7757 transfer function—see Transfer Function section.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see Measurement Error definition.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. PrC.
PRELIMINARY TECHNICAL DATA
ADE7757
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1V
DD
2,3 V2P, V2N Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential
4, 5 V1N, V1P Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage
6 AGND This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and
7 REF
IN/OUT
8 S C F Select Calibration Frequency. This logic input is used to select the frequency on the calibra-
9,10 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-fre-
11 RCLKIN To enable the internal oscillator as a clock source to the chip, a precise 5 kΩ resistor must be
12 RESERVED Reserved pin. No load should be connected to this pin.
13 DGND This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier,
14 C F Calibration Frequency Logic Output. The CF logic output provides instantaneous real power
15,16 F2,F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic
Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The
supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
input pair. The maximum differential input voltage is ±165 mV for specified operation. The
maximum signal level at these pins is ±165 mV with respect to AGND. Both inputs have
internal ESD protection circuitry and an overvoltage of ±6 V can also be sustained on these
inputs without risk of permanent damage.
inputs with a maximum signal level of ±30 mV with respect to pin V1N for specified operation. The maximum signal level at this pin is ±165 mV with respect to AGND. Both inputs
have internal ESD protection circuitry and in addition an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground
plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and
voltage sensors, etc. For accurate noise suppression, the analog ground plane should only be
connected to the digital ground plane at one point. A star ground configuration will help to
keep noisy digital currents away from the analog circuits.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external
reference source may also be connected at this pin. In either case this pin should be
decoupled to AGND with a 1 µF tantalum capacitor and 100 nF ceramic capacitor.
tion output CF. Table III shows calibration frequencies selection.
quency conversion. With this logic input, designers have greater flexibility when designing an
energy meter. See
Selecting a Frequency for an Energy Meter Application.Selecting a Frequency for an Energy Meter Application.
Selecting a Frequency for an Energy Meter Application.
Selecting a Frequency for an Energy Meter Application.Selecting a Frequency for an Energy Meter Application.
connected from this pin to DGND.
filters and digital-to-frequency converter. This pin should be tied to the digital ground plane
of the PCB. The digital ground plane is the ground reference for all digital circuitry, e.g.,
counters (mechanical and digital), MCUs and indicator LEDs. For accurate noise suppression the analog ground plane should only be connected to the digital ground plane at one
point only, e.g., a star ground.
information. This output is intended for calibration purposes. Also see SCF pin description.
outputs can be used to directly drive electromechanical counters and two phase stepper motors. See
Transfer Function.Transfer Function.
Transfer Function.
Transfer Function.Transfer Function.
REV. PrC.
PIN CONFIGURATION
SOIC-16nb Package
–5–
REF
V
DD
V2P
V2N
V1N
V1P
AGND
IN/OUT
SCF
1
2
3
4
ADE7757
TOP VIEW
5
(Not to Scale)
6
7
8
16
F1
15
F2
14
CF
13
DGND
12
RESERVED
11
RCLKIN
10
S0
9
S1
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