Analog Devices ADE7756 Datasheet

Active Energy Metering IC

FEATURES High Accuracy, Supports IEC 687/1036 Less than 0.1% Error over a Dynamic Range of 1000 to 1 An On-Chip User Programmable Threshold for Line

Voltage SAG Detection and PSU Supervisory

The ADE7756 Supplies Sampled Waveform Data

(20 Bits) and Active Energy (40 Bits) Digital Power, Phase and Input Offset Calibration An On-Chip Temperature Sensor (3C Typical after

Calibration) An SPI-Compatible Serial Interface A Pulse Output with Programmable Frequency An Interrupt Request Pin (IRQ) and Status Register

Provide Early Warning of Register Overflow and

Other Conditions Proprietary ADCs and DSP Provide High Accuracy

over Large Variations in Environmental Conditions

and Time Reference 2.4 V  8% (20 ppm/C Typical) with External

Overdrive Capability Single 5 V Supply, Low Power (25 mW Typical)

GENERAL DESCRIPTION

The ADE7756 is a high-accuracy electrical power measurement IC with a serial interface and a pulse output. The ADE7756 incorporates two second-order sigma-delta ADCs, reference circuitry, temperature sensor, and all the signal processing required to perform active power and energy measurement.

with Serial Interface

ADE7756*

The ADE7756 contains a sampled Waveform register and an Active Energy register capable of holding at least five seconds of accumulated power at full load. Data is read from the ADE7756 via the serial interface. The ADE7756 also provides a pulse output (CF) with a frequency that is proportional to the active power.

In addition to real power information, the ADE7756 also provides system calibration features, i.e., channel offset correction, phase calibration, and power calibration. The part also incorporates a detection circuit for short duration low voltage variations or sags. The voltage threshold level and the duration (in number of halfline cycles) of the variation are user programmable. An open drain logic output (SAG) goes active low when a sag event occurs.

A zero crossing output (ZX) produces an output that is synchronized to the zero crossing point of the line voltage. This output can be used to extract timing or frequency information from the line. The signal is also used internally to the chip in the calibration mode. This permits faster and more accurate calibration of the real power calculation. This signal is also useful for synchronization of relay switching with a voltage zero crossing, thus improving the relay life by reducing the risk of arcing.

The interrupt request output is an open drain, active low logic output. The IRQ output will become active when the accumulated real power register is half-full and also when the register overflows. A status register indicates the nature of the interrupt.

The ADE7756 is available in 20-lead DIP and 20-lead SSOP packages.

FUNCTIONAL BLOCK DIAGRAM

PGA

V1P

V1N

TEMP

SENSOR

V2P

V2N

2.4V

REFERENCE

AGND

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; other pending.

4k

REF

ADC

IN/OUT

RESET

MULTIPLIER

APGAIN[11:0]

LPF1

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DGND

HPF1

MULTIPLIER

PHCAL[5:0]



ADE7756 REGISTERS

AND

SERIAL INTERFACE

DIN

SCLK

DOUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

IRQ

LPF2

ADE7756

APOS[11:0]

CFDIV[11:0]

CLKIN

SAG

DFC

CLKOUT

ADE7756

TABLE OF CONTENTS

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

ADE7756–SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 3

TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6

TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8

PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8

POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8

ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13

LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14

Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14

INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the ADE7756 Interrupts with an MCU . . . . . . . . . 15

Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16

ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16

Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18

Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 20

ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 21

ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 22

Integration Times under Steady Load . . . . . . . . . . . . . . . 23

POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 23

ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 23

ENERGY CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . 24

CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24

Calculating the Average Active Power . . . . . . . . . . . . . . . 24

Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 24

Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 25

SUSPENDING THE ADE7756 FUNCTIONALITY . . . . 26

SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 29

Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Interrupt Status Register (04H)/Reset Interrupt

Status Register (05H) . . . . . . . . . . . . . . . . . . . . . . . . . . 31

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32

–2–

REV. 0

ADE7756

(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,

to T

SPECIFICATIONS

Parameter A Version B Version Unit Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth 14 14 kHz CLKIN = 3.579545 MHz Measurement Error1 on Channel 1 Channel 2 = 300 mV rms/60 Hz, Gain = 2

Channel 1 Range = 1 V Full Scale

Gain = 1 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 2 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 4 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 8 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 16 0.1 0.1 % typ Over a Dynamic Range 1000 to 1

Channel 1 Range = 0.5 V Full Scale

Channel 1 Range = 0.25 V Full Scale

Gain = 1 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 2 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 4 0.1 0.1 % typ Over a Dynamic Range 1000 to 1 Gain = 8 0.2 0.2 % typ Over a Dynamic Range 1000 to 1 Gain = 16 0.2 0.2 % typ Over a Dynamic Range 1000 to 1

Phase Error

AC Power Supply Rejection Output Frequency Variation (CF) 0.2 0.2 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16,

DC Power Supply Rejection

Output Frequency Variation (CF) ±0.3 ± 0.3 % typ Channel 1 = 20 mV rms/60 Hz, Gain = 16,

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels ±1 ±1 V max V1P, V1N, V2N and V2P to AGND Input Impedance (dc) 390 390 kΩ min Bandwidth 14 14 kHz CLKIN/256, CLKIN = 3.579545 MHz Gain Error

Channel 1

Channel 2 ±4 ±4 % typ V2 = 1 V dc

Gain Error Match

Channel 1

Channel 2 ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16

Offset Error

Channel 1 ±20 ± 20 mV max Range = 1 V, Gain = 1 Channel 2 ±20 ± 20 mV max Gain = 1

WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545 MHz/128 =

Channel 1 See Channel 1 Sampling

Signal-to-Noise Plus Distortion 62 62 dB typ 700 mV rms/60 Hz, Range = 1 V, Gain = 1 Bandwidth (–3 dB) 14 14 kHz CLKIN = 3.579545 MHz

Channel 2 See Channel 2 Sampling

Signal-to-Noise Plus Distortion 52 52 dB typ 300 mV rms/60 Hz, Gain = 2 Bandwidth (–3 dB) 156 156 Hz CLKIN = 3.579545 MHz

Between Channels ±0.05 ±0.05 ° max Line Frequency = 45 Hz to 65 Hz, HPF On

1, 2

Range = 1 V Full Scale ±4 ±4 % typ V1 = 1 V dc Range = 0.5 V Full Scale ±4 ±4 % typ V1 = 0.5 V dc Range = 0.25 V Full Scale ±4 ±4 % typ V1 = 0.25 V dc

Range = 1 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Range = 0.5 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16 Range = 0.25 V Full Scale ±0.3 ±0.3 % typ Gain = 1, 2, 4, 8, 16

MIN

= –40C to +85C, unless otherwise noted.)

MAX

AVDD = DVDD = 5 V + 175 mV rms/120 Hz

Range = 0.5 V Channel 2 = 175 mV rms/60 Hz, Gain = 4 AVDD = DVDD = 5 V ± 250 mV dc

Range = 0.5 V Channel 2 = 175 mV rms/60 Hz, Gain = 4

External 2.5 V Reference, Gain = 1 on Channel 1 and 2

External 2.5 V Reference

27.9 kSPS

REV. 0

–3–

ADE7756–SPECIFICATIONS

Parameter A Version B Version Unit Test Conditions/Comments

REFERENCE INPUT

REF

Input Capacitance 10 10 pF max

ON-CHIP REFERENCE Nominal 2.4 V at REF

Reference Error ±200 ± 200 mV max Load Current 10 10 µA max Output Impedance 4 4 kΩ min Temperature Coefficient ±20 ± 20 ppm/°C typ

CLKIN Note All Specifications CLKIN of 3.579545 MHz

Input Clock Frequency 10 10 MHz max

LOGIC INPUTS

RESET, DIN, SCLK, CLKIN and CS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

LOGIC OUTPUTS

SAG and IRQ Open Drain Outputs, 10 kΩ Pull-Up Resistor

Output High Voltage, V Output Low Voltage, V

ZX and DOUT

Output High Voltage, V Output Low Voltage, V

POWER SUPPLY For Specified Performance

NOTES

See Terminology section for explanation of specifications.

See plots in Typical Performance Characteristic curves.

See Analog Inputs section.

Specifications subject to change without notice

Input Voltage Range 2.6 2.6 V max 2.4 V + 8%

IN/OUT

2.2 2.2 V min 2.4 V – 8%

±80 ppm/°C max

1 1 MHz min

INH

INL

2.4 2.4 V min DVDD = 5 V ± 5%

0.8 0.8 V max DVDD = 5 V ± 5% ±3 ±3 µA max Typically 10 nA, VIN = 0 V to DV 10 10 pF max

4 4 V min I

0.4 0.4 V max I

4 4 V min I

0.4 0.4 V max I

4 4 V min I

0.4 0.4 V max I

4.75 4.75 V min 5 V – 5%

5.25 5.25 V max 5 V + 5%

4.75 4.75 V min 5 V – 5%

5.25 5.25 V max 5 V + 5% 3 3 mA max Typically 2.0 mA 4 4 mA max Typically 3.0 mA

SOURCE

= 0.8 mA

SINK

SOURCE

= 0.8 mA

SINK

SOURCE

= 7 mA

SINK

= 5 mA

IN/OUT

–4–

REV. 0

ADE7756

(AVDD = DVDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz

TIMING CHARACTERISTICS

Parameter A, B Versions Unit Test Conditions/Comments

Write Timing

Read Timing

NOTES

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V.

See timing diagram below and Serial Interface section of this data sheet.

Measured with the load circuit in Load Circuit for Timing Specifications and defined as the time required for the output to cross 0.8 V or 2.4 V.

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Load Circuit for Timing Specifications. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

Specifications subject to change without notice.

20 ns (min) CS falling edge to first SCLK falling edge. 150 ns (min) SCLK logic high pulsewidth. 150 ns (min) SCLK logic low pulsewidth. 10 ns (min) Valid Data Setup time before falling edge of SCLK. 5 ns (min) Data Hold time after SCLK falling edge.

6.4 µs (min) Minimum time between the end of data byte transfers. 4 µs (min) Minimum time between byte transfers during a serial write. 100 ns (min) CS Hold time after SCLK falling edge.

4 µs (min) Minimum time between read command (i.e., a write to Communication

4 µs (min) Minimum time between data byte transfers during a multibyte read. 30 ns (min) Data access time after SCLK rising edge following a write to the

100 ns (max) Bus relinquish time after falling edge of SCLK. 10 ns (min) 100 ns (max) Bus relinquish time after rising edge of CS. 10 ns (min)

1, 2

XTAL, T

to T

MIN

= –40C to +85C, unless otherwise noted.)

MAX

Communications Register.

200A

SCLK

DIN

SCLK

DIN

DOUT

OUTPUT

50pF

1.6mA

2.1V

Figure 1. Load Circuit for Timing Specifications

1 DB0 DB7 DB0

A4 A3 A2 A1 A0 DB7

COMMAND BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 2. Serial Write Timing

A4 A3 A2 A1 A0000

DB7

MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTECOMMAND BYTE

DB0 DB7 DB0

Figure 3. Serial Read Timing

REV. 0

–5–

ADE7756

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND

, V1N, V2P and V2N . . . . . . . . . . . . . . . . . . –6 V to +6 V

Reference Input Voltage to AGND . . . –0.3 V to AV Digital Input Voltage to DGND . . . –0.3 V to DV Digital Output Voltage to DGND . . . –0.3 V to DV

+ 0.3 V

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

20-Lead Plastic DIP, Power Dissipation . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260°C

20-Lead SSOP, Power Dissipation . . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7756 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Package Description Package Option

ADE7756AN Plastic DIP N-20 ADE7756BN Plastic DIP N-20 ADE7756ARS Shrink Small Outline Package in Tubes RS-20 ADE7756ARSRL Shrink Small Outline Package in Tubes RS-20 ADE7756BRS Shrink Small Outline Package in Tubes RS-20 ADE7756BRSRL Shrink Small Outline Package in Reel RS-20 EVAL-ADE7756EB ADE7756 Evaluation Board ADE7756AN-REF ADE7756 Reference Design

PIN CONFIGURATION

DIP and SSOP Packages

REF

RESET

V1P

V1N

V2N

V2P

AGND

IN/OUT

DGND

ADE7756

TOP VIEW

(Not to Scale)

–6–

DIN

DOUT

SCLK

CLKOUT

CLKIN

IRQ

SAG

REV. 0

ADE7756

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 RESET Reset Pin for the ADE7756. A logic low on this pin will hold the ADCs and digital circuitry (including

the Serial Interface) in a reset condition.

2DVDDDigital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7756.

The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

3AV

4, 5 V1P, V1N Analog Inputs for Channel 1. This channel is intended for use with the current transducer. These

6, 7 V2N, V2P Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These

8 AGND This pin provides the ground reference for the analog circuitry in the ADE7756, i.e., ADCs and refer-

9 REF

10 DGND This provides the ground reference for the digital circuitry in the ADE7756, i.e., multiplier, filters, and

11 CF Calibration Frequency Logic Output. The CF logic output gives Active Power information. This out-

12 ZX Voltage Waveform (Channel 2) Zero Crossing Output. This output toggles logic high and low at the

13 SAG This open drain logic output goes active low when either no zero crossings are detected or a low volt-

14 IRQ Interrupt Request Output. This is an active low open drain logic output. Maskable interrupts include:

15 CLKIN Master clock for ADCs and digital signal processing. An external clock can be provided at this logic

16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source

IN/OUT

Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7756. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs in this data sheet show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

inputs are fully differential voltage inputs with maximum differential input signal levels of ±1 V, ±0.5 V and ±0.25 V, depending on the full-scale selection. See Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±1 V. Both inputs have internal ESD protection circuitry and in addition an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.

inputs are fully differential voltage inputs with a maximum differential signal level of ±1 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±1 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.

ence. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. In order to keep ground noise around the ADE7756 to a minimum, the quiet ground plane should only be connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane—see Applications Information section.

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF ceramic capacitor.

digital-to-frequency converter. Because the digital return currents in the ADE7756 are small, it is acceptable to connect this pin to the analog ground plane of the system—see Applications Information section. However, high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance.

put is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDIV Register—see Energy To Frequency Conversion section.

zero crossing of the differential signal on Channel 2—see Zero Crossing Detection section.

age threshold (Channel 2) is crossed for a specified duration. See Line Voltage Sag Detection section.

Active Energy Register roll-over, Active Energy Register at half level, and arrivals of new waveform samples—see Interrupts section.

input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7756. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to crystal manufacturers data sheet for load capacitance requirements.

for the ADE7756. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.

REV. 0

–7–

ADE7756

Pin No. Mnemonic Description

17 CS Chip Select. Part of the 4-Wire SPI Serial Interface. This active low logic input allows the ADE7756

to share the serial bus with several other devices—see Serial Interface section.

18 SCLK Serial Clock Input for the Synchronous Serial Interface. All Serial data transfers are synchronized to

this clock. See Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, e.g., opto-isolator outputs.

19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This

logic output is normally in a high impedance state unless it is driving data onto the serial data bus— see Serial Interface section.

20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see

Serial Interface section.

TERMINOLOGY

MEASUREMENT ERROR

The error associated with the energy measurement made by the ADE7756 is defined by the following formula:

Percentage Error =



Energy by ADE True Energy

 

PHASE ERROR BETWEEN CHANNELS

The HPF (High-Pass Filter) in Channel 1 has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in Channel 1. The phase correction network ensures a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2° over a range 40 Hz to 1 kHz.

POWER SUPPLY REJECTION

This quantifies the ADE7756 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see Measurement Error definition above.

For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of reading.

Registered 7756

True Energy

 



100–%

ADC OFFSET ERROR

This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection —see Typical Performance Characteristics. However, when HPF1 is switched on the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets may be removed by performing an offset calibration—see Analog Inputs section.

GAIN ERROR

The gain error in the ADE7756 ADCs is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code—see Channel 1 ADC and Channel 2 ADC section. It is measured for each of the input ranges on Channel 1 (1 V, 0.5 V and 0.25 V ). The difference is expressed as a percentage of the ideal code.

GAIN ERROR MATCH

The Gain Error Match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a percentage of the output ADC code obtained under a gain of 1. This gives the gain error observed when the gain selection is changed from 1 to 2, 4, 8, or 16.

–8–

REV. 0

Typical Performance Characteristics–ADE7756

0.50

0.40

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

PF = 1 GAIN = 1 ON-CHIP REFERENCE

0.10 1.0 10.0 100.0

–40C

+85C

+25C

AMPS

TPC 1. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 1)

0.50 PF = 1 GAIN = 2

0.40 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10 1.0 10.0 100.0

–40C

+85C

+25C

AMPS

TPC 2. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 2)

0.50

0.40

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

PF = 0.5 GAIN = 1 ON-CHIP REFERENCE

0.10 1.0 10.0 100.0

–40C, PF = 0.5

+85C, PF = 0.5

+25C, PF = 0.5

+25C, PF = 1.0

AMPS

TPC 4. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 1)

0.50 PF = 0.5

0.40

GAIN = 2 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10 1.0 10.0 100.0

–40C, PF = 0.5

+25C, PF = 1.0

+85C, PF = 0.5

+25C, PF = 0.5

AMPS

TPC 5. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 2)

0.50 PF = 1 GAIN = 4

0.40

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

ON-CHIP REFERENCE

0.10 1.0 10.0 100.0

–40C

+85C

+25C

AMPS

TPC 3. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 4)

REV. 0

0.50 PF = 0.5

0.40

GAIN = 4 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10 1.0 10.0 100.0

–40C, PF = 0.5

+85C, PF = 0.5

+25C, PF = 1.0

+25C, PF = 0.5

AMPS

TPC 6. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 4)

–9–

ADE7756

0.50 PF = 1 GAIN = 8

0.40 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10 1.0 10.0 100.0

+85C

–40C

+25C

AMPS

TPC 7. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 8)

0.50 PF = 1 GAIN = 16

0.40 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

0.10 1.0 10.0 100.0

+85C

–40C

+25C

AMPS

TPC 8. Error as a % of Reading (Power Factor = 1, Internal Reference, Gain = 16)

0.50 PF = 0.5

0.40

GAIN = 8 ON-CHIP REFERENCE

0.30

+25C, PF = 1.0

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

–40C, PF = 0.5

0.10 1.0 10.0 100.0

+85C, PF = 0.5

+25C, PF = 0.5

AMPS

TPC 10. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 8)

0.50 PF = 0.5

0.40

GAIN = 16 ON-CHIP REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

+85C, PF = 0.5

+25C, PF = 1.0

+25C, PF = 0.5

0.10 1.0 10.0 100.0

–40C, PF = 0.5

AMPS

TPC 11. Error as a % of Reading (Power Factor = 0.5, Internal Reference, Gain = 16)

0.50 PF = 1 GAIN = 1

0.40 EXTERNAL REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

+85C

+25C

–40C

0.10 1.0 10.0 100.0 AMPS

TPC 9. Error as a % of Reading (Power Factor = 1, External Reference, Gain = 1)

–10–

0.50 PF = 1

0.40

GAIN = 2 EXTERNAL REFERENCE

0.30

0.20

0.10

% ERROR

–0.10

–0.20

–0.30

–0.40

–0.50

0.01

+25C

0.10 1.0 10.0 100.0

+85C

–40C

AMPS

TPC 12. Error as a % of Reading (Power Factor = 1, External Reference, Gain = 2)

REV. 0

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